From cd5848976ed36e1b0b2a1bdbd9e4d230fac72803 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 26 Nov 2019 13:57:34 +0200 Subject: [PATCH] axi_adc_trigger: Change out hold counter width Chance out hold_counter width form 17 to 20 bits. Out hold period max ~ 20 ms. Default out hold period 2 ms. --- library/axi_adc_trigger/axi_adc_trigger.v | 14 +++++++------- library/axi_adc_trigger/axi_adc_trigger_reg.v | 18 ++++++++++-------- 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/library/axi_adc_trigger/axi_adc_trigger.v b/library/axi_adc_trigger/axi_adc_trigger.v index 2af02c87f..baf884216 100644 --- a/library/axi_adc_trigger/axi_adc_trigger.v +++ b/library/axi_adc_trigger/axi_adc_trigger.v @@ -129,7 +129,7 @@ module axi_adc_trigger #( wire [31:0] trigger_delay; wire [31:0] trigger_holdoff; - wire [31:0] trigger_out_hold_pins; + wire [19:0] trigger_out_hold_pins; wire signed [DW:0] data_a_cmp; wire signed [DW:0] data_b_cmp; @@ -182,8 +182,8 @@ module axi_adc_trigger #( reg trig_o_hold_0 = 1'b0; reg trig_o_hold_1 = 1'b0; - reg [16:0] trig_o_hold_cnt_0 = 17'd0; - reg [16:0] trig_o_hold_cnt_1 = 17'd0; + reg [19:0] trig_o_hold_cnt_0 = 20'd0; + reg [19:0] trig_o_hold_cnt_1 = 20'd0; reg trigger_adc_a; reg trigger_adc_b; @@ -258,16 +258,16 @@ module axi_adc_trigger #( always @(posedge clk) begin // trigger_o[0] hold start - if (trig_o_hold_cnt_0 != 17'd0) begin - trig_o_hold_cnt_0 <= trig_o_hold_cnt_0 - 17'd1; + if (trig_o_hold_cnt_0 != 20'd0) begin + trig_o_hold_cnt_0 <= trig_o_hold_cnt_0 - 20'd1; end else if (trig_o_hold_0 != trigger_o_m[0]) begin trig_o_hold_cnt_0 <= trigger_out_hold_pins; trig_o_hold_0 <= trigger_o_m[0]; end // trigger_o[1] hold start - if (trig_o_hold_cnt_1 != 17'd0) begin - trig_o_hold_cnt_1 <= trig_o_hold_cnt_1 - 17'd1; + if (trig_o_hold_cnt_1 != 20'd0) begin + trig_o_hold_cnt_1 <= trig_o_hold_cnt_1 - 20'd1; end else if (trig_o_hold_1 != trigger_o_m[1]) begin trig_o_hold_cnt_1 <= trigger_out_hold_pins; trig_o_hold_1 <= trigger_o_m[1]; diff --git a/library/axi_adc_trigger/axi_adc_trigger_reg.v b/library/axi_adc_trigger/axi_adc_trigger_reg.v index d8dc9dbec..9338ab948 100644 --- a/library/axi_adc_trigger/axi_adc_trigger_reg.v +++ b/library/axi_adc_trigger/axi_adc_trigger_reg.v @@ -63,7 +63,7 @@ module axi_adc_trigger_reg ( output [31:0] fifo_depth, output [31:0] trigger_delay, output [31:0] trigger_holdoff, - output [31:0] trigger_out_hold_pins, + output [19:0] trigger_out_hold_pins, output streaming, @@ -80,6 +80,8 @@ module axi_adc_trigger_reg ( output reg [31:0] up_rdata, output reg up_rack); + localparam DEFAULT_OUT_HOLD = 100000; // 1ms + // internal signals wire [ 9:0] config_trigger_i; @@ -103,7 +105,7 @@ module axi_adc_trigger_reg ( reg [31:0] up_fifo_depth = 32'h0; reg [31:0] up_trigger_delay = 32'h0; reg [31:0] up_trigger_holdoff = 32'h0; - reg [31:0] up_trigger_out_hold_pins = 32'h0; + reg [19:0] up_trigger_out_hold_pins = DEFAULT_OUT_HOLD; reg up_triggered = 1'h0; reg up_streaming = 1'h0; @@ -134,7 +136,7 @@ module axi_adc_trigger_reg ( up_triggered <= 1'd0; up_streaming <= 1'd0; up_trigger_holdoff <= 32'h0; - up_trigger_out_hold_pins <= 32'h0; + up_trigger_out_hold_pins <= DEFAULT_OUT_HOLD; end else begin up_wack <= up_wreq; if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin @@ -194,7 +196,7 @@ module axi_adc_trigger_reg ( up_trigger_holdoff <= up_wdata[31:0]; end if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin - up_trigger_out_hold_pins <= up_wdata[31:0]; + up_trigger_out_hold_pins <= up_wdata[19:0]; end end end @@ -228,7 +230,7 @@ module axi_adc_trigger_reg ( 5'h10: up_rdata <= up_trigger_delay; 5'h11: up_rdata <= {31'h0,up_streaming}; 5'h12: up_rdata <= up_trigger_holdoff; - 5'h13: up_rdata <= up_trigger_out_hold_pins; + 5'h13: up_rdata <= {12'h0,up_trigger_out_hold_pins}; default: up_rdata <= 0; endcase end else begin @@ -237,7 +239,7 @@ module axi_adc_trigger_reg ( end end - up_xfer_cntrl #(.DATA_WIDTH(274)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(262)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_cntrl ({ up_streaming, // 1 @@ -255,7 +257,7 @@ module axi_adc_trigger_reg ( up_trigger_out_control, // 17 up_fifo_depth, // 32 up_trigger_holdoff, // 32 - up_trigger_out_hold_pins, // 32 + up_trigger_out_hold_pins, // 20 up_trigger_delay}), // 32 .up_xfer_done (), @@ -276,7 +278,7 @@ module axi_adc_trigger_reg ( trigger_out_control, // 17 fifo_depth, // 32 trigger_holdoff, // 32 - trigger_out_hold_pins, // 32 + trigger_out_hold_pins, // 20 trigger_delay})); // 32 endmodule