parent
d4126739b4
commit
cd6024b341
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@ -55,7 +55,7 @@ module data_offload_fsm #(
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output reg wr_resetn_out,
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input wr_valid_in,
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output wr_valid_out,
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output reg wr_ready,
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output wr_ready,
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output reg [WR_ADDRESS_WIDTH-1:0] wr_addr,
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input wr_last,
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input [WR_DATA_WIDTH/8-1:0] wr_tkeep,
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@ -260,11 +260,12 @@ module data_offload_fsm #(
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always @(posedge wr_clk) begin
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wr_ready_d <= wr_ready;
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// flush out the DMA if the transfer is bigger than the storage size
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wr_ready <= ((wr_fsm_state == WR_WRITE_TO_MEM) ||
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((wr_fsm_state == WR_WAIT_TO_END) && wr_ready_d && !(wr_valid_in && wr_last))) ? 1'b1 : 1'b0;
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end
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// flush out the DMA if the transfer is bigger than the storage size
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assign wr_ready = ((wr_fsm_state == WR_WRITE_TO_MEM) ||
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((wr_fsm_state == WR_WAIT_TO_END) && wr_valid_in && wr_ready_d && wr_full)) ? 1'b1 : 1'b0;
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// write control
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assign wr_valid_out = (wr_fsm_state == WR_WRITE_TO_MEM) & wr_valid_in;
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