diff --git a/library/Makefile b/library/Makefile index bab999d53..c347c001e 100644 --- a/library/Makefile +++ b/library/Makefile @@ -68,6 +68,7 @@ clean: $(MAKE) -C util_adcfifo clean $(MAKE) -C util_axis_fifo clean $(MAKE) -C util_axis_resize clean + $(MAKE) -C util_axis_upscale clean $(MAKE) -C util_bsplit clean $(MAKE) -C util_cdc clean $(MAKE) -C util_cic clean @@ -159,6 +160,7 @@ lib: $(MAKE) -C util_adcfifo $(MAKE) -C util_axis_fifo $(MAKE) -C util_axis_resize + $(MAKE) -C util_axis_upscale $(MAKE) -C util_bsplit $(MAKE) -C util_cdc $(MAKE) -C util_cic diff --git a/library/common/util_axis_upscale.v b/library/common/util_axis_upscale.v new file mode 100644 index 000000000..426ef2477 --- /dev/null +++ b/library/common/util_axis_upscale.v @@ -0,0 +1,96 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// + A simple AXI stream data upscale module, which can be used with devices +// with resolution which can not be aligned to a WORD (32 bits). Eg. 24 bits +// + It has the same control interface as the ad_datafmt module, which controls +// the data format inside a generic AXI converter core. +// + Supports multiple channels. Contains a single register stage. + +module util_axis_upscale # ( + + parameter NUM_OF_CHANNELS = 4, + parameter DATA_WIDTH = 24, + parameter UDATA_WIDTH = 32)( + + input clk, + input resetn, + + input s_axis_valid, + output reg s_axis_ready, + input [(NUM_OF_CHANNELS*DATA_WIDTH)-1:0] s_axis_data, + + output reg m_axis_valid, + input m_axis_ready, + output reg [(NUM_OF_CHANNELS*UDATA_WIDTH)-1:0] m_axis_data, + + input dfmt_enable, + input dfmt_type, + input dfmt_se); + + wire type_s; + wire signext_s; + wire sign_s; + wire [(NUM_OF_CHANNELS*UDATA_WIDTH)-1:0] data_out_s; + + localparam MSB_WIDTH = UDATA_WIDTH - DATA_WIDTH; + + assign type_s = dfmt_enable & dfmt_type; + assign signext_s = dfmt_enable & dfmt_se; + assign sign_s = signext_s & (type_s ^ s_axis_data[(DATA_WIDTH-1)]); + + genvar i; + generate + for (i=1; i <= NUM_OF_CHANNELS; i=i+1) begin + + assign data_out_s[(i*UDATA_WIDTH-1):(i*UDATA_WIDTH-MSB_WIDTH)] = {(MSB_WIDTH){sign_s}}; + assign data_out_s[((i-1)*UDATA_WIDTH+DATA_WIDTH-1)] = type_s ^ s_axis_data[(i*DATA_WIDTH-1)]; + assign data_out_s[((i-1)*UDATA_WIDTH+DATA_WIDTH-2):((i-1)*UDATA_WIDTH)] = s_axis_data[(i*DATA_WIDTH-2):((i-1)*DATA_WIDTH)]; + + end + endgenerate + + always @(posedge clk) begin + if (resetn == 1'b0) begin + m_axis_valid <= 1'b0; + s_axis_ready <= 1'b0; + m_axis_data <= {(NUM_OF_CHANNELS*UDATA_WIDTH){1'b0}}; + end else begin + m_axis_valid <= s_axis_valid; + s_axis_ready <= m_axis_ready; + m_axis_data <= data_out_s; + end + end + +endmodule diff --git a/library/util_axis_upscale/Makefile b/library/util_axis_upscale/Makefile new file mode 100644 index 000000000..e43e8fcef --- /dev/null +++ b/library/util_axis_upscale/Makefile @@ -0,0 +1,46 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/util_axis_upscale.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += util_axis_upscale_ip.tcl + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: util_axis_upscale.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +util_axis_upscale.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) util_axis_upscale_ip.tcl >> util_axis_upscale_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/util_axis_upscale/util_axis_upscale_ip.tcl b/library/util_axis_upscale/util_axis_upscale_ip.tcl new file mode 100644 index 000000000..0b4c7ed2d --- /dev/null +++ b/library/util_axis_upscale/util_axis_upscale_ip.tcl @@ -0,0 +1,32 @@ + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_axis_upscale +adi_ip_files util_axis_upscale [list \ + "$ad_hdl_dir/library/common/util_axis_upscale.v"] + +adi_ip_properties_lite util_axis_upscale + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"s_axis_valid" "TVALID"} \ + {"s_axis_ready" "TREADY"} \ + {"s_axis_data" "TDATA"} \ + } +adi_add_bus_clock "clk" "s_axis" "resetn" + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_valid" "TVALID"} \ + {"m_axis_ready" "TREADY"} \ + {"m_axis_data" "TDATA"} \ + } +ipx::associate_bus_interfaces -busif m_axis -clock s_axis_signal_clock [ipx::current_core] + +ipx::save_core [ipx::current_core] +