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axi_ad9361: sync dac_valid to adc_valid 

Sync the two valid signals to keep a fixed phase relationship between
the Rx ant Tx channels, this way avoiding +/- 1 sample differences
on the Tx-Rx latency between consecutive transfers.
main
Laszlo Nagy 2019-09-11 09:43:23 +01:00 committed by Laszlo Nagy
parent b174333fa2
commit cdaaa49a2a
2 changed files with 9 additions and 1 deletions
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6
library/axi_ad9361/axi_ad9361.v
View File

@ -252,6 +252,7 @@ module axi_ad9361 #(
wire dac_data_q0_s;
wire dac_data_i1_s;
wire dac_data_q1_s;
wire dac_sync_enable;
wire [12:0] up_adc_dld_s;
wire [64:0] up_adc_dwdata_s;
wire [64:0] up_adc_drdata_s;
@ -506,6 +507,7 @@ module axi_ad9361 #(
assign up_wack_tdd_s = 1'b0;
assign up_rack_tdd_s = 1'b0;
assign up_rdata_tdd_s = 32'b0;
assign dac_sync_enable = adc_valid_s;
end
endgenerate
@ -545,6 +547,9 @@ module axi_ad9361 #(
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_tdd_s),
.up_rack (up_rack_tdd_s));
assign dac_sync_enable = adc_valid_s || tdd_mode_s;
end
endgenerate
@ -673,6 +678,7 @@ module axi_ad9361 #(
.delay_clk (delay_clk),
.delay_rst (),
.delay_locked (delay_locked_s),
.dac_sync_enable (dac_sync_enable),
.dac_sync_in (dac_sync_in),
.dac_sync_out (dac_sync_out),
.dac_enable_i0 (dac_enable_i0),

4
library/axi_ad9361/axi_ad9361_tx.v
View File

@ -77,6 +77,7 @@ module axi_ad9361_tx #(
// master/slave
input dac_sync_enable,
input dac_sync_in,
output dac_sync_out,
@ -160,6 +161,7 @@ module axi_ad9361_tx #(
// master/slave
assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
assign dac_sync_out = dac_sync & dac_sync_enable;
always @(posedge dac_clk) begin
dac_data_sync <= dac_data_sync_s;
@ -371,7 +373,7 @@ module axi_ad9361_tx #(
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_out),
.dac_sync (dac_sync),
.dac_frame (),
.dac_clksel (dac_clksel),
.dac_par_type (),