diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v
index 82e236db3..e1af682ce 100644
--- a/library/axi_dacfifo/axi_dacfifo.v
+++ b/library/axi_dacfifo/axi_dacfifo.v
@@ -118,6 +118,7 @@ module axi_dacfifo (
   parameter   AXI_ADDRESS = 32'h00000000;
   parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
   parameter   AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
+  parameter   BYPASS_EN = 1;
 
   // dma interface
 
@@ -195,13 +196,18 @@ module axi_dacfifo (
   wire                                axi_rd_ready_s;
   wire                                axi_rd_valid_s;
   wire                                axi_xfer_req_s;
+  wire    [(AXI_DATA_WIDTH-1):0]      dac_rd_data_s;
+  wire                                dac_rd_ready_s;
+  wire                                dac_rd_valid_s;
   wire    [31:0]                      axi_last_addr_s;
   wire    [31:0]                      dma_last_addr_s;
 
   wire    [(DAC_DATA_WIDTH-1):0]      dac_data_s;
   wire                                dma_ready_s;
 
-  // instantiations
+  wire                                dma_valid_bp_s;
+  wire    [(AXI_DATA_WIDTH-1):0]      dma_data_bp_s;
+  wire                                dma_ready_bp_s;
 
   axi_dacfifo_wr #(
     .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
@@ -287,22 +293,48 @@ module axi_dacfifo (
     .DAC_DATA_WIDTH (DAC_DATA_WIDTH)
   ) i_dac (
     .axi_clk (axi_clk),
-    .axi_dvalid (axi_rd_valid_s),
-    .axi_ddata (axi_rd_data_s),
+    .axi_dvalid (dac_rd_valid_s),
+    .axi_ddata (dac_rd_data_s),
     .axi_dready (axi_rd_ready_s),
     .axi_xfer_req (axi_xfer_req_s),
     .dma_last_addr (dma_last_addr_s),
     .dac_clk (dac_clk),
     .dac_rst (dac_rst),
     .dac_valid (dac_valid),
-    .dac_data (dac_data_s),
+    .dac_data (dac_data),
     .dac_xfer_out (dac_xfer_out),
     .dac_dunf (dac_dunf));
 
-  // output logic
+  // bypass logic
 
-  assign dac_data = (dac_fifo_bypass) ? dma_data : dac_data_s;
-  assign dma_ready = (dac_fifo_bypass) ? dac_valid : dma_ready_s;
+  generate if (BYPASS_EN == 1) begin
+
+    util_axis_resize #(
+      .MASTER_DATA_WIDTH (AXI_DATA_WIDTH),
+      .SLAVE_DATA_WIDTH (DMA_DATA_WIDTH)
+    ) i_util_axis_resize (
+      .clk (axi_clk),
+      .resetn (axi_resetn),
+      .s_valid (dma_valid),
+      .s_ready (dma_ready_bp_s),
+      .s_data (dma_data),
+      .m_valid (dma_valid_bp_s),
+      .m_ready (axi_rd_ready_s),
+      .m_data (dma_data_bp_s)
+    );
+
+    assign  dac_rd_valid_s = (dac_fifo_bypass) ? dma_valid_bp_s : axi_rd_valid_s;
+    assign  dac_rd_data_s = (dac_fifo_bypass) ? dma_data_bp_s : axi_rd_data_s;
+    assign  dma_ready = (dac_fifo_bypass) ? dma_ready_bp_s : dma_ready_s;
+
+  end else begin
+
+    assign  dac_rd_valid_s = axi_rd_valid_s;
+    assign  dac_rd_data_s = axi_rd_data_s;
+    assign  dma_ready = dma_ready_s;
+
+  end
+  endgenerate
 
 endmodule
 
diff --git a/library/axi_dacfifo/axi_dacfifo_constr.xdc b/library/axi_dacfifo/axi_dacfifo_constr.xdc
index 55262bad7..8942ef3d9 100644
--- a/library/axi_dacfifo/axi_dacfifo_constr.xdc
+++ b/library/axi_dacfifo/axi_dacfifo_constr.xdc
@@ -15,3 +15,8 @@ set_false_path -from [get_cells *dac_* -hierarchical -filter {PRIMITIVE_SUBGROUP
 set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
   -to [get_cells *dac_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
 
+set_false_path -from [get_cells *dac_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
+  -to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
+  -to [get_cells *dac_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
+
diff --git a/library/axi_dacfifo/axi_dacfifo_ip.tcl b/library/axi_dacfifo/axi_dacfifo_ip.tcl
index 905139739..77c5b2acc 100644
--- a/library/axi_dacfifo/axi_dacfifo_ip.tcl
+++ b/library/axi_dacfifo/axi_dacfifo_ip.tcl
@@ -8,11 +8,12 @@ adi_ip_create axi_dacfifo
 adi_ip_files axi_dacfifo [list \
   "$ad_hdl_dir/library/common/ad_mem_asym.v" \
   "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
+  "$ad_hdl_dir/library/util_axis_resize/util_axis_resize.v" \
+  "axi_dacfifo_constr.xdc" \
   "axi_dacfifo_dac.v" \
   "axi_dacfifo_wr.v" \
   "axi_dacfifo_rd.v" \
-  "axi_dacfifo.v" \
-  "axi_dacfifo_constr.xdc" ]
+  "axi_dacfifo.v"]
 
 adi_ip_properties_lite axi_dacfifo
 adi_ip_constraints axi_dacfifo [list \