adrv9371x: Updated constraints for altera projects

main
Adrian Costina 2016-11-04 18:20:46 +02:00
parent 0dfbb0af11
commit ce3b6a2d3f
2 changed files with 16 additions and 16 deletions

View File

@ -8,33 +8,33 @@ derive_clock_uncertainty
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
-to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
-to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0k}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]
-to [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]
-to [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]

View File

@ -8,33 +8,33 @@ derive_clock_uncertainty
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
-to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
-to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]
-to [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]
-to [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]\
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]