adrv9371x: Updated constraints for altera projects
parent
0dfbb0af11
commit
ce3b6a2d3f
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@ -8,33 +8,33 @@ derive_clock_uncertainty
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
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-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_ctl_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
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-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0k}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]
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-to [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]
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-to [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
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-through [get_nets *altera_jesd204_tx_ctl_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]\
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]\
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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@ -8,33 +8,33 @@ derive_clock_uncertainty
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
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-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_ctl_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
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-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]
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-to [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]
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-to [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
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-through [get_nets *altera_jesd204_tx_ctl_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]\
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]\
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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