zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

up_dac_common: rename internal signals

main
Adrian Costina 2017-05-15 18:58:26 +03:00
parent cfcb269d38
commit ce4f9bf906
1 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
library/common/up_dac_common.v
View File

@ -68,7 +68,7 @@ module up_dac_common #(
input dac_status_ovf,
input dac_status_unf,
input [31:0] dac_clk_ratio,
output reg up_dac_ce,
output up_dac_ce,
// drp interface
@ -110,7 +110,8 @@ module up_dac_common #(
reg up_mmcm_preset = 'd1;
reg up_wack_int = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_dac_ce_int = 'd0;
reg up_dac_clk_enb_int = 'd0;
reg up_dac_clk_enb = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_dac_sync = 'd0;
@ -159,6 +160,7 @@ module up_dac_common #(
assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0;
assign up_dac_ce = up_dac_clk_enb_int;
// processor write interface
@ -166,12 +168,12 @@ module up_dac_common #(
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dac_ce <= 1'd1;
up_core_preset <= 1'd1;
up_mmcm_preset <= 1'd1;
up_wack_int <= 'd0;
up_scratch <= 'd0;
up_dac_ce_int <= 'd0;
up_dac_clk_enb_int <= 'd1;
up_dac_clk_enb <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_dac_sync <= 'd0;
@ -183,7 +185,7 @@ module up_dac_common #(
up_dac_frame <= 'd0;
up_dac_clksel <= 'd0;
end else begin
up_dac_ce <= ~up_dac_ce_int;
up_dac_clk_enb_int <= ~up_dac_clk_enb;
up_core_preset <= ~up_resetn;
up_mmcm_preset <= ~up_mmcm_resetn;
up_wack_int <= up_wreq_s;
@ -191,7 +193,7 @@ module up_dac_common #(
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_dac_ce_int <= up_wdata[2];
up_dac_clk_enb <= up_wdata[2];
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
@ -353,7 +355,7 @@ module up_dac_common #(
8'h01: up_rdata_int <= ID;
8'h02: up_rdata_int <= up_scratch;
8'h03: up_rdata_int <= CONFIG;
8'h10: up_rdata_int <= {29'd0, up_dac_ce_int, up_mmcm_resetn, up_resetn};
8'h10: up_rdata_int <= {29'd0, up_dac_clk_enb, up_mmcm_resetn, up_resetn};
8'h11: up_rdata_int <= {31'd0, up_dac_sync};
8'h12: up_rdata_int <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode,
up_dac_datafmt, 4'd0};