ultrasound: disconnected ADN4670 chips from SPI lines.
Connected everything to ground so that the the clock selected is 0 and all outputs are enabledmain
Adrian Costina
parent
fb5d212370
commit
cead3aaf86
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@ -1,8 +1,8 @@
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# usdrx1
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set spi_csn_i [create_bd_port -dir I -from 10 -to 0 spi_csn_i]
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set spi_csn_o [create_bd_port -dir O -from 10 -to 0 spi_csn_o]
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set spi_csn_i [create_bd_port -dir I -from 4 -to 0 spi_csn_i]
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set spi_csn_o [create_bd_port -dir O -from 4 -to 0 spi_csn_o]
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set spi_clk_i [create_bd_port -dir I spi_clk_i]
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set spi_clk_o [create_bd_port -dir O spi_clk_o]
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set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
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@ -15,8 +15,6 @@ set rx_sysref [create_bd_port -dir O rx_sysref]
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set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p]
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set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n]
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#set mlo_clk [create_bd_port -dir O mlo_clk]
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set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data]
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set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0]
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set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1]
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@ -94,8 +92,8 @@ set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_dma_interconnect
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set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_usdrx1_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {11}] $axi_usdrx1_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {16}] $axi_usdrx1_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {5}] $axi_usdrx1_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi
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# additions to default configuration
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@ -124,25 +122,25 @@ connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_u
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connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o]
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connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk]
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connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk]
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connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3]
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# connections (gt)
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connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p]
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connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n]
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connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync]
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connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref]
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connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p]
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connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n]
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connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync]
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connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref]
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# connections (adc)
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk_g]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_jesd/rx_core_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset]
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@ -181,7 +179,7 @@ connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core
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connect_bd_net -net axi_ad9671_dma_wr_en [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_wr_en]
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connect_bd_net -net axi_ad9671_dma_adc_data [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_data]
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connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf]
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connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2]
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connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2]
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# interconnect (cpu)
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@ -201,14 +199,14 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sy
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
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@ -217,14 +215,14 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESET
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn]
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# interconnect (gt es)
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@ -250,7 +248,7 @@ connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
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connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
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connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi]
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connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
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@ -259,7 +257,7 @@ connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn]
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn]
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# ila
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@ -39,20 +39,17 @@
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module usdrx1_spi (
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spi_fout_csn,
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spi_afe_csn,
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spi_clk_csn,
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spi_clk,
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spi_mosi,
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spi_miso,
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spi_fout_sdio,
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spi_afe_sdio,
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spi_clk_sdio);
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// 4 wire
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input [ 5:0] spi_fout_csn;
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input [ 3:0] spi_afe_csn;
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input spi_clk_csn;
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input spi_clk;
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@ -61,7 +58,6 @@ module usdrx1_spi (
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// 3 wire
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inout spi_fout_sdio;
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inout spi_afe_sdio;
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inout spi_clk_sdio;
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@ -73,16 +69,14 @@ module usdrx1_spi (
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// internal signals
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wire [ 2:0] spi_csn_3_s;
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wire [ 1:0] spi_csn_3_s;
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wire spi_csn_s;
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wire spi_enable_s;
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wire spi_fout_miso_s;
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wire spi_afe_miso_s;
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wire spi_clk_miso_s;
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// check on rising edge and change on falling edge
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assign spi_csn_3_s[2] = & spi_fout_csn;
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assign spi_csn_3_s[1] = & spi_afe_csn;
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assign spi_csn_3_s[0] = spi_clk_csn;
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assign spi_csn_s = & spi_csn_3_s;
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@ -111,15 +105,11 @@ module usdrx1_spi (
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end
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end
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assign spi_miso = ((spi_fout_miso_s & ~spi_csn_3_s[2]) |
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(spi_afe_miso_s & ~spi_csn_3_s[1]) |
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assign spi_miso = ((spi_afe_miso_s & ~spi_csn_3_s[1]) |
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(spi_clk_miso_s & ~spi_csn_3_s[0]));
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// io buffers
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assign spi_fout_miso_s = spi_fout_sdio;
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assign spi_fout_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
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assign spi_afe_miso_s = spi_afe_sdio;
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assign spi_afe_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
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@ -1,9 +1,9 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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//
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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@ -21,16 +21,16 @@
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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@ -171,7 +171,7 @@ module system_top (
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output spi_fout_enb_sysref;
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output spi_fout_enb_trig;
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output spi_fout_clk;
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inout spi_fout_sdio;
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output spi_fout_sdio;
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output [ 3:0] spi_afe_csn;
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output spi_afe_clk;
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inout spi_afe_sdio;
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@ -199,7 +199,7 @@ module system_top (
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// internal signals
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wire [10:0] spi_csn;
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||||
wire [ 4:0] spi_csn;
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||||
wire spi_clk;
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||||
wire spi_mosi;
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||||
wire spi_miso;
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||||
|
|
@ -236,26 +236,25 @@ module system_top (
|
|||
|
||||
// spi assignments
|
||||
|
||||
assign spi_fout_enb_clk = ~spi_csn[10:10];
|
||||
assign spi_fout_enb_mlo = ~spi_csn[ 9: 9];
|
||||
assign spi_fout_enb_rst = ~spi_csn[ 8: 8];
|
||||
assign spi_fout_enb_sync = ~spi_csn[ 7: 7];
|
||||
assign spi_fout_enb_sysref = ~spi_csn[ 6: 6];
|
||||
assign spi_fout_enb_trig = ~spi_csn[ 5: 5];
|
||||
assign spi_fout_enb_clk = 1'b0;
|
||||
assign spi_fout_enb_mlo = 1'b0;
|
||||
assign spi_fout_enb_rst = 1'b0;
|
||||
assign spi_fout_enb_sync = 1'b0;
|
||||
assign spi_fout_enb_sysref = 1'b0;
|
||||
assign spi_fout_enb_trig = 1'b0;
|
||||
assign spi_fout_sdio = 1'b0;
|
||||
assign spi_afe_csn = spi_csn[ 4: 1];
|
||||
assign spi_clk_csn = spi_csn[ 0: 0];
|
||||
assign spi_fout_clk = spi_clk;
|
||||
assign spi_fout_clk = 1'b0;
|
||||
assign spi_afe_clk = spi_clk;
|
||||
assign spi_clk_clk = spi_clk;
|
||||
|
||||
usdrx1_spi i_spi (
|
||||
.spi_fout_csn (spi_csn[10:5]),
|
||||
.spi_afe_csn (spi_csn[4:1]),
|
||||
.spi_clk_csn (spi_csn[0]),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi),
|
||||
.spi_miso (spi_miso),
|
||||
.spi_fout_sdio (spi_fout_sdio),
|
||||
.spi_afe_sdio (spi_afe_sdio),
|
||||
.spi_clk_sdio (spi_clk_sdio));
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue