From ced36f6159cf5774af358edef7e3680722ee2a78 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Thu, 21 Jul 2016 11:57:03 -0400
Subject: [PATCH] up-dac- support iq mode

---
 library/common/up_dac_channel.v | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/library/common/up_dac_channel.v b/library/common/up_dac_channel.v
index e42f2fc08..7cb96f3e7 100644
--- a/library/common/up_dac_channel.v
+++ b/library/common/up_dac_channel.v
@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -54,6 +52,7 @@ module up_dac_channel (
   dac_pat_data_1,
   dac_pat_data_2,
   dac_data_sel,
+  dac_iq_mode,
   dac_iqcor_enb,
   dac_iqcor_coeff_1,
   dac_iqcor_coeff_2,
@@ -106,6 +105,7 @@ module up_dac_channel (
   output  [15:0]  dac_pat_data_1;
   output  [15:0]  dac_pat_data_2;
   output  [ 3:0]  dac_data_sel;
+  output          dac_iq_mode;
   output          dac_iqcor_enb;
   output  [15:0]  dac_iqcor_coeff_1;
   output  [15:0]  dac_iqcor_coeff_2;
@@ -164,6 +164,7 @@ module up_dac_channel (
   reg     [ 7:0]  up_usr_datatype_bits = 'd0;
   reg     [15:0]  up_usr_interpolation_m = 'd0;
   reg     [15:0]  up_usr_interpolation_n = 'd0;
+  reg             up_dac_iq_mode = 'd0;
   reg             up_rack = 'd0;
   reg     [31:0]  up_rdata = 'd0;
   reg     [15:0]  up_dac_dds_scale_tc_1 = 'd0;
@@ -223,6 +224,7 @@ module up_dac_channel (
       up_usr_datatype_bits <= 'd0;
       up_usr_interpolation_m <= 'd0;
       up_usr_interpolation_n <= 'd0;
+      up_dac_iq_mode <= 'd0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
@@ -266,6 +268,9 @@ module up_dac_channel (
         up_usr_interpolation_m <= up_wdata[31:16];
         up_usr_interpolation_n <= up_wdata[15:0];
       end
+      if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha)) begin
+        up_dac_iq_mode <= up_wdata[0];
+      end
     end
   end
 
@@ -291,6 +296,7 @@ module up_dac_channel (
                               dac_usr_datatype_shift, dac_usr_datatype_total_bits,
                               dac_usr_datatype_bits};
           4'h9: up_rdata <= {dac_usr_interpolation_m, dac_usr_interpolation_n};
+          4'ha: up_rdata <= {31'd0, up_dac_iq_mode};
           default: up_rdata <= 0;
         endcase
       end else begin
@@ -331,10 +337,11 @@ module up_dac_channel (
 
   // dac control & status
 
-  up_xfer_cntrl #(.DATA_WIDTH(165)) i_xfer_cntrl (
+  up_xfer_cntrl #(.DATA_WIDTH(166)) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_data_cntrl ({ up_dac_iqcor_enb,
+    .up_data_cntrl ({ up_dac_iq_mode,
+                      up_dac_iqcor_enb,
                       up_dac_iqcor_coeff_tc_1,
                       up_dac_iqcor_coeff_tc_2,
                       up_dac_dds_scale_tc_1,
@@ -349,7 +356,8 @@ module up_dac_channel (
     .up_xfer_done (),
     .d_rst (dac_rst),
     .d_clk (dac_clk),
-    .d_data_cntrl ({  dac_iqcor_enb,
+    .d_data_cntrl ({  dac_iq_mode,
+                      dac_iqcor_enb,
                       dac_iqcor_coeff_1,
                       dac_iqcor_coeff_2,
                       dac_dds_scale_1,