up-dac- support iq mode
parent
3a1ecb7463
commit
ced36f6159
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@ -34,8 +34,6 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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`timescale 1ns/100ps
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@ -54,6 +52,7 @@ module up_dac_channel (
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dac_pat_data_1,
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dac_pat_data_1,
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dac_pat_data_2,
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dac_pat_data_2,
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dac_data_sel,
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dac_data_sel,
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dac_iq_mode,
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dac_iqcor_enb,
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dac_iqcor_enb,
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dac_iqcor_coeff_1,
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dac_iqcor_coeff_1,
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dac_iqcor_coeff_2,
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dac_iqcor_coeff_2,
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@ -106,6 +105,7 @@ module up_dac_channel (
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output [15:0] dac_pat_data_1;
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output [15:0] dac_pat_data_1;
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output [15:0] dac_pat_data_2;
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output [15:0] dac_pat_data_2;
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output [ 3:0] dac_data_sel;
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output [ 3:0] dac_data_sel;
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output dac_iq_mode;
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output dac_iqcor_enb;
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output dac_iqcor_enb;
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output [15:0] dac_iqcor_coeff_1;
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output [15:0] dac_iqcor_coeff_1;
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output [15:0] dac_iqcor_coeff_2;
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output [15:0] dac_iqcor_coeff_2;
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@ -164,6 +164,7 @@ module up_dac_channel (
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reg [ 7:0] up_usr_datatype_bits = 'd0;
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reg [ 7:0] up_usr_datatype_bits = 'd0;
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reg [15:0] up_usr_interpolation_m = 'd0;
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reg [15:0] up_usr_interpolation_m = 'd0;
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reg [15:0] up_usr_interpolation_n = 'd0;
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reg [15:0] up_usr_interpolation_n = 'd0;
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reg up_dac_iq_mode = 'd0;
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reg up_rack = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg [15:0] up_dac_dds_scale_tc_1 = 'd0;
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reg [15:0] up_dac_dds_scale_tc_1 = 'd0;
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@ -223,6 +224,7 @@ module up_dac_channel (
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up_usr_datatype_bits <= 'd0;
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up_usr_datatype_bits <= 'd0;
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up_usr_interpolation_m <= 'd0;
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up_usr_interpolation_m <= 'd0;
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up_usr_interpolation_n <= 'd0;
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up_usr_interpolation_n <= 'd0;
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up_dac_iq_mode <= 'd0;
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end else begin
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end else begin
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up_wack <= up_wreq_s;
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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@ -266,6 +268,9 @@ module up_dac_channel (
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up_usr_interpolation_m <= up_wdata[31:16];
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up_usr_interpolation_m <= up_wdata[31:16];
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up_usr_interpolation_n <= up_wdata[15:0];
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up_usr_interpolation_n <= up_wdata[15:0];
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end
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha)) begin
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up_dac_iq_mode <= up_wdata[0];
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end
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end
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end
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end
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end
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@ -291,6 +296,7 @@ module up_dac_channel (
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dac_usr_datatype_shift, dac_usr_datatype_total_bits,
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dac_usr_datatype_shift, dac_usr_datatype_total_bits,
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dac_usr_datatype_bits};
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dac_usr_datatype_bits};
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4'h9: up_rdata <= {dac_usr_interpolation_m, dac_usr_interpolation_n};
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4'h9: up_rdata <= {dac_usr_interpolation_m, dac_usr_interpolation_n};
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4'ha: up_rdata <= {31'd0, up_dac_iq_mode};
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default: up_rdata <= 0;
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default: up_rdata <= 0;
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endcase
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endcase
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end else begin
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end else begin
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@ -331,10 +337,11 @@ module up_dac_channel (
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// dac control & status
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// dac control & status
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up_xfer_cntrl #(.DATA_WIDTH(165)) i_xfer_cntrl (
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up_xfer_cntrl #(.DATA_WIDTH(166)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_dac_iqcor_enb,
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.up_data_cntrl ({ up_dac_iq_mode,
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up_dac_iqcor_enb,
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up_dac_iqcor_coeff_tc_1,
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up_dac_iqcor_coeff_tc_1,
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up_dac_iqcor_coeff_tc_2,
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up_dac_iqcor_coeff_tc_2,
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up_dac_dds_scale_tc_1,
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up_dac_dds_scale_tc_1,
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@ -349,7 +356,8 @@ module up_dac_channel (
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.up_xfer_done (),
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.up_xfer_done (),
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.d_rst (dac_rst),
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.d_rst (dac_rst),
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.d_clk (dac_clk),
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.d_clk (dac_clk),
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.d_data_cntrl ({ dac_iqcor_enb,
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.d_data_cntrl ({ dac_iq_mode,
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dac_iqcor_enb,
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dac_iqcor_coeff_1,
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dac_iqcor_coeff_1,
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dac_iqcor_coeff_2,
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dac_iqcor_coeff_2,
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dac_dds_scale_1,
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dac_dds_scale_1,
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