axi_dmac: Add suport for 64 bit address width
New improvements for the ADI DMAC IP: 1)The capability to manually overwrite the DMA_AXI_ADDR_WIDTH(from GUI or from tcl) 2)DMA_AXI_ADDR_WIDTH attribute is now visible in the Vivado GUI: -"Auto mode": Automatically calculated by the core tcl files based on the existing attached address segments. -"Manual mode": Specify the desired dma_width between 32-64 bits. 3)Added two new debug registers that return higher part of the current source/destination address. Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>main
Filip Gherman
Filip Gherman
parent
fd0870352b
commit
cef4adb81d
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@ -80,6 +80,13 @@ set_parameter_property MAX_BYTES_PER_BURST DISPLAY_NAME "Maximum bytes per burst
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set_parameter_property MAX_BYTES_PER_BURST HDL_PARAMETER true
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set_parameter_property MAX_BYTES_PER_BURST GROUP $group
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add_parameter DMA_AXI_ADDR_WIDTH INTEGER 32
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set_parameter_property DMA_AXI_ADDR_WIDTH DISPLAY_NAME "DMA AXI Address Width"
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set_parameter_property DMA_AXI_ADDR_WIDTH UNITS Bits
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set_parameter_property DMA_AXI_ADDR_WIDTH HDL_PARAMETER true
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set_parameter_property DMA_AXI_ADDR_WIDTH ALLOWED_RANGES {16:64}
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set_parameter_property DMA_AXI_ADDR_WIDTH GROUP $group
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foreach {suffix group} { \
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"SRC" "Source" \
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"DEST" "Destination" \
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@ -228,6 +228,13 @@ set_property -dict [list \
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] \
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[ipx::get_user_parameters DMA_LENGTH_WIDTH -of_objects $cc]
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set_property -dict [list \
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"value_validation_type" "range_long" \
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"value_validation_range_minimum" "16" \
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"value_validation_range_maximum" "64" \
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] \
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[ipx::get_user_parameters DMA_AXI_ADDR_WIDTH -of_objects $cc]
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foreach {k v} { \
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"ASYNC_CLK_REQ_SRC" "true" \
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"ASYNC_CLK_SRC_DEST" "true" \
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@ -367,6 +374,12 @@ set_property -dict [list \
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"display_name" "Maximum Bytes per Burst" \
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] $p
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set p [ipgui::get_guiparamspec -name "DMA_AXI_ADDR_WIDTH" -component $cc]
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ipgui::move_param -component $cc -order 4 $p -parent $general_group
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set_property -dict [list \
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"display_name" "DMA AXI Address Width" \
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] $p
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set feature_group [ipgui::add_group -name "Features" -component $cc \
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-parent $page0 -display_name "Features"]
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@ -418,7 +431,6 @@ set_property -dict [list \
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"display_name" "Enable Diagnostics Interface" \
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] $p
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ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXI_ADDR_WIDTH" -component $cc]
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ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_SRC" -component $cc]
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ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_DEST" -component $cc]
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ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "ALLOW_ASYM_MEM" -component $cc]
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -117,6 +117,8 @@ module axi_dmac_regmap #(
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);
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localparam PCORE_VERSION = 'h00040461;
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localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32;
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localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1;
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// Register interface signals
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reg [31:0] up_rdata = 32'h00;
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@ -212,11 +214,13 @@ module axi_dmac_regmap #(
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9'h021: up_rdata <= up_irq_pending;
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9'h022: up_rdata <= up_irq_source;
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9'h100: up_rdata <= {ctrl_pause, ctrl_enable};
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9'h10d: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_dest_addr;
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9'h10e: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_src_addr;
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9'h10d: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_dest_addr[ADDR_LOW_MSB:0];
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9'h10e: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_src_addr[ADDR_LOW_MSB:0];
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9'h10f: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_status;
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9'h110: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids0;
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9'h111: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids1;
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9'h126: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_dest_addr[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
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9'h127: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_src_addr[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
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default: up_rdata <= up_rdata_request;
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endcase
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end
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -88,6 +88,9 @@ module axi_dmac_regmap_request #(
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);
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localparam MEASURED_LENGTH_WIDTH = (DMA_2D_TRANSFER == 1) ? 32 : DMA_LENGTH_WIDTH;
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localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32;
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localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1;
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localparam ADDR_HIGH_MSB = HAS_ADDR_HIGH ? DMA_AXI_ADDR_WIDTH-32-1 : 0;
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// DMA transfer signals
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reg up_dma_req_valid = 1'b0;
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@ -150,9 +153,17 @@ module axi_dmac_regmap_request #(
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up_dma_last <= up_wdata[1];
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up_dma_enable_tlen_reporting <= up_wdata[2];
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end
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9'h104: up_dma_dest_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
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9'h105: up_dma_src_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
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9'h104: up_dma_dest_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_DEST] <= up_wdata[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_DEST];
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9'h105: up_dma_src_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SRC] <= up_wdata[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SRC];
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9'h106: up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= up_wdata[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN];
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9'h124:
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if (HAS_ADDR_HIGH) begin
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up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0];
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end
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9'h125:
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if (HAS_ADDR_HIGH) begin
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up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0];
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end
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endcase
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end
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end
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@ -163,8 +174,8 @@ module axi_dmac_regmap_request #(
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9'h101: up_rdata <= up_transfer_id;
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9'h102: up_rdata <= up_dma_req_valid;
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9'h103: up_rdata <= {29'h00, up_dma_enable_tlen_reporting, up_dma_last, up_dma_cyclic}; // Flags
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9'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
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9'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
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9'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_DEST],{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
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9'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SRC],{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
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9'h106: up_rdata <= up_dma_x_length;
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9'h107: up_rdata <= request_y_length;
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9'h108: up_rdata <= request_dest_stride;
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@ -175,6 +186,8 @@ module axi_dmac_regmap_request #(
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9'h112: up_rdata <= up_measured_transfer_length;
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9'h113: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH-1 : 0]; // Length
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9'h114: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH+: 2]; // ID
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9'h124: up_rdata <= (HAS_ADDR_HIGH && HAS_DEST_ADDR) ? up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
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9'h125: up_rdata <= (HAS_ADDR_HIGH && HAS_SRC_ADDR) ? up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
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default: up_rdata <= 32'h00;
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endcase
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end
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@ -5,7 +5,7 @@ proc init {cellpath otherInfo} {
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bd::mark_propagate_override $ip \
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"ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ"
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bd::mark_propagate_only $ip \
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bd::mark_propagate_override $ip \
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"DMA_AXI_ADDR_WIDTH"
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# On ZYNQ the core is most likely connected to the AXI3 HP ports so use AXI3
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