Merge branch 'dev' into dev_ad7616

library/axi_hdmi_tx/axi_hdmi_tx.v

@@ -103,6 +103,8 @@ module axi_hdmi_tx (
   parameter   CR_CB_N = 0;
   parameter   DEVICE_TYPE = 0;
   parameter   EMBEDDED_SYNC = 0;
+  /* 0 = Launch on rising edge, 1 = Launch on falling edge */
+  parameter   OUT_CLK_POLARITY = 0;
 
   localparam  XILINX_7SERIES = 0;
   localparam  XILINX_ULTRASCALE = 1;
@@ -362,8 +364,8 @@ module axi_hdmi_tx (
   if (DEVICE_TYPE == XILINX_ULTRASCALE) begin
   ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
     .SR (1'b0),
-    .D1 (1'b1),
+    .D1 (~OUT_CLK_POLARITY),
-    .D2 (1'b0),
+    .D2 (OUT_CLK_POLARITY),
     .C (hdmi_clk),
     .Q (hdmi_out_clk));
   end
@@ -375,8 +377,8 @@ module axi_hdmi_tx (
     .sset (1'b0),
     .oe (1'b1),
     .outclocken (1'b1),
-    .datain_h (1'b1),
+    .datain_h (~OUT_CLK_POLARITY),
-    .datain_l (1'b0),
+    .datain_l (OUT_CLK_POLARITY),
     .outclock (hdmi_clk),
     .oe_out (),
     .dataout (hdmi_out_clk));
@@ -386,8 +388,8 @@ module axi_hdmi_tx (
     .R (1'b0),
     .S (1'b0),
     .CE (1'b1),
-    .D1 (1'b1),
+    .D1 (~OUT_CLK_POLARITY),
-    .D2 (1'b0),
+    .D2 (OUT_CLK_POLARITY),
     .C (hdmi_clk),
     .Q (hdmi_out_clk));
   end

projects/fmcadc5/common/fmcadc5_bd.tcl

@@ -10,6 +10,7 @@ create_bd_port -dir I -from 7 -to 0 rx_data_1_p
 create_bd_port -dir I -from 7 -to 0 rx_data_1_n
 create_bd_port -dir O rx_sync_1
 create_bd_port -dir O rx_sysref
+create_bd_port -dir O rx_clk
 
 # adc peripherals
 
@@ -219,6 +220,7 @@ ad_connect  util_fmcadc5_1_gt/rx_n rx_data_1_n
 ad_connect  util_fmcadc5_1_gt/rx_sysref GND
 ad_connect  util_fmcadc5_1_gt/rx_sync rx_sync_1
 ad_connect  util_fmcadc5_0_gt/rx_ip_sysref rx_sysref
+ad_connect  util_fmcadc5_0_gt/rx_out_clk rx_clk
 ad_connect  util_fmcadc5_0_gt/rx_out_clk util_fmcadc5_0_gt/rx_clk
 ad_connect  util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_jesd/rx_core_clk
 ad_connect  util_fmcadc5_0_gt/rx_ip_rst axi_ad9625_0_jesd/rx_reset
@@ -286,8 +288,12 @@ ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq
 
 create_bd_port -dir O up_clk
 create_bd_port -dir O up_rstn
+create_bd_port -dir O delay_clk
+create_bd_port -dir O delay_rst
 
 ad_connect  sys_cpu_clk up_clk
 ad_connect  sys_cpu_resetn up_rstn
+ad_connect  sys_200m_clk delay_clk
+ad_connect  sys_cpu_reset delay_rst
 
 

projects/fmcadc5/vc707/system_bd.tcl

@@ -8,19 +8,15 @@ source ../common/fmcadc5_bd.tcl
 set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc]
 set_property -dict [list CONFIG.NUM_OF_CHANNELS {1}] $mfifo_adc
 set_property -dict [list CONFIG.DIN_DATA_WIDTH {512}] $mfifo_adc
-set_property -dict [list CONFIG.ADDRESS_WIDTH {5}] $mfifo_adc
+set_property -dict [list CONFIG.ADDRESS_WIDTH {6}] $mfifo_adc
 
 set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc]
 set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
 set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {6}] $ila_adc
+set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc
 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
 set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE2_WIDTH {256}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE5_WIDTH {16}] $ila_adc
 
 ad_connect  util_fmcadc5_0_gt/rx_rst mfifo_adc/din_rst
 ad_connect  util_fmcadc5_0_gt/rx_out_clk mfifo_adc/din_clk
@@ -31,7 +27,4 @@ ad_connect  util_fmcadc5_0_gt/rx_out_clk mfifo_adc/dout_clk
 ad_connect  util_fmcadc5_0_gt/rx_out_clk ila_adc/clk
 ad_connect  mfifo_adc/dout_valid ila_adc/probe0
 ad_connect  mfifo_adc/dout_data_0 ila_adc/probe1
-ad_connect  axi_ad9625_0_core/adc_data ila_adc/probe2
+
-ad_connect  axi_ad9625_1_core/adc_data ila_adc/probe3
-ad_connect  axi_ad9625_0_core/adc_sref ila_adc/probe4
-ad_connect  axi_ad9625_1_core/adc_sref ila_adc/probe5

projects/fmcadc5/vc707/system_constr.xdc

@@ -86,3 +86,4 @@ create_clock -name rx_ref_clk_0   -period  1.60 [get_ports rx_ref_clk_0_p]
 create_clock -name rx_ref_clk_1   -period  1.60 [get_ports rx_ref_clk_1_p]
 create_clock -name rx_div_clk     -period  6.40 [get_pins i_system_wrapper/system_i/axi_fmcadc5_0_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
 
+

projects/fmcadc5/vc707/system_project.tcl

@@ -12,6 +12,7 @@ adi_project_files fmcadc5_vc707 [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_lvds_out.v" \
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
 set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]

projects/fmcadc5/vc707/system_top.v

@@ -231,8 +231,15 @@ module system_top (
   output            drst_0;
   output            arst_0;
 
+  // internal registers
+
+  reg     [  4:0]   gpio_o_60_56_d = 'd0;
+  reg               gpio_dld = 'd0;
+
   // internal signals
 
+  wire              delay_clk;
+  wire              delay_rst;
   wire    [ 63:0]   gpio_i;
   wire    [ 63:0]   gpio_o;
   wire    [ 63:0]   gpio_t;
@@ -240,9 +247,10 @@ module system_top (
   wire              spi_clk;
   wire              spi_mosi;
   wire              spi_miso;
+  wire              rx_clk;
   wire              rx_ref_clk_0;
   wire              rx_ref_clk_1;
-  wire              rx_sysref;
+  wire              rx_sysref_s;
   wire              rx_sync_0;
   wire              rx_sync_1;
   wire              up_rstn;
@@ -263,8 +271,44 @@ module system_top (
   assign drst_0 = 1'b0;
   assign arst_0 = 1'b0;
 
+  // sysref iob
+
+  always @(posedge up_clk or negedge up_rstn) begin
+    if (up_rstn == 1'b0) begin
+      gpio_o_60_56_d <= 5'd0;
+      gpio_dld <= 1'b0;
+    end else begin
+      gpio_o_60_56_d <= gpio_o[60:56];
+      if (gpio_o[60:56] == gpio_o_60_56_d) begin
+        gpio_dld <= 1'b0;
+      end else begin
+        gpio_dld <= 1'b1;
+      end
+    end
+  end
+
   // instantiations
 
+  ad_lvds_out #(
+    .DEVICE_TYPE (0),
+    .SINGLE_ENDED (0),
+    .IODELAY_ENABLE (1),
+    .IODELAY_CTRL (1),
+    .IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP"))
+  i_rx_sysref (
+    .tx_clk (rx_clk),
+    .tx_data_p (rx_sysref_s),
+    .tx_data_n (rx_sysref_s),
+    .tx_data_out_p (rx_sysref_p),
+    .tx_data_out_n (rx_sysref_n),
+    .up_clk (up_clk),
+    .up_dld (gpio_dld),
+    .up_dwdata (gpio_o[60:56]),
+    .up_drdata (gpio_i[60:56]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (gpio_i[61]));
+
   IBUFDS_GTE2 i_ibufds_rx_ref_clk_0 (
     .CEB (1'd0),
     .I (rx_ref_clk_0_p),
@@ -279,11 +323,6 @@ module system_top (
     .O (rx_ref_clk_1),
     .ODIV2 ());
 
-  OBUFDS i_obufds_rx_sysref (
-    .I (rx_sysref),
-    .O (rx_sysref_p),
-    .OB (rx_sysref_n));
-
   OBUFDS i_obufds_rx_sync_0 (
     .I (rx_sync_0),
     .O (rx_sync_0_p),
@@ -355,6 +394,8 @@ module system_top (
     .ddr3_ras_n (ddr3_ras_n),
     .ddr3_reset_n (ddr3_reset_n),
     .ddr3_we_n (ddr3_we_n),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
     .gpio0_i (gpio_i[31:0]),
     .gpio0_o (gpio_o[31:0]),
     .gpio0_t (gpio_t[31:0]),
@@ -382,6 +423,7 @@ module system_top (
     .mgt_clk_clk_p (mgt_clk_p),
     .phy_rstn (phy_rstn),
     .phy_sd (1'b1),
+    .rx_clk (rx_clk),
     .rx_data_0_n (rx_data_0_n),
     .rx_data_0_p (rx_data_0_p),
     .rx_data_1_n (rx_data_1_n),
@@ -390,7 +432,7 @@ module system_top (
     .rx_ref_clk_1 (rx_ref_clk_1),
     .rx_sync_0 (rx_sync_0),
     .rx_sync_1 (rx_sync_1),
-    .rx_sysref (rx_sysref),
+    .rx_sysref (rx_sysref_s),
     .sgmii_rxn (sgmii_rxn),
     .sgmii_rxp (sgmii_rxp),
     .sgmii_txn (sgmii_txn),

projects/pzsdr/ccfmc/system_top.v

@@ -314,6 +314,13 @@ module system_top (
   wire            tdd_sync_i;
   wire            tdd_sync_o;
   wire            tdd_sync_t;
+  wire            up_clk;
+  wire            up_rst;
+  wire            up_rstn;
+  wire            up_pn_err_clr;
+  wire            up_pn_oos_clr;
+  wire            up_pn_err;
+  wire            up_pn_oos;
 
   // assignments
 
@@ -569,7 +576,14 @@ module system_top (
     .tx_frame_out_n (tx_frame_out_n),
     .tx_frame_out_p (tx_frame_out_p),
     .txnrx (txnrx),
+    .up_clk (up_clk),
     .up_enable (gpio_o[47]),
+    .up_pn_err (up_pn_err),
+    .up_pn_err_clr (up_pn_err_clr),
+    .up_pn_oos (up_pn_oos),
+    .up_pn_oos_clr (up_pn_oos_clr),
+    .up_rst (up_rst),
+    .up_rstn (up_rstn),
     .up_txnrx (gpio_o[48]));
 
 endmodule

projects/pzsdr/common/ccfmc_bd.tcl

@@ -50,6 +50,7 @@ set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rgmii_rstgen
 
 set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
 set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
+set_property -dict [list CONFIG.OUT_CLK_POLARITY {1}] $axi_hdmi_core
 
 set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
 set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma