jesd204_tpl: addresses cleanup
The TPL has an address space of 12 bits while the legacy subcomponents have 16 bits. Update the module for a better readability.main
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560e9b9e52
commit
cf593d5a40
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@ -100,11 +100,11 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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wire adc_rst;
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wire adc_rst;
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wire up_wreq_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [9:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_wdata_s;
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wire [NUM_CHANNELS+1:0] up_wack_s;
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wire [NUM_CHANNELS+1:0] up_wack_s;
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wire up_rreq_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [9:0] up_raddr_s;
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wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
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wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
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wire [NUM_CHANNELS+1:0] up_rack_s;
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wire [NUM_CHANNELS+1:0] up_rack_s;
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@ -129,13 +129,14 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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// up bus interface
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// up bus interface
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up_axi #(
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up_axi #(
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.AXI_ADDRESS_WIDTH (16)
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.AXI_ADDRESS_WIDTH (12),
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.ADDRESS_WIDTH (10)
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) i_up_axi (
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) i_up_axi (
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.up_clk (up_clk),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_rstn (up_rstn),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr ({4'b0,s_axi_awaddr}),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wdata (s_axi_wdata),
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@ -145,7 +146,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr ({4'b0,s_axi_araddr}),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rresp (s_axi_rresp),
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@ -191,6 +192,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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// common processor control
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// common processor control
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up_adc_common #(
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up_adc_common #(
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.COMMON_ID (6'h0),
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.ID (ID),
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.ID (ID),
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.DRP_DISABLE (1),
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.DRP_DISABLE (1),
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.USERPORTS_DISABLE (1),
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.USERPORTS_DISABLE (1),
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@ -233,11 +235,11 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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.up_clk (up_clk),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_rstn (up_rstn),
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.up_wreq (up_wreq_s),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_waddr ({4'b0,up_waddr_s}),
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.up_wdata (up_wdata_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[0]),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_raddr ({4'b0,up_raddr_s}),
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.up_rdata (up_rdata_s[0]),
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.up_rdata (up_rdata_s[0]),
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.up_rack (up_rack_s[0])
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.up_rack (up_rack_s[0])
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);
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);
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@ -246,6 +248,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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genvar i;
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genvar i;
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for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
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for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
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up_adc_channel #(
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up_adc_channel #(
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.COMMON_ID (6'h1),
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.CHANNEL_ID (i),
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.CHANNEL_ID (i),
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.USERPORTS_DISABLE (1),
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.USERPORTS_DISABLE (1),
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.DCFILTER_DISABLE (1),
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.DCFILTER_DISABLE (1),
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@ -290,11 +293,11 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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.up_clk (up_clk),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_rstn (up_rstn),
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.up_wreq (up_wreq_s),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_waddr ({4'b0,up_waddr_s}),
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.up_wdata (up_wdata_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[i+1]),
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.up_wack (up_wack_s[i+1]),
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.up_rreq (up_rreq_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_raddr ({4'b0,up_raddr_s}),
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.up_rdata (up_rdata_s[i+1]),
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.up_rdata (up_rdata_s[i+1]),
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.up_rack (up_rack_s[i+1])
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.up_rack (up_rack_s[i+1])
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);
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);
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@ -302,7 +305,7 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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endgenerate
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endgenerate
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up_tpl_common #(
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up_tpl_common #(
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.COMMON_ID(4'h3), // Offset of regmap
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.COMMON_ID(2'h3), // Offset of regmap
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.NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles
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.NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles
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) i_up_tpl_adc (
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) i_up_tpl_adc (
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@ -328,4 +331,5 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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.up_rdata (up_rdata_s[NUM_CHANNELS+1]),
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.up_rdata (up_rdata_s[NUM_CHANNELS+1]),
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.up_rack (up_rack_s[NUM_CHANNELS+1])
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.up_rack (up_rack_s[NUM_CHANNELS+1])
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);
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);
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endmodule
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endmodule
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@ -38,7 +38,7 @@
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module up_tpl_common #(
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module up_tpl_common #(
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// parameters
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// parameters
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parameter COMMON_ID = 4'hF, // Offset of regmap
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parameter COMMON_ID = 2'h3, // Offset of regmap
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parameter NUM_PROFILES = 1 // Number of JESD profiles
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parameter NUM_PROFILES = 1 // Number of JESD profiles
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)(
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)(
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@ -56,11 +56,11 @@ module up_tpl_common #(
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input up_rstn,
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input up_rstn,
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input up_clk,
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input up_clk,
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input up_wreq,
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input up_wreq,
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input [13:0] up_waddr,
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input [9:0] up_waddr,
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input [31:0] up_wdata,
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input [31:0] up_wdata,
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output up_wack,
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output up_wack,
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input up_rreq,
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input up_rreq,
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input [13:0] up_raddr,
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input [9:0] up_raddr,
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output [31:0] up_rdata,
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output [31:0] up_rdata,
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output up_rack
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output up_rack
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);
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);
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@ -77,8 +77,8 @@ module up_tpl_common #(
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// decode block select
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0;
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assign up_wreq_s = (up_waddr[9:8] == COMMON_ID) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0;
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assign up_rreq_s = (up_raddr[9:8] == COMMON_ID) ? up_rreq : 1'b0;
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// processor write interface
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// processor write interface
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@ -94,11 +94,11 @@ module ad_ip_jesd204_tpl_dac_regmap #(
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wire up_wreq_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [9:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_wdata_s;
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wire [NUM_CHANNELS+1:0] up_wack_s;
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wire [NUM_CHANNELS+1:0] up_wack_s;
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wire up_rreq_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [9:0] up_raddr_s;
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wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
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wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
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wire [NUM_CHANNELS+1:0] up_rack_s;
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wire [NUM_CHANNELS+1:0] up_rack_s;
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@ -116,7 +116,8 @@ module ad_ip_jesd204_tpl_dac_regmap #(
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// up bus interface
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// up bus interface
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up_axi #(
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up_axi #(
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.AXI_ADDRESS_WIDTH (16)
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.AXI_ADDRESS_WIDTH (12),
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.ADDRESS_WIDTH (10)
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) i_up_axi (
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) i_up_axi (
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.up_clk (up_clk),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_rstn (up_rstn),
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@ -213,11 +214,11 @@ module ad_ip_jesd204_tpl_dac_regmap #(
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.up_rstn (up_rstn),
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.up_rstn (up_rstn),
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.up_wreq (up_wreq_s),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_waddr ({4'b0,up_waddr_s}),
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.up_wdata (up_wdata_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[0]),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_raddr ({4'b0,up_raddr_s}),
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.up_rdata (up_rdata_s[0]),
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.up_rdata (up_rdata_s[0]),
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.up_rack (up_rack_s[0])
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.up_rack (up_rack_s[0])
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);
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);
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@ -264,11 +265,11 @@ module ad_ip_jesd204_tpl_dac_regmap #(
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.up_clk (up_clk),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_rstn (up_rstn),
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.up_wreq (up_wreq_s),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_waddr ({4'b0,up_waddr_s}),
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.up_wdata (up_wdata_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[i+1]),
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.up_wack (up_wack_s[i+1]),
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.up_rreq (up_rreq_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_raddr ({4'b0,up_raddr_s}),
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.up_rdata (up_rdata_s[i+1]),
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.up_rdata (up_rdata_s[i+1]),
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.up_rack (up_rack_s[i+1])
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.up_rack (up_rack_s[i+1])
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);
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);
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@ -276,7 +277,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
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endgenerate
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endgenerate
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up_tpl_common #(
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up_tpl_common #(
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.COMMON_ID(4'h3), // Offset of regmap
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.COMMON_ID(2'h3), // Offset of regmap
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.NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles
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.NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles
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) i_up_tpl_dac (
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) i_up_tpl_dac (
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