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util_adc_pack: Fixed problems when working in 4 channels mode

main
Adrian Costina 2014-08-29 13:51:40 +03:00
parent da913864c9
commit cf660c126d
1 changed files with 178 additions and 125 deletions
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303
library/util_adc_pack/util_adc_pack.v
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@ -81,73 +81,74 @@ module util_adc_pack (
); );
parameter CHANNELS = 8 ; // valid values are 4 and 8 parameter CHANNELS = 8 ; // valid values are 4 and 8
parameter DATA_WIDTH = 16; // valid values are 16 and 32 parameter DATA_WIDTH = 16; // valid values are 16 and 32
// common clock // common clock
input clk; input clk;
input chan_enable_0; input chan_enable_0;
input chan_valid_0; input chan_valid_0;
input [(DATA_WIDTH-1):0] chan_data_0; input [(DATA_WIDTH-1):0] chan_data_0;
input chan_enable_1; input chan_enable_1;
input chan_valid_1; input chan_valid_1;
input [(DATA_WIDTH-1):0] chan_data_1; input [(DATA_WIDTH-1):0] chan_data_1;
input chan_enable_2; input chan_enable_2;
input chan_valid_2; input chan_valid_2;
input [(DATA_WIDTH-1):0] chan_data_2; input [(DATA_WIDTH-1):0] chan_data_2;
input chan_enable_3; input chan_enable_3;
input chan_valid_3; input chan_valid_3;
input [(DATA_WIDTH-1):0] chan_data_3; input [(DATA_WIDTH-1):0] chan_data_3;
input chan_enable_4; input chan_enable_4;
input chan_valid_4; input chan_valid_4;
input [(DATA_WIDTH-1):0] chan_data_4; input [(DATA_WIDTH-1):0] chan_data_4;
input chan_enable_5; input chan_enable_5;
input chan_valid_5; input chan_valid_5;
input [(DATA_WIDTH-1):0] chan_data_5; input [(DATA_WIDTH-1):0] chan_data_5;
input chan_enable_6; input chan_enable_6;
input chan_valid_6; input chan_valid_6;
input [(DATA_WIDTH-1):0] chan_data_6; input [(DATA_WIDTH-1):0] chan_data_6;
input chan_valid_7; input chan_valid_7;
input chan_enable_7; input chan_enable_7;
input [(DATA_WIDTH-1):0] chan_data_7; input [(DATA_WIDTH-1):0] chan_data_7;
output [(DATA_WIDTH * CHANNELS - 1):0] ddata; output [(DATA_WIDTH*CHANNELS-1):0] ddata;
output dvalid; output dvalid;
output dsync; output dsync;
reg [3:0] enable_cnt; reg [3:0] enable_cnt;
reg [2:0] enable_cnt_0; reg [2:0] enable_cnt_0;
reg [2:0] enable_cnt_1; reg [2:0] enable_cnt_1;
reg [(DATA_WIDTH * CHANNELS - 1):0] packed_data = 0; reg [255:0] packed_data = 0;
reg [63:0] temp_data_0 = 0; reg [127:0] temp_data_0 = 0;
reg [63:0] temp_data_1 = 0; reg [127:0] temp_data_1 = 0;
reg [7:0] path_enabled = 0; reg [7:0] path_enabled = 0;
reg [7:0] path_enabled_d1 = 0; reg [7:0] path_enabled_d1 = 0;
reg [6:0] counter_0 = 0; reg [6:0] counter_0 = 0;
reg [7:0] en1 = 0; reg [7:0] en1 = 0;
reg [7:0] en2 = 0; reg [7:0] en2 = 0;
reg [7:0] en4 = 0; reg [7:0] en4 = 0;
reg [(DATA_WIDTH * CHANNELS - 1):0] ddata = 0;
reg dvalid = 0; reg dvalid = 0;
reg chan_valid = 0; reg chan_valid = 0;
reg chan_valid_d1 = 0; reg chan_valid_d1 = 0;
reg [(DATA_WIDTH-1):0] chan_data_0_r;
reg [(DATA_WIDTH-1):0] chan_data_1_r; reg [(DATA_WIDTH*CHANNELS-1):0] ddata = 0;
reg [(DATA_WIDTH-1):0] chan_data_2_r; reg [(DATA_WIDTH-1):0] chan_data_0_r;
reg [(DATA_WIDTH-1):0] chan_data_3_r; reg [(DATA_WIDTH-1):0] chan_data_1_r;
reg [(DATA_WIDTH-1):0] chan_data_4_r; reg [(DATA_WIDTH-1):0] chan_data_2_r;
reg [(DATA_WIDTH-1):0] chan_data_5_r; reg [(DATA_WIDTH-1):0] chan_data_3_r;
reg [(DATA_WIDTH-1):0] chan_data_6_r; reg [(DATA_WIDTH-1):0] chan_data_4_r;
reg [(DATA_WIDTH-1):0] chan_data_7_r; reg [(DATA_WIDTH-1):0] chan_data_5_r;
reg [(DATA_WIDTH-1):0] chan_data_6_r;
reg [(DATA_WIDTH-1):0] chan_data_7_r;
assign dsync = dvalid; assign dsync = dvalid;
@ -155,7 +156,14 @@ module util_adc_pack (
begin begin
enable_cnt = enable_cnt_0 + enable_cnt_1; enable_cnt = enable_cnt_0 + enable_cnt_1;
enable_cnt_0 = chan_enable_0 + chan_enable_1 + chan_enable_2 + chan_enable_3; enable_cnt_0 = chan_enable_0 + chan_enable_1 + chan_enable_2 + chan_enable_3;
enable_cnt_1 = chan_enable_4 + chan_enable_5 + chan_enable_6 + chan_enable_7; if (CHANNELS == 8)
begin
enable_cnt_1 = chan_enable_4 + chan_enable_5 + chan_enable_6 + chan_enable_7;
end
else
begin
enable_cnt_1 = 0;
end
end end
always @(posedge clk) always @(posedge clk)
@ -253,11 +261,6 @@ module util_adc_pack (
end end
end end
always @(temp_data_0, temp_data_1, enable_cnt_0)
begin
packed_data = temp_data_0 | temp_data_1 << enable_cnt_0 * DATA_WIDTH;
end
always @(enable_cnt) always @(enable_cnt)
begin begin
case(enable_cnt) case(enable_cnt)
@ -269,39 +272,9 @@ module util_adc_pack (
endcase endcase
end end
always @(posedge clk) always @(temp_data_0, temp_data_1, enable_cnt_0)
begin begin
path_enabled_d1 <= path_enabled; packed_data = temp_data_0 | temp_data_1 << (enable_cnt_0 * DATA_WIDTH);
if (path_enabled == 8'h0 || path_enabled_d1 != path_enabled )
begin
counter_0 <= 7'h0;
end
else
begin
if( chan_valid == 1'b1)
begin
if (counter_0 > 7)
begin
counter_0 <= counter_0 - 8 + enable_cnt;
end
else
begin
counter_0 <= counter_0 + enable_cnt;
end
if ((counter_0 == (8 - enable_cnt)) || (path_enabled == 8'h80) )
begin
dvalid <= 1'b1;
end
else
begin
dvalid <= 1'b0;
end
end
else
begin
dvalid <= 1'b0;
end
end
end end
always @(counter_0, path_enabled) always @(counter_0, path_enabled)
@ -333,9 +306,18 @@ module util_adc_pack (
end end
4: 4:
begin begin
en1 = path_enabled[0] << 4; if (CHANNELS == 8)
en2 = {2{path_enabled[1]}} << 4; begin
en4 = {4{path_enabled[3]}} << 4; en1 = path_enabled[0] << 4;
en2 = {2{path_enabled[1]}} << 4;
en4 = {4{path_enabled[3]}} << 4;
end
else
begin
en1 = path_enabled[0];
en2 = {2{path_enabled[1]}};
en4 = {4{path_enabled[3]}};
end
end end
5: 5:
begin begin
@ -370,63 +352,94 @@ module util_adc_pack (
endcase endcase
end end
// FOUR CHANNELS
always @(posedge clk) always @(posedge clk)
begin begin
// ddata 0 path_enabled_d1 <= path_enabled;
if ((en1[0] | en2[0] | en4[0] | path_enabled[7]) == 1'b1) if (path_enabled == 8'h0 || path_enabled_d1 != path_enabled )
begin begin
ddata[(DATA_WIDTH-1):0] <= temp_data_0[(DATA_WIDTH-1):0]; counter_0 <= 7'h0;
end end
else
// ddata 1
if( en1[1] == 1'b1)
begin begin
ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= temp_data_0[(DATA_WIDTH-1):0]; if( chan_valid == 1'b1)
begin
if (counter_0 > (CHANNELS - 1) )
begin
counter_0 <= counter_0 - CHANNELS + enable_cnt;
end
else
begin
counter_0 <= counter_0 + enable_cnt;
end
if ((counter_0 == (CHANNELS - enable_cnt)) || (path_enabled == (8'h1 << (CHANNELS - 1)) ))
begin
dvalid <= 1'b1;
end
else
begin
dvalid <= 1'b0;
end
end
else
begin
dvalid <= 1'b0;
end
end end
if ( (en2[1] | en4[1] | path_enabled[7]) == 1'b1)
begin
ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH];
end
// ddata 2
if ((en1[2] | en2[2]) == 1'b1)
begin
ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= temp_data_0[(DATA_WIDTH-1):0];
end
if ((en4[2] | path_enabled[7]) == 1'b1)
begin
ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH];
end
// ddata 3
if (en1[3] == 1'b1)
begin
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= temp_data_0[(DATA_WIDTH-1):0];
end
if (en2[3] == 1'b1)
begin
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH];
end
if ((en4[3] | path_enabled[7]) == 1'b1)
begin
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH];
end
end end
// EIGHT CHANNELS
generate generate
if ( CHANNELS == 8) // 8 CHANNELS
if ( CHANNELS == 8 )
begin begin
// FIRST FOUR CHANNELS
always @(posedge clk) always @(posedge clk)
begin begin
// ddata 0
if ((en1[0] | en2[0] | en4[0] | path_enabled[CHANNELS-1]) == 1'b1)
begin
ddata[(DATA_WIDTH-1):0] <= packed_data[(DATA_WIDTH-1):0];
end
// ddata 1
if( en1[1] == 1'b1)
begin
ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
end
if ( (en2[1] | en4[1] | path_enabled[CHANNELS-1]) == 1'b1)
begin
ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
end
// ddata 2
if ((en1[2] | en2[2]) == 1'b1)
begin
ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
end
if ((en4[2] | path_enabled[CHANNELS-1]) == 1'b1)
begin
ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH];
end
// ddata 3
if (en1[3] == 1'b1)
begin
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
end
if (en2[3] == 1'b1)
begin
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
end
if ((en4[3] | path_enabled[CHANNELS-1]) == 1'b1)
begin
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH];
end
// ddata 4 // ddata 4
if ((en1[4] | en2[4] | en4[4]) == 1'b1) if ((en1[4] | en2[4] | en4[4]) == 1'b1)
begin begin
ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
end end
if (path_enabled[7] == 1'b1) if (path_enabled[CHANNELS-1] == 1'b1)
begin begin
ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[5*DATA_WIDTH-1:4*DATA_WIDTH]; ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[5*DATA_WIDTH-1:4*DATA_WIDTH];
end end
@ -440,7 +453,7 @@ module util_adc_pack (
begin begin
ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH]; ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
end end
if (path_enabled[7] == 1'b1) if (path_enabled[CHANNELS-1] == 1'b1)
begin begin
ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[6*DATA_WIDTH-1:5*DATA_WIDTH]; ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[6*DATA_WIDTH-1:5*DATA_WIDTH];
end end
@ -454,7 +467,7 @@ module util_adc_pack (
begin begin
ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH]; ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH];
end end
if (path_enabled[7] == 1'b1) if (path_enabled[CHANNELS-1] == 1'b1)
begin begin
ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[7*DATA_WIDTH-1:6*DATA_WIDTH]; ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[7*DATA_WIDTH-1:6*DATA_WIDTH];
end end
@ -472,21 +485,61 @@ module util_adc_pack (
begin begin
ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH]; ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH];
end end
if (path_enabled[7] == 1'b1) if (path_enabled[CHANNELS-1] == 1'b1)
begin begin
ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[127:7*DATA_WIDTH]; ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[8*DATA_WIDTH-1:7*DATA_WIDTH];
end end
end end
end
always @(temp_data_0, temp_data_1, enable_cnt_0) else
begin
always @(posedge clk)
begin begin
packed_data = temp_data_0 | temp_data_1 << enable_cnt_0 * DATA_WIDTH; // ddata 0
end if ((en1[0] | en2[0] | path_enabled[3] ) == 1'b1)
begin
ddata[(DATA_WIDTH-1):0] <= packed_data[(DATA_WIDTH-1):0];
end
// ddata 1
if( en1[1] == 1'b1)
begin
ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
end
if ( (en2[1] | | path_enabled[3] )== 1'b1)
begin
ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
end
// ddata 2
if ((en1[2] | en2[2]) == 1'b1)
begin
ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
end
if (( path_enabled[3]) == 1'b1)
begin
ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH];
end
// ddata 3
if (en1[3] == 1'b1)
begin
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
end
if (en2[3] == 1'b1)
begin
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
end
if (path_enabled[3] == 1'b1)
begin
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH];
end
end
end end
endgenerate endgenerate
endmodule endmodule
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************