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Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev

main
Michael Hennerich 2014-10-30 08:42:09 +01:00
parent b7946febfa 56374cf592
commit cfa1a93441
15 changed files with 195 additions and 81 deletions
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7
library/axi_ad9671/axi_ad9671_hw.tcl
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@ -94,6 +94,13 @@ set_interface_property xcvr_data associatedClock xcvr_clk
add_interface_port xcvr_data rx_data data Input 64*PCORE_4L_2L_N+64
add_interface_port xcvr_data rx_data_sof data_sof Input 1
add_interface xcvr_sync conduit end
set_interface_property xcvr_sync associatedClock xcvr_clk
add_interface_port xcvr_sync adc_sync_in sync_in Input 1
add_interface_port xcvr_sync adc_sync_out sync_out Output 1
add_interface_port xcvr_sync adc_raddr_in raddr_in Input 4
add_interface_port xcvr_sync adc_raddr_out raddr_out Output 4
# dma interface
add_interface adc_clock clock start

2
library/axi_dmac/axi_dmac.v
View File

@ -146,6 +146,7 @@ module axi_dmac (
input s_axis_valid,
input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
// Master streaming AXI interface
input m_axis_aclk,
@ -587,6 +588,7 @@ dmac_request_arb #(
.s_axis_valid(s_axis_valid),
.s_axis_data(s_axis_data),
.s_axis_user(s_axis_user),
.s_axis_xfer_req(s_axis_xfer_req),
.m_axis_aclk(m_axis_aclk),

4
library/axi_dmac/request_arb.v
View File

@ -102,6 +102,7 @@ module dmac_request_arb (
input s_axis_valid,
input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
// Master streaming AXI interface
input m_axis_aclk,
@ -691,7 +692,8 @@ dmac_src_axi_stream #(
.s_axis_valid(s_axis_valid),
.s_axis_ready(s_axis_ready),
.s_axis_data(s_axis_data),
.s_axis_user(s_axis_user)
.s_axis_user(s_axis_user),
.s_axis_xfer_req(s_axis_xfer_req)
);
end else begin

3
library/axi_dmac/src_axi_stream.v
View File

@ -53,6 +53,7 @@ module dmac_src_axi_stream (
input s_axis_valid,
input [C_S_AXIS_DATA_WIDTH-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
input fifo_ready,
output fifo_valid,
@ -101,6 +102,8 @@ dmac_data_mover # (
.enabled(enabled),
.sync_id(sync_id),
.xfer_req(s_axis_xfer_req),
.request_id(request_id),
.response_id(response_id),
.eot(eot),

1
projects/ad9625_fmc/common/ad9625_fmc_bd.tcl
View File

@ -201,6 +201,7 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_fifo
connect_bd_net -net axi_ad9625_dma_dvalid [get_bd_pins axi_ad9625_fifo/dma_wvalid] [get_bd_pins axi_ad9625_dma/s_axis_valid]
connect_bd_net -net axi_ad9625_dma_dready [get_bd_pins axi_ad9625_fifo/dma_wready] [get_bd_pins axi_ad9625_dma/s_axis_ready]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data]
connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins axi_ad9625_fifo/axi_xfer_req] [get_bd_pins axi_ad9625_dma/s_axis_xfer_req]
connect_bd_net -net axi_ad9625_dma_intr [get_bd_pins axi_ad9625_dma/irq] [get_bd_ports ad9625_dma_intr]
if {$sys_zynq == 0} {

24
projects/ad9625_fmc/zc706/system_top.v
View File

@ -200,6 +200,7 @@ module system_top (
wire spi_clk;
wire spi_miso;
wire spi_mosi;
wire [15:0] ps_intrs;
// instantiations
@ -280,8 +281,9 @@ module system_top (
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.ad9625_dma_intr (ps_intrs[13]),
.ad9625_gpio_intr (),
.ad9625_spi_intr (),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
@ -289,6 +291,20 @@ module system_top (
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
@ -302,7 +318,9 @@ module system_top (
.spi_csn_1_o (spi_clk_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi));
.spi_sdo_o (spi_mosi),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p));
endmodule

41
projects/ad9671_fmc/a5gt/system_constr.sdc
View File

@ -1,32 +1,29 @@
create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name n_clk_250m [get_ports {ref_clk}]
create_clock -period "12.500 ns" -name n_clk_ref [get_ports {ref_clk}]
create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_nets {eth_tx_clk}]
derive_pll_clocks
derive_clock_uncertainty
set clk_100m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_166m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_125m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_25m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_2m5 [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_rxlink [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_100m {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_166m {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_125m {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_25m {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_2m5 {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_rxlink {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
set_clock_groups -asynchronous -group [get_clocks {n_clk_ref} ]
set_clock_groups -asynchronous -group [get_clocks {n_clk_100m} ]
set_clock_groups -asynchronous -group [get_clocks {n_eth_rx_clk_125m} ]
set_clock_groups -asynchronous -group [get_clocks {n_eth_tx_clk_125m} ]
set_clock_groups -asynchronous -group [get_clocks $clk_100m ]
set_clock_groups -asynchronous -group [get_clocks $clk_166m ]
set_clock_groups -asynchronous -group [get_clocks $clk_125m ]
set_clock_groups -asynchronous -group [get_clocks $clk_25m ]
set_clock_groups -asynchronous -group [get_clocks $clk_2m5 ]
set_clock_groups -asynchronous -group [get_clocks $clk_rxlink ]
set_false_path -from {sys_resetn} -to *
set_false_path -from $clk_100m -to $clk_166m
set_false_path -from $clk_100m -to $clk_rxlink
set_false_path -from $clk_166m -to $clk_100m
set_false_path -from $clk_166m -to $clk_rxlink
set_false_path -from $clk_rxlink -to $clk_100m
set_false_path -from $clk_rxlink -to $clk_166m
set_false_path -from $clk_125m -to $clk_25m
set_false_path -from $clk_125m -to $clk_2m5
set_false_path -from $clk_25m -to $clk_125m
set_false_path -from $clk_25m -to $clk_2m5
set_false_path -from $clk_2m5 -to $clk_125m
set_false_path -from $clk_2m5 -to $clk_25m
set_false_path -from * -to {sys_resetn}

15
projects/ad9671_fmc/a5gt/system_timing.tcl
View File

@ -1,3 +1,16 @@
report_timing -detail path_only -npaths 20 -file timing_impl.log
set worst_path [get_timing_paths -npaths 1 -setup]
foreach_in_collection path $worst_path {
set slack [get_path_info $path -slack]
}
if {$slack > 0} {
set worst_path [get_timing_paths -npaths 1 -hold]
foreach_in_collection path $worst_path {
set slack [get_path_info $path -slack]
}
}
if {$slack < 0} {
use_this_invalid_command_to_crash
}

26
projects/common/zc706/zc706_system_bd.tcl
View File

@ -22,12 +22,6 @@ set hdmi_data [create_bd_port -dir O -from 23 -to 0 hdmi_data]
set spdif [create_bd_port -dir O spdif]
# interrupts
set iic_irq [create_bd_port -dir O iic_irq]
set hdmi_dma_irq [create_bd_port -dir O hdmi_dma_irq]
set ps7_irq_f2p [create_bd_port -dir I -from 15 -to 0 -type intr ps7_irq_f2p]
# instance: sys_ps7
set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7]
@ -48,6 +42,9 @@ set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect
@ -118,7 +115,6 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sy
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
connect_bd_net -net iic_irq_net [get_bd_pins axi_iic_main/iic2intc_irpt] [get_bd_ports iic_irq]
# hdmi
@ -171,11 +167,6 @@ connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync]
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
connect_bd_net -net hdmi_dma_irq_net [get_bd_pins axi_hdmi_dma/mm2s_introut] [get_bd_ports hdmi_dma_irq]
connect_bd_net -net sys_ps7_interrupt [get_bd_pins sys_ps7/IRQ_F2P] [get_bd_ports ps7_irq_f2p]
set_property -dict [list CONFIG.PortWidth {16}] [get_bd_ports ps7_irq_f2p]
# spdif audio
connect_bd_intf_net -intf_net axi_cpu_interconnect_m04_axi [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
@ -202,6 +193,17 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESET
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source
# interrupts
connect_bd_net [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P]
connect_bd_net [get_bd_pins sys_concat_intc/In15] [get_bd_pins axi_hdmi_dma/mm2s_introut]
connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2intc_irpt]
for {set intc_index 0} {$intc_index < 14} {incr intc_index} {
set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}]
connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}]
}
# address map
set sys_zynq 1

1
projects/daq2/common/daq2_bd.tcl
View File

@ -337,6 +337,7 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid]
connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready]
connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data]
connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_fifo/axi_xfer_req] [get_bd_pins axi_ad9680_dma/s_axis_xfer_req]
connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_ports axi_ad9680_dma_intr]
# dac/adc clocks

1
projects/daq3/common/daq3_bd.tcl
View File

@ -341,6 +341,7 @@ if {$sys_zynq == 1} {
connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid]
connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready]
connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data]
connect_bd_net -net axi_ad9680_xfer_req [get_bd_pins axi_ad9680_fifo/axi_xfer_req] [get_bd_pins axi_ad9680_dma/s_axis_xfer_req]
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13]
}

78
projects/usdrx1/a5gt/system_bd.qsys
View File

@ -180,14 +180,6 @@
type = "String";
}
}
element sys_gpio.s1
{
datum baseAddress
{
value = "86025408";
type = "String";
}
}
element sys_timer.s1
{
datum baseAddress
@ -209,14 +201,6 @@
type = "String";
}
}
element sys_tcm_mem.s1
{
datum baseAddress
{
value = "86016000";
type = "String";
}
}
element sys_ethernet_desc_mem.s1
{
datum baseAddress
@ -225,6 +209,22 @@
type = "String";
}
}
element sys_gpio.s1
{
datum baseAddress
{
value = "86025408";
type = "String";
}
}
element sys_tcm_mem.s1
{
datum baseAddress
{
value = "86016000";
type = "String";
}
}
element sys_tcm_mem.s2
{
datum baseAddress
@ -246,14 +246,6 @@
type = "String";
}
}
element axi_ad9671_2.s_axi
{
datum baseAddress
{
value = "86114304";
type = "String";
}
}
element axi_ad9671_3.s_axi
{
datum baseAddress
@ -262,6 +254,14 @@
type = "String";
}
}
element axi_ad9671_2.s_axi
{
datum baseAddress
{
value = "86114304";
type = "String";
}
}
element axi_ad9671_0.s_axi
{
datum baseAddress
@ -846,6 +846,26 @@
type="conduit"
dir="end" />
<interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
<interface
name="axi_ad9671_1_xcvr_sync"
internal="axi_ad9671_1.xcvr_sync"
type="conduit"
dir="end" />
<interface
name="axi_ad9671_0_xcvr_sync"
internal="axi_ad9671_0.xcvr_sync"
type="conduit"
dir="end" />
<interface
name="axi_ad9671_2_xcvr_sync"
internal="axi_ad9671_2.xcvr_sync"
type="conduit"
dir="end" />
<interface
name="axi_ad9671_3_xcvr_sync"
internal="axi_ad9671_3.xcvr_sync"
type="conduit"
dir="end" />
<module kind="clock_source" version="14.0" enabled="1" name="sys_clk">
<parameter name="clockFrequency" value="100000000" />
<parameter name="clockFrequencyKnown" value="true" />
@ -2089,31 +2109,27 @@
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_DEVICE_TYPE" value="0" />
<parameter name="PCORE_4L_2L_N" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="3" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
</module>
<module kind="axi_ad9671" version="1.0" enabled="1" name="axi_ad9671_1">
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_ID" value="1" />
<parameter name="PCORE_DEVICE_TYPE" value="0" />
<parameter name="PCORE_4L_2L_N" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="3" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
</module>
<module kind="axi_ad9671" version="1.0" enabled="1" name="axi_ad9671_2">
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_ID" value="2" />
<parameter name="PCORE_DEVICE_TYPE" value="0" />
<parameter name="PCORE_4L_2L_N" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="3" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
</module>
<module kind="axi_ad9671" version="1.0" enabled="1" name="axi_ad9671_3">
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_ID" value="3" />
<parameter name="PCORE_DEVICE_TYPE" value="0" />
<parameter name="PCORE_4L_2L_N" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="3" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
</module>

22
projects/usdrx1/a5gt/system_constr.sdc
View File

@ -1,9 +1,29 @@
create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_ports {eth_tx_clk_out}]
create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
create_clock -period "12.500 ns" -name n_clk_80m [get_ports {ref_clk}]
derive_pll_clocks
derive_clock_uncertainty
set clk_100m {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_166m {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_125m {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_25m {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_2m5 {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_rxlink {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
set_clock_groups -asynchronous -group [get_clocks {n_clk_80m} ]
set_clock_groups -asynchronous -group [get_clocks {n_clk_100m} ]
set_clock_groups -asynchronous -group [get_clocks {n_eth_rx_clk_125m} ]
set_clock_groups -asynchronous -group [get_clocks {n_eth_tx_clk_125m} ]
set_clock_groups -asynchronous -group [get_clocks $clk_100m ]
set_clock_groups -asynchronous -group [get_clocks $clk_166m ]
set_clock_groups -asynchronous -group [get_clocks $clk_125m ]
set_clock_groups -asynchronous -group [get_clocks $clk_25m ]
set_clock_groups -asynchronous -group [get_clocks $clk_2m5 ]
set_clock_groups -asynchronous -group [get_clocks $clk_rxlink ]
set_false_path -from {sys_resetn} -to *
set_false_path -from * -to {sys_resetn}

15
projects/usdrx1/a5gt/system_timing.tcl
View File

@ -1,3 +1,16 @@
report_timing -detail path_only -npaths 20 -file timing_impl.log
set worst_path [get_timing_paths -npaths 1 -setup]
foreach_in_collection path $worst_path {
set slack [get_path_info $path -slack]
}
if {$slack > 0} {
set worst_path [get_timing_paths -npaths 1 -hold]
foreach_in_collection path $worst_path {
set slack [get_path_info $path -slack]
}
}
if {$slack < 0} {
use_this_invalid_command_to_crash
}

20
projects/usdrx1/a5gt/system_top.v
View File

@ -280,6 +280,8 @@ module system_top (
wire rx_pll_locked_s;
wire [ 22:0] rx_xcvr_status_s;
wire [ 7:0] rx_data_sof;
wire [ 3:0] sync_raddr;
wire sync_signal;
// ethernet transmit clock
@ -503,7 +505,23 @@ module system_top (
.axi_ad9671_3_adc_dma_if_enable (adc_enable_3),
.axi_ad9671_3_adc_dma_if_data (adc_data_3),
.axi_ad9671_3_adc_dma_if_dovf (adc_dovf_3),
.axi_ad9671_3_adc_dma_if_dunf (1'b0));
.axi_ad9671_3_adc_dma_if_dunf (1'b0),
.axi_ad9671_0_xcvr_sync_sync_in (),
.axi_ad9671_0_xcvr_sync_sync_out (sync_signal),
.axi_ad9671_0_xcvr_sync_raddr_in (),
.axi_ad9671_0_xcvr_sync_raddr_out (sync_raddr),
.axi_ad9671_1_xcvr_sync_sync_in (sync_signal),
.axi_ad9671_1_xcvr_sync_sync_out (),
.axi_ad9671_1_xcvr_sync_raddr_in (sync_raddr),
.axi_ad9671_1_xcvr_sync_raddr_out(),
.axi_ad9671_2_xcvr_sync_sync_in (sync_signal),
.axi_ad9671_2_xcvr_sync_sync_out (),
.axi_ad9671_2_xcvr_sync_raddr_in (sync_raddr),
.axi_ad9671_2_xcvr_sync_raddr_out (),
.axi_ad9671_3_xcvr_sync_sync_in (sync_signal),
.axi_ad9671_3_xcvr_sync_sync_out (),
.axi_ad9671_3_xcvr_sync_raddr_in (sync_raddr),
.axi_ad9671_3_xcvr_sync_raddr_out ());
endmodule