diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index ee7169628..6142a0c10 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -113,6 +113,10 @@ module axi_ad9361 ( enable, txnrx, + tdd_sync_i, + tdd_sync_o, + tdd_sync_t, + // axi interface s_axi_aclk, @@ -229,6 +233,10 @@ module axi_ad9361 ( output enable; output txnrx; + input tdd_sync_i; + output tdd_sync_o; + output tdd_sync_t; + // axi interface input s_axi_aclk; @@ -403,6 +411,9 @@ module axi_ad9361 ( .tdd_tx_rf_en(tdd_tx_rf_en_s), .tdd_enable (tdd_enable), .tdd_status(tdd_status_s), + .tdd_sync_i(tdd_sync_i), + .tdd_sync_o(tdd_sync_o), + .tdd_sync_t(tdd_sync_t), .tx_valid_i0(dac_valid_i0_s), .tx_valid_q0(dac_valid_q0_s), .tx_valid_i1(dac_valid_i1_s), diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v index 7c8c29215..7c73504a4 100644 --- a/library/axi_ad9361/axi_ad9361_tdd.v +++ b/library/axi_ad9361/axi_ad9361_tdd.v @@ -58,6 +58,12 @@ module axi_ad9361_tdd ( tdd_enable, tdd_status, + // sync signals + + tdd_sync_i, + tdd_sync_o, + tdd_sync_t, + // tx/rx data flow control tx_valid_i0, @@ -109,6 +115,10 @@ module axi_ad9361_tdd ( output tdd_enable; input [ 7:0] tdd_status; + input tdd_sync_i; + output tdd_sync_o; + output tdd_sync_t; + // tx data flow control input tx_valid_i0; @@ -148,40 +158,45 @@ module axi_ad9361_tdd ( output [34:0] tdd_dbg; + reg tdd_enable = 1'b0; + reg tdd_slave_synced = 1'b0; + reg tdd_sync_o = 1'b0; + // internal signals wire rst; wire tdd_enable_s; wire tdd_secondary_s; - wire [ 7:0] tdd_burst_count_s; + wire [ 7:0] tdd_burst_count_s; wire tdd_rx_only_s; wire tdd_tx_only_s; wire tdd_gated_rx_dmapath_s; wire tdd_gated_tx_dmapath_s; - wire [23:0] tdd_counter_init_s; - wire [23:0] tdd_frame_length_s; - wire [23:0] tdd_vco_rx_on_1_s; - wire [23:0] tdd_vco_rx_off_1_s; - wire [23:0] tdd_vco_tx_on_1_s; - wire [23:0] tdd_vco_tx_off_1_s; - wire [23:0] tdd_rx_on_1_s; - wire [23:0] tdd_rx_off_1_s; - wire [23:0] tdd_tx_on_1_s; - wire [23:0] tdd_tx_off_1_s; - wire [23:0] tdd_tx_dp_on_1_s; - wire [23:0] tdd_tx_dp_off_1_s; - wire [23:0] tdd_vco_rx_on_2_s; - wire [23:0] tdd_vco_rx_off_2_s; - wire [23:0] tdd_vco_tx_on_2_s; - wire [23:0] tdd_vco_tx_off_2_s; - wire [23:0] tdd_rx_on_2_s; - wire [23:0] tdd_rx_off_2_s; - wire [23:0] tdd_tx_on_2_s; - wire [23:0] tdd_tx_off_2_s; - wire [23:0] tdd_tx_dp_on_2_s; - wire [23:0] tdd_tx_dp_off_2_s; + wire [23:0] tdd_counter_init_s; + wire [23:0] tdd_frame_length_s; + wire tdd_terminal_type_s; + wire [23:0] tdd_vco_rx_on_1_s; + wire [23:0] tdd_vco_rx_off_1_s; + wire [23:0] tdd_vco_tx_on_1_s; + wire [23:0] tdd_vco_tx_off_1_s; + wire [23:0] tdd_rx_on_1_s; + wire [23:0] tdd_rx_off_1_s; + wire [23:0] tdd_tx_on_1_s; + wire [23:0] tdd_tx_off_1_s; + wire [23:0] tdd_tx_dp_on_1_s; + wire [23:0] tdd_tx_dp_off_1_s; + wire [23:0] tdd_vco_rx_on_2_s; + wire [23:0] tdd_vco_rx_off_2_s; + wire [23:0] tdd_vco_tx_on_2_s; + wire [23:0] tdd_vco_tx_off_2_s; + wire [23:0] tdd_rx_on_2_s; + wire [23:0] tdd_rx_off_2_s; + wire [23:0] tdd_tx_on_2_s; + wire [23:0] tdd_tx_off_2_s; + wire [23:0] tdd_tx_dp_on_2_s; + wire [23:0] tdd_tx_dp_off_2_s; - wire [23:0] tdd_counter_status; + wire [23:0] tdd_counter_status; wire tdd_tx_dp_en_s; @@ -208,7 +223,45 @@ module axi_ad9361_tdd ( assign tdd_rx_valid_q1 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ? (rx_valid_q1 & tdd_rx_rf_en) : rx_valid_q1; - assign tdd_enable = tdd_enable_s; + // assign tdd_enable = tdd_enable_s; + + assign tdd_sync_t = tdd_terminal_type_s; + + // catch generated sync signal + always @(posedge clk) begin + if (rst == 1'b1) begin + tdd_slave_synced <= 1'b0; + end else begin + if(tdd_sync_i == 1) begin + tdd_slave_synced <= 1'b1; + end else begin + tdd_slave_synced <= tdd_slave_synced & tdd_enable_s; + end + end + end + + // generate sync signal + always @(posedge clk) begin + if (rst == 1'b1) begin + tdd_sync_o <= 1'b0; + end else begin + if(~tdd_enable & tdd_enable_s == 1'b1) begin + tdd_sync_o <= 1'b1; + end else begin + tdd_sync_o <= 1'b0; + end + end + end + + // generate tdd enable in function of the terminal type + always @(posedge clk) begin + if (rst == 1'b1) begin + tdd_enable <= 1'b0; + end else begin + tdd_enable <= (tdd_terminal_type_s == 1'b1) ? tdd_enable_s : + (tdd_enable_s & tdd_slave_synced); + end + end // instantiations @@ -224,6 +277,7 @@ module axi_ad9361_tdd ( .tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s), .tdd_counter_init(tdd_counter_init_s), .tdd_frame_length(tdd_frame_length_s), + .tdd_terminal_type(tdd_terminal_type_s), .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v index 5f7f179aa..555d0483b 100644 --- a/library/common/up_tdd_cntrl.v +++ b/library/common/up_tdd_cntrl.v @@ -54,6 +54,7 @@ module up_tdd_cntrl ( tdd_burst_count, tdd_counter_init, tdd_frame_length, + tdd_terminal_type, tdd_vco_rx_on_1, tdd_vco_rx_off_1, tdd_vco_tx_on_1, @@ -107,6 +108,7 @@ module up_tdd_cntrl ( output [ 7:0] tdd_burst_count; output [23:0] tdd_counter_init; output [23:0] tdd_frame_length; + output tdd_terminal_type; output [23:0] tdd_vco_rx_on_1; output [23:0] tdd_vco_rx_off_1; output [23:0] tdd_vco_tx_on_1; @@ -156,6 +158,7 @@ module up_tdd_cntrl ( reg up_tdd_tx_only = 1'h0; reg up_tdd_gated_tx_dmapath = 1'h0; reg up_tdd_gated_rx_dmapath = 1'h0; + reg up_tdd_terminal_type = 1'h0; reg [ 7:0] up_tdd_burst_count = 8'h0; reg [23:0] up_tdd_counter_init = 24'h0; @@ -206,6 +209,7 @@ module up_tdd_cntrl ( up_tdd_tx_only <= 1'h0; up_tdd_gated_tx_dmapath <= 1'h0; up_tdd_gated_rx_dmapath <= 1'h0; + up_tdd_terminal_type <= 1'h0; up_tdd_counter_init <= 24'h0; up_tdd_frame_length <= 24'h0; up_tdd_burst_count <= 8'h0; @@ -246,6 +250,9 @@ module up_tdd_cntrl ( if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin up_tdd_frame_length <= up_wdata[23:0]; end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin + up_tdd_terminal_type <= up_wdata[0]; + end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin up_tdd_vco_rx_on_1 <= up_wdata[23:0]; end @@ -328,6 +335,7 @@ module up_tdd_cntrl ( 8'h11: up_rdata <= {24'h0, up_tdd_burst_count}; 8'h12: up_rdata <= { 8'h0, up_tdd_counter_init}; 8'h13: up_rdata <= { 8'h0, up_tdd_frame_length}; + 8'h14: up_rdata <= {31'h0, up_tdd_terminal_type}; 8'h18: up_rdata <= {24'h0, up_tdd_status_s}; 8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1}; 8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1}; @@ -357,7 +365,7 @@ module up_tdd_cntrl ( // rf tdd control signal CDC - up_xfer_cntrl #(.DATA_WIDTH(14)) i_tdd_control ( + up_xfer_cntrl #(.DATA_WIDTH(15)) i_tdd_control ( .up_rstn(up_rstn), .up_clk(up_clk), .up_data_cntrl({up_tdd_enable, @@ -366,7 +374,8 @@ module up_tdd_cntrl ( up_tdd_tx_only, up_tdd_gated_rx_dmapath, up_tdd_gated_tx_dmapath, - up_tdd_burst_count + up_tdd_burst_count, + up_tdd_terminal_type }), .up_xfer_done(), .d_rst(rst), @@ -377,7 +386,8 @@ module up_tdd_cntrl ( tdd_tx_only, tdd_gated_rx_dmapath, tdd_gated_tx_dmapath, - tdd_burst_count + tdd_burst_count, + tdd_terminal_type })); up_xfer_cntrl #(.DATA_WIDTH(528)) i_tdd_counter_values ( diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 60ffced88..709adfe94 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -20,6 +20,10 @@ create_bd_port -dir O txnrx create_bd_port -dir O tdd_enable +create_bd_port -dir I tdd_sync_i +create_bd_port -dir O tdd_sync_o +create_bd_port -dir O tdd_sync_t + # ad9361 core set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] @@ -78,6 +82,9 @@ ad_connect tx_data_out_p axi_ad9361/tx_data_out_p ad_connect tx_data_out_n axi_ad9361/tx_data_out_n ad_connect enable axi_ad9361/enable ad_connect txnrx axi_ad9361/txnrx +ad_connect tdd_sync_i axi_ad9361/tdd_sync_i +ad_connect tdd_sync_o axi_ad9361/tdd_sync_o +ad_connect tdd_sync_t axi_ad9361/tdd_sync_t ad_connect tdd_enable axi_ad9361/tdd_enable ad_connect axi_ad9361_clk util_adc_pack/clk ad_connect axi_ad9361/adc_valid_i0 util_adc_pack/chan_valid_0 diff --git a/projects/fmcomms2/rfsom/system_constr.xdc b/projects/fmcomms2/rfsom/system_constr.xdc index f94dbc59f..7c20ac70f 100644 --- a/projects/fmcomms2/rfsom/system_constr.xdc +++ b/projects/fmcomms2/rfsom/system_constr.xdc @@ -2,63 +2,64 @@ # constraints # ad9361 -set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35 -set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35 -set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35 -set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35 -set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35 -set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35 -set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35 -set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35 -set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35 -set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35 -set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35 -set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35 -set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35 -set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35 -set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35 -set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35 -set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35 -set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35 -set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35 -set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35 -set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35 -set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35 -set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35 -set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35 -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35 -set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35 -set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35 -set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35 -set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35 -set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35 -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35 -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35 -set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35 -set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35 +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35 +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35 +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35 +set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35 +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35 +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35 +set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35 +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35 +set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35 +set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35 +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35 +set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35 +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35 +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35 +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35 +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35 +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35 +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35 +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35 +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35 +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35 +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35 +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35 +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35 +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35 +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35 +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35 +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35 +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35 +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35 +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35 +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35 +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35 +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35 +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## IO_L24_13_JX2_N -set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35 -set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35 -set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35 -set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35 -set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35 -set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35 -set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35 -set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35 -set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34 -set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34 -set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34 -set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34 -set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## IO_L10P_T1_AD11P_35 -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35 -set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## IO_0_VRN_35 -set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports gpio_clksel] ; ## IO_0_VRN_34 +set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35 +set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35 +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35 +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35 +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35 +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35 +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35 +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35 +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34 +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34 +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34 +set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34 +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## IO_L10P_T1_AD11P_35 +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35 +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## IO_0_VRN_35 +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports gpio_clksel] ; ## IO_0_VRN_34 set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable] ; ## IO_25_VRP_34 -set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35 -set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## IO_L23N_T3_35 -set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35 -set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35 +set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35 +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## IO_L23N_T3_35 +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35 +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35 # clocks diff --git a/projects/fmcomms2/rfsom/system_top.v b/projects/fmcomms2/rfsom/system_top.v index a5b7f1549..a1f47b0a6 100644 --- a/projects/fmcomms2/rfsom/system_top.v +++ b/projects/fmcomms2/rfsom/system_top.v @@ -110,6 +110,7 @@ module system_top ( enable, txnrx, + tdd_sync, gpio_rfpwr_enable, gpio_clksel, @@ -194,6 +195,7 @@ module system_top ( output enable; output txnrx; + inout tdd_sync; inout gpio_rfpwr_enable; inout gpio_clksel; @@ -221,6 +223,10 @@ module system_top ( wire enable_s; wire txnrx_s; + wire tdd_sync_t_s; + wire tdd_sync_o_s; + wire tdd_sync_i_s; + // assignments assign hdmi_pd = 1'b0; @@ -249,6 +255,12 @@ module system_top ( .dio_o (gpio_i[11:0]), .dio_p (gpio_bd)); + ad_iobuf #(.DATA_WIDTH(1)) i_tdd_sync ( + .dio_t (tdd_sync_t_s), + .dio_i (tdd_sync_o_s), + .dio_o (tdd_sync_i_s), + .dio_p (tdd_sync)); + system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), @@ -349,7 +361,10 @@ module system_top ( .tx_frame_out_n (tx_frame_out_n), .tx_frame_out_p (tx_frame_out_p), .txnrx (txnrx_s), - .tdd_enable (tdd_enable_s)); + .tdd_enable (tdd_enable_s), + .tdd_sync_i (tdd_sync_i_s), + .tdd_sync_o (tdd_sync_o_s), + .tdd_sync_t (tdd_sync_t_s)); endmodule diff --git a/projects/fmcomms2/zc706/system_constr.xdc b/projects/fmcomms2/zc706/system_constr.xdc index 323bcd825..a6384218f 100644 --- a/projects/fmcomms2/zc706/system_constr.xdc +++ b/projects/fmcomms2/zc706/system_constr.xdc @@ -36,6 +36,7 @@ set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_o set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N +set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## PMOD1_7_LS set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N diff --git a/projects/fmcomms2/zc706/system_top.v b/projects/fmcomms2/zc706/system_top.v index df3db223a..dc5294c96 100644 --- a/projects/fmcomms2/zc706/system_top.v +++ b/projects/fmcomms2/zc706/system_top.v @@ -92,6 +92,7 @@ module system_top ( enable, txnrx, + tdd_sync, gpio_muxout_tx, gpio_muxout_rx, @@ -162,6 +163,7 @@ module system_top ( output enable; output txnrx; + inout tdd_sync; inout gpio_muxout_tx; inout gpio_muxout_rx; @@ -213,6 +215,9 @@ module system_top ( wire gpio_txnrx; wire enable_s; wire txnrx_s; + wire tdd_sync_t_s; + wire tdd_sync_o_s; + wire tdd_sync_i_s; // internal logic @@ -241,6 +246,12 @@ module system_top ( .dio_o (gpio_i[14:0]), .dio_p (gpio_bd)); + ad_iobuf #(.DATA_WIDTH(1)) i_tdd_sync ( + .dio_t (tdd_sync_t_s), + .dio_i (tdd_sync_o_s), + .dio_o (tdd_sync_i_s), + .dio_p (tdd_sync)); + system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), @@ -318,7 +329,10 @@ module system_top ( .tx_frame_out_n (tx_frame_out_n), .tx_frame_out_p (tx_frame_out_p), .txnrx (txnrx_s), - .tdd_enable (tdd_enable_s)); + .tdd_enable (tdd_enable_s), + .tdd_sync_i (tdd_sync_i_s), + .tdd_sync_o (tdd_sync_o_s), + .tdd_sync_t (tdd_sync_t_s)); endmodule