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axi_adc_trigger: equalize delay paths 

- Change the trigger delay path to match between the internal and
external(axi_logic_analyzer delays).
main
AndreiGrozav 2019-09-06 15:57:54 +03:00 committed by AndreiGrozav
parent 9f112640f3
commit cfc8ff51e1
1 changed files with 5 additions and 3 deletions
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8
library/axi_adc_trigger/axi_adc_trigger.v
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@ -62,7 +62,7 @@ module axi_adc_trigger #(
output data_valid_a_trig, output data_valid_a_trig,
output data_valid_b_trig, output data_valid_b_trig,
output trigger_out, output trigger_out,
output reg trigger_out_la, output trigger_out_la,
output [31:0] fifo_depth, output [31:0] fifo_depth,
@ -198,6 +198,7 @@ module axi_adc_trigger #(
reg [31:0] trigger_delay_counter; reg [31:0] trigger_delay_counter;
reg triggered; reg triggered;
reg trigger_out_m1; reg trigger_out_m1;
reg trigger_out_m2;
reg streaming_on; reg streaming_on;
reg trigger_out_hold; reg trigger_out_hold;
@ -275,6 +276,7 @@ module axi_adc_trigger #(
// The data goes through and it is delayed with 4 clock cycles) // The data goes through and it is delayed with 4 clock cycles)
always @(posedge clk) begin always @(posedge clk) begin
trigger_out_m1 <= trigger_out_s; trigger_out_m1 <= trigger_out_s;
trigger_out_m2 <= trigger_out_m1;
if (trigger_out_m1 & ~trigger_out_s) begin if (trigger_out_m1 & ~trigger_out_s) begin
trigger_out_hold <= 1'b1; trigger_out_hold <= 1'b1;
end end
@ -285,10 +287,10 @@ module axi_adc_trigger #(
trigger_out_ack <= trigger_out_hold & (data_valid_a | data_valid_b); trigger_out_ack <= trigger_out_hold & (data_valid_a | data_valid_b);
// triggers logic analyzer // triggers logic analyzer
trigger_out_la <= trigger_out_mixed;
end end
assign trigger_out = trigger_out_hold | trigger_out_m1; assign trigger_out_la = trigger_out_mixed;
assign trigger_out = trigger_out_hold | trigger_out_m2;
// the embedded trigger does not require any extra delay, since the util_extract // the embedded trigger does not require any extra delay, since the util_extract
// present in this case, delays the trigger with 2 clock cycles // present in this case, delays the trigger with 2 clock cycles