From c8b56253d7b95d997946ab88c30435b73ca7f679 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 12 Mar 2015 16:49:46 +0200 Subject: [PATCH 01/18] axi_i2s_adi: Fixed pins directions --- library/axi_i2s_adi/axi_i2s_adi.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/library/axi_i2s_adi/axi_i2s_adi.vhd b/library/axi_i2s_adi/axi_i2s_adi.vhd index 9d3bd5a6a..b1728d22b 100644 --- a/library/axi_i2s_adi/axi_i2s_adi.vhd +++ b/library/axi_i2s_adi/axi_i2s_adi.vhd @@ -99,10 +99,10 @@ entity axi_i2s_adi is S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; - S_AXI_WREADY : inout std_logic; + S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); - S_AXI_BVALID : inout std_logic; - S_AXI_AWREADY : inout std_logic + S_AXI_BVALID : out std_logic; + S_AXI_AWREADY : out std_logic ); end entity axi_i2s_adi; From 1c0d5fbb5158845db542a00e20786807bca4e429 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 12 Mar 2015 16:51:31 +0200 Subject: [PATCH 02/18] utiil_gmii_to_rgmii: registerd Rx/ Tx paths. Changed RX clock buffers to a single BUFG --- .../util_gmii_to_rgmii/util_gmii_to_rgmii.v | 89 ++++++++----------- 1 file changed, 37 insertions(+), 52 deletions(-) diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v index 5c165cc67..3ad00a845 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v @@ -103,13 +103,8 @@ module util_gmii_to_rgmii ( wire clk_100msps; wire [ 3:0] rgmii_rd_delay; wire [ 7:0] gmii_rxd_s; - wire [ 3:0] gmii_txd_low; wire rgmii_rx_ctl_delay; - wire gmii_rx_er_s; - wire rgmii_rxc_s; - wire rgmii_rx_ctl_clk_s; wire rgmii_rx_ctl_s; - wire rgmii_rxc_bufmr; wire [ 1:0] speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps wire duplex_mode; // 1 full, 0 half @@ -118,30 +113,45 @@ module util_gmii_to_rgmii ( reg tx_reset_d1; reg tx_reset_sync; reg rx_reset_d1; - reg rx_reset_sync; reg [ 7:0] gmii_txd_r; reg gmii_tx_en_r; reg gmii_tx_er_r; + reg [ 7:0] gmii_txd_r_d1; + reg gmii_tx_en_r_d1; + reg gmii_tx_er_r_d1; + + reg rgmii_tx_ctl_r; + reg [ 3:0] gmii_txd_low; + reg gmii_col; + reg gmii_crs; + + reg [ 7:0] gmii_rxd; + reg gmii_rx_dv; + reg gmii_rx_er; - // assignments assign gigabit = speed_selection [1]; - assign gmii_tx_clk = gmii_tx_clk_s; - assign rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r; - assign gmii_txd_low = gigabit ? gmii_txd_r[7:4] : gmii_txd_r[3:0]; - assign gmii_col = duplex_mode ? 1'b0 : (gmii_tx_en_r | gmii_tx_er_r) & ( gmii_rx_dv_s | gmii_rx_er_s) ; - assign gmii_crs = duplex_mode ? 1'b0 : (gmii_tx_en_r | gmii_tx_er_r | gmii_rx_dv_s | gmii_rx_er_s); - assign gmii_rxd = gmii_rxd_s; - assign gmii_rx_dv = gmii_rx_dv_s; - assign gmii_rx_er = gmii_rx_er_s; - assign gmii_rx_er_s = gmii_rx_dv_s ^ rgmii_rx_ctl_s; + always @(posedge gmii_rx_clk) + begin + gmii_rxd = gmii_rxd_s; + gmii_rx_dv = gmii_rx_dv_s; + gmii_rx_er = gmii_rx_dv_s ^ rgmii_rx_ctl_s; + end always @(posedge gmii_tx_clk_s) begin tx_reset_d1 <= reset; tx_reset_sync <= tx_reset_d1; end + always @(posedge gmii_tx_clk_s) + begin + rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r; + gmii_txd_low = gigabit ? gmii_txd_r[7:4] : gmii_txd_r[3:0]; + gmii_col = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r) & ( gmii_rx_dv | gmii_rx_er) ; + gmii_crs = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r| gmii_rx_dv | gmii_rx_er); + end + always @(posedge gmii_tx_clk_s) begin if (tx_reset_sync == 1'b1) begin gmii_txd_r <= 8'h0; @@ -153,6 +163,9 @@ module util_gmii_to_rgmii ( gmii_txd_r <= gmii_txd; gmii_tx_en_r <= gmii_tx_en; gmii_tx_er_r <= gmii_tx_er; + gmii_txd_r_d1 <= gmii_txd_r; + gmii_tx_en_r_d1 <= gmii_tx_en_r; + gmii_tx_er_r_d1 <= gmii_tx_er_r; end end @@ -201,7 +214,7 @@ module util_gmii_to_rgmii ( .Q (rgmii_td[i]), .C (gmii_tx_clk_s), .CE(1), - .D1(gmii_txd_r[i]), + .D1(gmii_txd_r_d1[i]), .D2(gmii_txd_low[i]), .R(tx_reset_sync), .S(0)); @@ -214,41 +227,13 @@ module util_gmii_to_rgmii ( .Q (rgmii_tx_ctl), .C (gmii_tx_clk_s), .CE(1), - .D1(gmii_tx_en_r), + .D1(gmii_tx_en_r_d1), .D2(rgmii_tx_ctl_r), .R(tx_reset_sync), .S(0)); - - always @(posedge rgmii_rxc_s) begin - rx_reset_d1 <= reset; - rx_reset_sync <= rx_reset_d1; - end - - BUFMR bufmr_rgmii_rxc( + BUFG bufmr_rgmii_rxc( .I(rgmii_rxc), - .O(rgmii_rxc_bufmr)); - - BUFR #( - .SIM_DEVICE("7SERIES"), - .BUFR_DIVIDE(1) - ) bufr_rgmii_rx_clk ( - .I(rgmii_rxc_bufmr), - .CE(1), - .CLR(0), - .O(rgmii_rxc_s)); - - BUFR #( - .SIM_DEVICE("7SERIES"), - .BUFR_DIVIDE(1) - ) bufr_rgmii_rx_ctl_clk ( - .I(rgmii_rxc_bufmr), - .CE(1), - .CLR(0), - .O(rgmii_rx_ctl_clk_s)); - - BUFG bufg_rgmii_rx_clk ( - .I(rgmii_rxc_s), .O(gmii_rx_clk)); IDELAYE2 #( @@ -275,9 +260,9 @@ module util_gmii_to_rgmii ( for (i = 0; i < 4; i = i + 1) begin IDELAYE2 #( .IDELAY_TYPE("FIXED"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA"), .DELAY_SRC("IDATAIN") ) delay_rgmii_rd ( .IDATAIN(rgmii_rd[i]), @@ -298,7 +283,7 @@ module util_gmii_to_rgmii ( ) rgmii_rx_iddr ( .Q1(gmii_rxd_s[i]), .Q2(gmii_rxd_s[i+4]), - .C(rgmii_rxc_s), + .C(gmii_rx_clk), .CE(1), .D(rgmii_rd_delay[i]), .R(0), @@ -311,7 +296,7 @@ module util_gmii_to_rgmii ( ) rgmii_rx_ctl_iddr ( .Q1(gmii_rx_dv_s), .Q2(rgmii_rx_ctl_s), - .C(rgmii_rx_ctl_clk_s), + .C(gmii_rx_clk), .CE(1), .D(rgmii_rx_ctl_delay), .R(0), From f62bc5cc9a737c8bd69de8e64cffb67659a5b444 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 12 Mar 2015 16:55:36 +0200 Subject: [PATCH 03/18] motcon2_fmc: Updated design - separated clocks for ethernet and other cores in the design - removed constraints that were not needed --- .../motcon2_fmc/common/motcon2_fmc_bd.tcl | 21 +-- projects/motcon2_fmc/zed/system_constr.xdc | 134 +++++------------- 2 files changed, 48 insertions(+), 107 deletions(-) diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index e3ffa0597..e557b6f6a 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -107,9 +107,14 @@ set_property -dict [ list CONFIG.CLKOUT2_USED {true} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT3_USED {true} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT4_USED {true} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT5_USED {true} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT2_DRIVES {No_buffer} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT3_DRIVES {No_buffer} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT4_DRIVES {No_buffer} ] $sys_audio_clkgen # speed detectors # speed detector core motor 1 @@ -281,7 +286,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/m_dest_axi_aresetn] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net adc_m1_ia_dat_i_1 [get_bd_ports adc_m1_ia_dat_i] [get_bd_pins current_monitor_m1/adc_ia_dat_i] connect_bd_net -net adc_m1_ib_dat_i_1 [get_bd_ports adc_m1_ib_dat_i] [get_bd_pins current_monitor_m1/adc_ib_dat_i] connect_bd_net -net adc_m1_vbus_dat_i_1 [get_bd_ports adc_m1_vbus_dat_i] [get_bd_pins current_monitor_m1/adc_vbus_dat_i] @@ -330,7 +335,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/m_dest_axi_aresetn] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net adc_m2_ia_dat_i_1 [get_bd_ports adc_m2_ia_dat_i] [get_bd_pins current_monitor_m2/adc_ia_dat_i] connect_bd_net -net adc_m2_ib_dat_i_1 [get_bd_ports adc_m2_ib_dat_i] [get_bd_pins current_monitor_m2/adc_ib_dat_i] connect_bd_net -net adc_m2_vbus_dat_i_1 [get_bd_ports adc_m2_vbus_dat_i] [get_bd_pins current_monitor_m2/adc_vbus_dat_i] @@ -375,7 +380,7 @@ # motor 1 connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/ref_clk] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1/s_axi_aresetn] $sys_100m_resetn_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/s_axi_aclk] $sys_100m_clk_source @@ -464,7 +469,7 @@ # motor 2 connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/s_axi_aclk] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/ref_clk] $sys_100m_clk_source - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2/s_axi_aresetn] $sys_100m_resetn_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/s_axi_aclk] $sys_100m_clk_source @@ -568,9 +573,9 @@ connect_bd_intf_net -intf_net gmii_to_rgmii_eth1_rgmii [get_bd_intf_ports eth1_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth1/rgmii] connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset] [get_bd_pins sys_rstgen/peripheral_reset] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth1/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] - connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth1/mdio_mdc] connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_w] connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_r] @@ -578,9 +583,9 @@ connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_2 [get_bd_intf_pins gmii_to_rgmii_eth2/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1] connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/rgmii] connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset] [get_bd_pins sys_rstgen/peripheral_reset] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth2/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] - connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth2/mdio_mdc] connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_w] diff --git a/projects/motcon2_fmc/zed/system_constr.xdc b/projects/motcon2_fmc/zed/system_constr.xdc index d4546f3f6..271018fdb 100644 --- a/projects/motcon2_fmc/zed/system_constr.xdc +++ b/projects/motcon2_fmc/zed/system_constr.xdc @@ -48,16 +48,6 @@ set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25 } [get_ports {gpo[3]}] set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}] set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}] - -#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 -#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 -#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 -#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 -#set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}] -#set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}] -#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}] -#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}] - set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0] set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8] set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0] @@ -88,12 +78,12 @@ set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_ set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}] set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}] set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}] -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_txc] -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_tx_ctl] -set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[0]}] -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[1]}] -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[2]}] -set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[3]}] +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_txc] +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_tx_ctl] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[0]}] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[1]}] +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[2]}] +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[3]}] # Ethernet 2 set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc] @@ -102,20 +92,26 @@ set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_ set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}] set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}] set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}] -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_txc] -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_tx_ctl] -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[0]}] -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[1]}] -set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}] -set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}] +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_txc] +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_tx_ctl] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[0]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[1]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[2]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[3]}] + + +#create clocks +# Clock Period Constraints +create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC] + +create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc] + +create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc] create_generated_clock -name pwm_ctrl_1 -source [get_pins i_system_wrapper/system_i/controller_m1/inst/ref_clk] \ -divide_by 2 [get_pins i_system_wrapper/system_i/controller_m1/inst/pwm_gen_clk_reg/Q] create_generated_clock -name pwm_ctrl_2 -source [get_pins i_system_wrapper/system_i/controller_m2/inst/ref_clk] \ -divide_by 2 [get_pins i_system_wrapper/system_i/controller_m2/inst/pwm_gen_clk_reg/Q] -set_clock_groups -asynchronous \ - -group [get_clocks {pwm_ctrl_1}] \ - -group [get_clocks {pwm_ctrl_2}] create_generated_clock -name cm1_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/ia_if/filter/word_count_reg[7]/Q] @@ -124,9 +120,6 @@ create_generated_clock -name cm1_ib -source [get_pins i_system_wrapper/system_i/ create_generated_clock -name cm1_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/vbus_if/filter/word_count_reg[7]/Q] -set_clock_groups -asynchronous \ - -group [get_clocks {cm1_ia cm1_ib cm1_vbus }] - create_generated_clock -name cm2_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/ia_if/filter/word_count_reg[7]/Q] create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ @@ -134,87 +127,30 @@ create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/ create_generated_clock -name cm2_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/vbus_if/filter/word_count_reg[7]/Q] +set_clock_groups -asynchronous \ + -group [get_clocks {cm1_ia cm1_ib cm1_vbus }] + set_clock_groups -asynchronous \ -group [get_clocks {cm2_ia cm2_ib cm2_vbus }] +set_clock_groups -asynchronous \ + -group [get_clocks {pwm_ctrl_1 }] \ + -group [get_clocks {pwm_ctrl_2 }] + # Ethernet common set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl] -create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC] - -set_clock_groups -logically_exclusive \ - -group [get_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks {clk_out4_system_sys_audio_clkgen_0_1 }] - -set_clock_groups -asynchronous \ - -group [get_clocks {mdio_mdc}] \ - -group [get_clocks -include_generated_clocks {clk_out1_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks -include_generated_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks -include_generated_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks -include_generated_clocks {clk_out4_system_sys_audio_clkgen_0_1}] - # Ethernet 1 - -# Clock Period Constraints -create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc] -#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1] -#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1] - -create_clock -name eth1_rx_clk_vir -period 8 - -set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] -set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] +#IDELAY +set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] +set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max 1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] - -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -setup -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -setup -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -hold -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -hold - -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -setup -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -setup -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -hold -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -hold - -set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to [get_clocks rgmii_rx_ctl_clk_s] -setup 0 -create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc] -#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1] -#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1] - -create_clock -name eth2_rx_clk_vir -period 8 -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmii_to_rgmii_eth2/inst/clk_100msps] -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3] - - -set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] -set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] +# Ethernet 2 +#IDELAY +set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] +set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] - -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max 1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -0.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -0.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] - -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold - -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -setup -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -setup -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -hold -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -hold - -set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay -set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay From bc68a4e9390fb98075b5aa686bf9d9be2ed74fcf Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:55:41 -0400 Subject: [PATCH 04/18] common-base-designs: add intr net names --- projects/common/ac701/ac701_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 3be137cb8..243f7bcce 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -342,7 +342,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2 for {set intc_index 10} {$intc_index < 32} {incr intc_index} { set mb_intr_${intc_index} [create_bd_port -dir I mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] + connect_bd_net -net mb_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } # defaults (external interface) From 19c79e685b4b8adc508e2e857d400890ae89e9ae Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:55:50 -0400 Subject: [PATCH 05/18] common-base-designs: add intr net names --- projects/common/kc705/kc705_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 386fa19d2..f93085a81 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -331,7 +331,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2 for {set intc_index 10} {$intc_index < 32} {incr intc_index} { set mb_intr_${intc_index} [create_bd_port -dir I -type intr mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] + connect_bd_net -net mb_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } # defaults (external interface) From bc837a67f03e7dde85d49303fdd13c588d6b5a1d Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:55:59 -0400 Subject: [PATCH 06/18] common-base-designs: add intr net names --- projects/common/mitx045/mitx045_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index e8cf2d339..b38b19cec 100755 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -237,7 +237,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From 4931bca1f7a73537adcf0b89c92d72e40542492b Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:06 -0400 Subject: [PATCH 07/18] common-base-designs: add intr net names --- projects/common/vc707/vc707_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 36d339c54..da1544056 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -354,7 +354,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2 for {set intc_index 10} {$intc_index < 32} {incr intc_index} { set mb_intr_${intc_index} [create_bd_port -dir I -type intr mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] + connect_bd_net -net mb_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } # defaults (external interface) From d767e590e8cfbb9eab1f55f9ee127f9b29b0650c Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:15 -0400 Subject: [PATCH 08/18] common-base-designs: add intr net names --- projects/common/zc702/zc702_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 694c13417..462ab6f12 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -198,7 +198,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From e689471ee60b52630477b71de289fa6144e92df8 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:25 -0400 Subject: [PATCH 09/18] common-base-designs: add intr net names --- projects/common/zc706/zc706_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index f1f9c2d33..81561c413 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -201,7 +201,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From e4494efc91b36018e8ba731cf51952f5b2e35dab Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:31 -0400 Subject: [PATCH 10/18] common-base-designs: add intr net names --- projects/common/zed/zed_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 83080b1a0..008895515 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -285,7 +285,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From 6ee02f7ade992ae03eb9b026b38eae05f7022e86 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:57:35 -0400 Subject: [PATCH 11/18] fmcomms2: intrs within ipi --- projects/fmcomms2/common/fmcomms2_bd.tcl | 29 ++++++++++++------------ 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index c9814c302..7ee03021a 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -42,16 +42,6 @@ if {$sys_zynq == 1} { set spi_udc_miso_i [create_bd_port -dir I spi_udc_miso_i] } - # interrupts - - set ad9361_adc_dma_irq [create_bd_port -dir O ad9361_adc_dma_irq] - set ad9361_dac_dma_irq [create_bd_port -dir O ad9361_dac_dma_irq] - -if {$sys_zynq == 0} { - set fmcomms2_gpio_irq [create_bd_port -dir O fmcomms2_gpio_irq] - set fmcomms2_spi_irq [create_bd_port -dir O fmcomms2_spi_irq] -} - # ad9361 core set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] @@ -161,7 +151,6 @@ if {$sys_zynq == 0} { connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins axi_fmcomms2_spi/io0_i] connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins axi_fmcomms2_spi/io0_o] connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins axi_fmcomms2_spi/io1_i] - connect_bd_net -net axi_fmcomms2_spi_irq [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] [get_bd_ports fmcomms2_spi_irq] } else { connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O] @@ -178,7 +167,6 @@ if {$sys_zynq == 0} { connect_bd_net -net gpio_fmcomms2_i [get_bd_ports gpio_fmcomms2_i] [get_bd_pins axi_fmcomms2_gpio/gpio_io_i] connect_bd_net -net gpio_fmcomms2_o [get_bd_ports gpio_fmcomms2_o] [get_bd_pins axi_fmcomms2_gpio/gpio_io_o] connect_bd_net -net gpio_fmcomms2_t [get_bd_ports gpio_fmcomms2_t] [get_bd_pins axi_fmcomms2_gpio/gpio_io_t] - connect_bd_net -net axi_fmcomms2_gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_ports fmcomms2_gpio_irq] } # connections (up/down converter spi) @@ -251,8 +239,21 @@ if {$sys_zynq == 1} { connect_bd_net -net axi_ad9361_dac_drd [get_bd_pins util_dac_unpack/dma_rd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en] connect_bd_net -net axi_ad9361_dac_dunf [get_bd_pins axi_ad9361/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins ad9361_adc_dma_irq] - connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins ad9361_dac_dma_irq] + if {$sys_zynq == 0} { + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] + delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net axi_fmcomms2_spi_irq [get_bd_pins sys_concat_intc/In10] [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] + connect_bd_net -net axi_fmcomms2_gpio_irq [get_bd_pins sys_concat_intc/In11] [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] + connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins sys_concat_intc/In12] [get_bd_pins axi_ad9361_adc_dma/irq] + connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins sys_concat_intc/In13] [get_bd_pins axi_ad9361_dac_dma/irq] + } else { + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins sys_concat_intc/In12] [get_bd_pins axi_ad9361_dac_dma/irq] + connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins sys_concat_intc/In13] [get_bd_pins axi_ad9361_adc_dma/irq] + } # interconnect (cpu) From 15a0de80a933d687cca2552898f422bf0d0c2024 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:37 -0400 Subject: [PATCH 12/18] fmcomms2: intrs within ipi --- projects/fmcomms2/ac701/system_top.v | 8 -------- 1 file changed, 8 deletions(-) diff --git a/projects/fmcomms2/ac701/system_top.v b/projects/fmcomms2/ac701/system_top.v index 78d581ad7..41bddcb8c 100644 --- a/projects/fmcomms2/ac701/system_top.v +++ b/projects/fmcomms2/ac701/system_top.v @@ -249,10 +249,6 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -271,10 +267,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .fmcomms2_spi_irq(mb_intrs[10]), - .fmcomms2_gpio_irq(mb_intrs[11]), - .ad9361_adc_dma_irq (mb_intrs[12]), - .ad9361_dac_dma_irq (mb_intrs[13]), .mdio_io (phy_mdio), .mdio_mdc (phy_mdc), .phy_rst_n (phy_reset_n), From 0fcd47f5ea8b7a2823eb27463dc4d04e40ecdf45 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:44 -0400 Subject: [PATCH 13/18] fmcomms2: intrs within ipi --- projects/fmcomms2/kc705/system_top.v | 8 -------- 1 file changed, 8 deletions(-) diff --git a/projects/fmcomms2/kc705/system_top.v b/projects/fmcomms2/kc705/system_top.v index 6b6dd4372..40155f0b1 100644 --- a/projects/fmcomms2/kc705/system_top.v +++ b/projects/fmcomms2/kc705/system_top.v @@ -275,10 +275,6 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -297,10 +293,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .fmcomms2_spi_irq(mb_intrs[10]), - .fmcomms2_gpio_irq(mb_intrs[11]), - .ad9361_adc_dma_irq (mb_intrs[12]), - .ad9361_dac_dma_irq (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio_io), .mii_col (mii_col), From 5faced7eaa13e76bb33d8a6bcc8e226a0d033c13 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:49 -0400 Subject: [PATCH 14/18] fmcomms2: intrs within ipi --- projects/fmcomms2/mitx045/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/mitx045/system_top.v b/projects/fmcomms2/mitx045/system_top.v index 6139f4045..90c11a6f2 100644 --- a/projects/fmcomms2/mitx045/system_top.v +++ b/projects/fmcomms2/mitx045/system_top.v @@ -242,8 +242,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -252,8 +250,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), From 70e5d5c13970af3976956a3bc2de0d3c27dc0b12 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:55 -0400 Subject: [PATCH 15/18] fmcomms2: intrs within ipi --- projects/fmcomms2/vc707/system_top.v | 8 -------- 1 file changed, 8 deletions(-) diff --git a/projects/fmcomms2/vc707/system_top.v b/projects/fmcomms2/vc707/system_top.v index 4058a3237..5a682959c 100644 --- a/projects/fmcomms2/vc707/system_top.v +++ b/projects/fmcomms2/vc707/system_top.v @@ -272,10 +272,6 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -294,10 +290,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .fmcomms2_spi_irq(mb_intrs[10]), - .fmcomms2_gpio_irq(mb_intrs[11]), - .ad9361_adc_dma_irq (mb_intrs[12]), - .ad9361_dac_dma_irq (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .mgt_clk_clk_n (mgt_clk_n), From a9b5e07e76e65858df287d0e3b3147158357126d Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:59:03 -0400 Subject: [PATCH 16/18] fmcomms2: intrs within ipi --- projects/fmcomms2/zc702/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/zc702/system_top.v b/projects/fmcomms2/zc702/system_top.v index 5eba2dd0d..a4055aae7 100644 --- a/projects/fmcomms2/zc702/system_top.v +++ b/projects/fmcomms2/zc702/system_top.v @@ -236,8 +236,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -246,8 +244,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), From c5fcec1f2f326c487a2228f59ef932dd95207c22 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:59:10 -0400 Subject: [PATCH 17/18] fmcomms2: intrs within ipi --- projects/fmcomms2/zc706/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/zc706/system_top.v b/projects/fmcomms2/zc706/system_top.v index 5e95536b5..84f2a95d5 100644 --- a/projects/fmcomms2/zc706/system_top.v +++ b/projects/fmcomms2/zc706/system_top.v @@ -233,8 +233,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -243,8 +241,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), From fac1434dccf6969f34b61498000cada26f72e5ac Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:59:16 -0400 Subject: [PATCH 18/18] fmcomms2: intrs within ipi --- projects/fmcomms2/zed/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/zed/system_top.v b/projects/fmcomms2/zed/system_top.v index 1f08eb0bb..9cef3446c 100644 --- a/projects/fmcomms2/zed/system_top.v +++ b/projects/fmcomms2/zed/system_top.v @@ -282,8 +282,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -292,8 +290,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .iic_fmc_intr(ps_intrs[11]), .otg_vbusoc (otg_vbusoc), .rx_clk_in_n (rx_clk_in_n),