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motor_control: added the MW FOC IP and updated the design

main
acozma 2014-09-01 18:34:19 +03:00
parent ee752ec08a
commit d08d0cd70b
108 changed files with 19149 additions and 166 deletions
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463
library/axi_mc_controller/axi_mc_controller.v
View File

@ -45,6 +45,7 @@ module axi_mc_controller
)
(
input ref_clk, // 100 MHz
input ctrl_data_clk,
// physical interface
@ -60,29 +61,55 @@ module axi_mc_controller
// controller connections
input [31:0] err_i,
input [31:0] pwm_i,
input [31:0] speed_rpm_i,
output ctrl_rst_o,
output [31:0] ref_speed_o,
output [31:0] kp_o,
output [31:0] ki_o,
output [31:0] kd_o,
input pwm_a_i,
input pwm_b_i,
input pwm_c_i,
input ctrl_data_valid_i,
input [31:0] ctrl_data0_i,
input [31:0] ctrl_data1_i,
input [31:0] ctrl_data2_i,
input [31:0] ctrl_data3_i,
input [31:0] ctrl_data4_i,
input [31:0] ctrl_data5_i,
input [31:0] ctrl_data6_i,
input [31:0] ctrl_data7_i,
// interconnection with other modules
output [1:0] sensors_o,
input [2:0] position_i,
input new_speed_i,
input [31:0] speed_i,
// dma interface
output adc_clk_o,
output adc_dwr_o,
output [31:0] adc_ddata_o,
input adc_dovf_i,
input adc_dunf_i,
output adc_enable_c0,
output adc_enable_c1,
output adc_enable_c2,
output adc_enable_c3,
output adc_enable_c4,
output adc_enable_c5,
output adc_enable_c6,
output adc_enable_c7,
output adc_valid_c0,
output adc_valid_c1,
output adc_valid_c2,
output adc_valid_c3,
output adc_valid_c4,
output adc_valid_c5,
output adc_valid_c6,
output adc_valid_c7,
output [31:0] adc_data_c0,
output [31:0] adc_data_c1,
output [31:0] adc_data_c2,
output [31:0] adc_data_c3,
output [31:0] adc_data_c4,
output [31:0] adc_data_c5,
output [31:0] adc_data_c6,
output [31:0] adc_data_c7,
// axi interface
@ -104,12 +131,7 @@ module axi_mc_controller
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
// debug signals
output adc_mon_valid,
output [31:0] adc_mon_data
input s_axi_rready
);
//------------------------------------------------------------------------------
@ -141,24 +163,41 @@ wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire [31:0] up_control_rdata_s;
wire [31:0] rdata_ref_speed_s;
wire [31:0] rdata_actual_speed_s;
wire [31:0] rdata_c0_s;
wire [31:0] rdata_c1_s;
wire [31:0] rdata_c2_s;
wire [31:0] rdata_c3_s;
wire [31:0] rdata_c4_s;
wire [31:0] rdata_c5_s;
wire [31:0] rdata_c6_s;
wire [31:0] rdata_c7_s;
wire up_adc_common_ack_s;
wire up_control_ack_s;
wire ack_ref_speed_s;
wire ack_actual_speed_s;
wire ack_c0_s;
wire ack_c1_s;
wire ack_c2_s;
wire ack_c3_s;
wire ack_c4_s;
wire ack_c5_s;
wire ack_c6_s;
wire ack_c7_s;
wire run_s;
wire star_delta_s;
wire oloop_matlab_s; // 0 - open loop, 1 matlab controlls pwm
wire dir_s;
wire [10:0] pwm_open_s;
wire [10:0] pwm_s;
wire enable_ref_speed_s;
wire enable_actual_speed_s;
wire [10:0] gpo_s;
wire dpwm_ah_s;
wire dpwm_al_s;
wire dpwm_bh_s;
wire dpwm_bl_s;
wire dpwm_ch_s;
wire dpwm_cl_s;
wire foc_ctrl_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
@ -168,19 +207,40 @@ wire [10:0] gpo_s;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ref_clk;
assign adc_dwr_o = adc_valid;
assign adc_ddata_o = adc_data;
assign adc_clk_o = ctrl_data_clk;
assign adc_valid_c0 = ctrl_data_valid_i;
assign adc_valid_c1 = ctrl_data_valid_i;
assign adc_valid_c2 = ctrl_data_valid_i;
assign adc_valid_c3 = ctrl_data_valid_i;
assign adc_valid_c4 = ctrl_data_valid_i;
assign adc_valid_c5 = ctrl_data_valid_i;
assign adc_valid_c6 = ctrl_data_valid_i;
assign adc_valid_c7 = ctrl_data_valid_i;
assign adc_data_c0 = ctrl_data0_i;
assign adc_data_c1 = ctrl_data1_i;
assign adc_data_c2 = ctrl_data2_i;
assign adc_data_c3 = ctrl_data3_i;
assign adc_data_c4 = ctrl_data4_i;
assign adc_data_c5 = ctrl_data5_i;
assign adc_data_c6 = ctrl_data6_i;
assign adc_data_c7 = ctrl_data7_i;
assign ctrl_rst_o = !run_s;
// monitor signals
assign adc_mon_valid = adc_valid;
assign adc_mon_data = {25'h0 ,fmc_m1_en_o, pwm_ah_o, pwm_al_o, pwm_bh_o, pwm_bl_o, pwm_ch_o, pwm_cl_o};
assign fmc_m1_en_o = run_s;
assign pwm_s = oloop_matlab_s ? pwm_i[10:0] : pwm_open_s ;
assign pwm_s = pwm_open_s ;
assign pwm_ah_o = foc_ctrl_s ? !pwm_a_i : dpwm_ah_s;
assign pwm_al_o = foc_ctrl_s ? pwm_a_i : dpwm_al_s;
assign pwm_bh_o = foc_ctrl_s ? !pwm_b_i : dpwm_bh_s;
assign pwm_bl_o = foc_ctrl_s ? pwm_b_i : dpwm_bl_s;
assign pwm_ch_o = foc_ctrl_s ? !pwm_c_i : dpwm_ch_s;
assign pwm_cl_o = foc_ctrl_s ? pwm_c_i : dpwm_cl_s;
// assign gpo
@ -194,57 +254,6 @@ begin
pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk
end
// adc channels - dma interface
always @(posedge ref_clk)
begin
if(new_speed_i == 1)
begin
case({enable_actual_speed_s , enable_ref_speed_s})
2'b11:
begin
adc_data <= {speed_rpm_i[31:16], ref_speed_o[15:0]};
adc_valid <= 1'b1;
end
2'b01:
begin
adc_data <= { adc_data[15:0], ref_speed_o[15:0]};
one_chan_reg <= ~one_chan_reg;
if(one_chan_reg == 1'b1)
begin
adc_valid <= 1'b1;
end
else
begin
adc_valid <= 1'b0;
end
end
2'b10:
begin
adc_data <= { adc_data[15:0], speed_rpm_i[31:16]};
one_chan_reg <= ~one_chan_reg;
if(one_chan_reg == 1'b1)
begin
adc_valid <= 1'b1;
end
else
begin
adc_valid <= 1'b0;
end
end
2'b00:
begin
adc_data <= 32'hdeadbeef;
adc_valid <= 1'b1;
end
endcase
end
else
begin
adc_data <= adc_data;
adc_valid <= 1'b0;
end
end
// processor read interface
@ -253,8 +262,8 @@ always @(negedge up_rstn or posedge up_clk) begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_rdata <= up_control_rdata_s | up_adc_common_rdata_s | rdata_ref_speed_s | rdata_actual_speed_s ;
up_ack <= up_control_ack_s | up_adc_common_ack_s | ack_ref_speed_s | ack_actual_speed_s;
up_rdata <= up_control_rdata_s | up_adc_common_rdata_s | rdata_c0_s | rdata_c1_s | rdata_c2_s | rdata_c3_s | rdata_c4_s | rdata_c5_s | rdata_c6_s | rdata_c7_s;
up_ack <= up_control_ack_s | up_adc_common_ack_s | ack_c0_s | ack_c1_s | ack_c2_s | ack_c3_s | ack_c4_s | ack_c5_s | ack_c6_s | ack_c7_s;
end
end
@ -271,12 +280,12 @@ motor_driver_inst(
.dir_i(dir_s),
.position_i(position_i),
.pwm_duty_i(pwm_s),
.AH_o(pwm_ah_o),
.BH_o(pwm_bh_o),
.CH_o(pwm_ch_o),
.AL_o(pwm_al_o),
.BL_o(pwm_bl_o),
.CL_o(pwm_cl_o));
.AH_o(dpwm_ah_s),
.BH_o(dpwm_bh_s),
.CH_o(dpwm_ch_s),
.AL_o(dpwm_al_s),
.BL_o(dpwm_bl_s),
.CL_o(dpwm_cl_s));
control_registers control_reg_inst(
.up_rstn(up_rstn),
@ -301,15 +310,15 @@ control_registers control_reg_inst(
.kd1_o(),
.gpo_o(gpo_s),
.reference_speed_o(ref_speed_o),
.oloop_matlab_o(oloop_matlab_s),
.oloop_matlab_o(foc_ctrl_s),
.err_i(err_i),
.calibrate_adcs_o(),
.pwm_open_o( pwm_open_s));
up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel_ref_speed(
up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(enable_ref_speed_s),
.adc_enable(adc_enable_c0),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
@ -345,13 +354,13 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel_ref_speed(
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_ref_speed_s),
.up_ack(ack_ref_speed_s));
.up_rdata(rdata_c0_s),
.up_ack(ack_c0_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel_actual_speed(
up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(enable_actual_speed_s),
.adc_enable(adc_enable_c1),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
@ -387,9 +396,261 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel_actual_speed(
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_actual_speed_s),
.up_ack(ack_actual_speed_s));
.up_rdata(rdata_c1_s),
.up_ack(ack_c1_s));
up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c2),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c2_s),
.up_ack(ack_c2_s));
up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c3),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c3_s),
.up_ack(ack_c3_s));
up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c4),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c4_s),
.up_ack(ack_c4_s));
up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c5),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c5_s),
.up_ack(ack_c5_s));
up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c6),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c6_s),
.up_ack(ack_c6_s));
up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c7),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c7_s),
.up_ack(ack_c7_s));
// common processor control
up_adc_common i_up_adc_common(

12
library/axi_mc_current_monitor/axi_mc_current_monitor.v
View File

@ -58,9 +58,9 @@ module axi_mc_current_monitor
input ref_clk,
output [15:0] ia_o,
output [15:0] ib_o,
output [15:0] it_o,
output [17:0] ia_o,
output [17:0] ib_o,
output [17:0] it_o,
output i_ready_o,
// dma interface
@ -193,9 +193,9 @@ assign adc_mon_data[31:16] = {adc_enable_vbus, adc_enable_it, adc_enable_ib, ad
// current outputs
assign i_ready_o = data_rd_ready_ia_s;
assign ia_o = adc_data_ia_s;
assign ib_o = adc_data_ib_s;
assign it_o = adc_data_it_n_s;
assign ia_o = {adc_data_ia_s - 16'h7FFF, 2'b00};
assign ib_o = {adc_data_ib_s - 16'h7FFF, 2'b00};
assign it_o = {adc_data_it_s, 2'b00};
assign adc_data_it_n_s = 65535 - adc_data_it_s;
// adc clock

112
library/controllerperipheralhdladi_pcore/Chart.v Normal file
View File

@ -0,0 +1,112 @@
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Chart.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Chart
// Source Path: controllerPeripheralHdlAdi/PWM/Chart
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Chart
(
CLK_IN,
reset,
enb,
CounterMax,
count
);
input CLK_IN;
input reset;
input enb;
input [15:0] CounterMax; // uint16
output [15:0] count; // uint16
parameter IN_COUNT_Down = 0, IN_COUNT_UP = 1;
reg [1:0] is_libPwmCompareToPinsHdl_c1_Chart; // uint8
reg [15:0] count_reg; // uint16
reg [1:0] is_libPwmCompareToPinsHdl_c1_Chart_next; // enumerated type (2 enums)
reg [15:0] count_reg_next; // uint16
reg [16:0] add_temp_1; // ufix17
reg signed [16:0] sub_temp_1; // sfix17
always @(posedge CLK_IN)
begin : libPwmCompareToPinsHdl_c1_Chart_process
if (reset == 1'b1) begin
//Entry: PWM_HDL/Chart
//Entry Internal: PWM_HDL/Chart
//Transition: '<S13>:5'
count_reg <= 16'd0;
is_libPwmCompareToPinsHdl_c1_Chart <= IN_COUNT_UP;
end
else if (enb) begin
is_libPwmCompareToPinsHdl_c1_Chart <= is_libPwmCompareToPinsHdl_c1_Chart_next;
count_reg <= count_reg_next;
end
end
always @(is_libPwmCompareToPinsHdl_c1_Chart, CounterMax, count_reg) begin
is_libPwmCompareToPinsHdl_c1_Chart_next = is_libPwmCompareToPinsHdl_c1_Chart;
count_reg_next = count_reg;
//Gateway: PWM_HDL/Chart
//During: PWM_HDL/Chart
case ( is_libPwmCompareToPinsHdl_c1_Chart)
IN_COUNT_Down :
begin
//During 'COUNT_Down': '<S13>:2'
if (count_reg <= 16'b0000000000000000) begin
//Transition: '<S13>:4'
is_libPwmCompareToPinsHdl_c1_Chart_next = IN_COUNT_UP;
end
else begin
sub_temp_1 = $signed({1'b0, count_reg}) - 1;
if (sub_temp_1[16] == 1'b1) begin
count_reg_next = 16'b0000000000000000;
end
else begin
count_reg_next = sub_temp_1[15:0];
end
end
end
default :
begin
//During 'COUNT_UP': '<S13>:1'
if (count_reg >= CounterMax) begin
//Transition: '<S13>:3'
is_libPwmCompareToPinsHdl_c1_Chart_next = IN_COUNT_Down;
end
else begin
add_temp_1 = count_reg + 1;
if (add_temp_1[16] != 1'b0) begin
count_reg_next = 16'b1111111111111111;
end
else begin
count_reg_next = add_temp_1[15:0];
end
end
end
endcase
end
assign count = count_reg_next;
endmodule // Chart

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Count_Up_Down.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Count_Up_Down
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_A/Count_Up_Down
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Count_Up_Down
(
CLK_IN,
reset,
enb,
u,
count_debounce,
y
);
input CLK_IN;
input reset;
input enb;
input u;
input [7:0] count_debounce; // uint8
output y;
reg u_n1;
reg [7:0] count; // uint8
reg y_reg;
reg u_n1_next;
reg [7:0] count_next; // uint8
reg y_reg_next;
reg [8:0] add_temp_1; // ufix9
always @(posedge CLK_IN)
begin : libDebounce_c2_Count_Up_Down_process
if (reset == 1'b1) begin
u_n1 <= 1'b0;
count <= 8'd0;
y_reg <= 1'b0;
end
else if (enb) begin
u_n1 <= u_n1_next;
count <= count_next;
y_reg <= y_reg_next;
end
end
always @(u, u_n1, count, count_debounce, y_reg) begin
count_next = count;
y_reg_next = y_reg;
//Gateway: Debounce/Count_Up_Down
//During: Debounce/Count_Up_Down
//Entry Internal: Debounce/Count_Up_Down
//Transition: '<S10>:27'
if (u == u_n1) begin
//Transition: '<S10>:4'
//Transition: '<S10>:6'
if (count >= count_debounce) begin
//Transition: '<S10>:8'
//Transition: '<S10>:10'
y_reg_next = u;
//Transition: '<S10>:16'
end
else begin
//Transition: '<S10>:12'
add_temp_1 = count + 1;
if (add_temp_1[8] != 1'b0) begin
count_next = 8'b11111111;
end
else begin
count_next = add_temp_1[7:0];
end
end
//Transition: '<S10>:15'
end
else begin
//Transition: '<S10>:14'
count_next = 8'd0;
end
//Transition: '<S10>:18'
u_n1_next = u;
end
assign y = y_reg_next;
endmodule // Count_Up_Down

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Debounce_A.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Debounce_A
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_A
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Debounce_A
(
CLK_IN,
reset,
enb,
In,
Out
);
input CLK_IN;
input reset;
input enb;
input In;
output Out;
wire [7:0] Debouce_Count_out1; // uint8
wire Count_Up_Down_out1;
// <S3>/Debouce_Count
assign Debouce_Count_out1 = 8'd20;
// <S3>/Count_Up_Down
Count_Up_Down u_Count_Up_Down (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.u(In),
.count_debounce(Debouce_Count_out1), // uint8
.y(Count_Up_Down_out1)
);
assign Out = Count_Up_Down_out1;
endmodule // Debounce_A

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Debounce_B.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Debounce_B
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_B
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Debounce_B
(
CLK_IN,
reset,
enb,
In,
Out
);
input CLK_IN;
input reset;
input enb;
input In;
output Out;
wire [7:0] Debouce_Count_out1; // uint8
wire Count_Up_Down_out1;
// <S4>/Debouce_Count
assign Debouce_Count_out1 = 8'd20;
// <S4>/Count_Up_Down
Count_Up_Down u_Count_Up_Down (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.u(In),
.count_debounce(Debouce_Count_out1), // uint8
.y(Count_Up_Down_out1)
);
assign Out = Count_Up_Down_out1;
endmodule // Debounce_B

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Debounce_Index.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Debounce_Index
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_Index
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Debounce_Index
(
CLK_IN,
reset,
enb,
In,
Out
);
input CLK_IN;
input reset;
input enb;
input In;
output Out;
wire [7:0] Debouce_Count_out1; // uint8
wire Count_Up_Down_out1;
// <S5>/Debouce_Count
assign Debouce_Count_out1 = 8'd20;
// <S5>/Count_Up_Down
Count_Up_Down u_Count_Up_Down (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.u(In),
.count_debounce(Debouce_Count_out1), // uint8
.y(Count_Up_Down_out1)
);
assign Out = Count_Up_Down_out1;
endmodule // Debounce_Index

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Detect_Change_To_One.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Detect_Change_To_One
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Detect Change To One
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Detect_Change_To_One
(
CLK_IN,
reset,
enb,
In1,
Out1
);
input CLK_IN;
input reset;
input enb;
input In1;
output Out1;
reg Unit_Delay_out1;
wire Unit_Delay_out1_1;
wire In1_1;
// <S6>/Unit Delay
always @(posedge CLK_IN)
begin : Unit_Delay_process
if (reset == 1'b1) begin
Unit_Delay_out1 <= 1'b0;
end
else if (enb) begin
Unit_Delay_out1 <= In1;
end
end
// <S6>/Logical Operator
assign Unit_Delay_out1_1 = ~ Unit_Delay_out1;
// <S6>/Logical Operator1
assign In1_1 = In1 & Unit_Delay_out1_1;
assign Out1 = In1_1;
endmodule // Detect_Change_To_One

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Encoder_Peripheral_Hardware_Specification.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Encoder_Peripheral_Hardware_Specification
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Encoder_Peripheral_Hardware_Specification
(
CLK_IN,
reset,
enb,
a,
b,
index,
valid,
count
);
input CLK_IN;
input reset;
input enb;
input a;
input b;
input index;
output valid;
output [15:0] count; // uint16
wire y;
wire Latch_Index_Pulse_out1;
wire Select_AB_Inputs_out1;
wire y_1;
wire y_2;
wire Select_AB_out1;
wire Select_AB_out2;
wire Detect_Change_To_One_out1;
wire signed [15:0] Counter_Max_out1; // int16
wire signed [15:0] Update_Count_From_AB_out1; // int16
wire [15:0] Data_Type_Conversion_out1; // uint16
// <S1>/Debounce_Index
Debounce_Index u_Debounce_Index (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.In(index),
.Out(y)
);
// <S1>/Latch_Index_Pulse
Latch_Index_Pulse u_Latch_Index_Pulse (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.In1(y),
.Out1(Latch_Index_Pulse_out1)
);
assign valid = Latch_Index_Pulse_out1;
// <S1>/Select_AB_Inputs
assign Select_AB_Inputs_out1 = 1'b0;
// <S1>/Debounce_A
Debounce_A u_Debounce_A (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.In(a),
.Out(y_1)
);
// <S1>/Debounce_B
Debounce_B u_Debounce_B (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.In(b),
.Out(y_2)
);
// <S1>/Select AB
Select_AB u_Select_AB (.in_select(Select_AB_Inputs_out1),
.in1(y_1),
.in2(y_2),
.A(Select_AB_out1),
.B(Select_AB_out2)
);
// <S1>/Detect Change To One
Detect_Change_To_One u_Detect_Change_To_One (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.In1(y),
.Out1(Detect_Change_To_One_out1)
);
// <S1>/Counter_Max
assign Counter_Max_out1 = 16'sd4999;
// <S1>/Update_Count_From_AB
Update_Count_From_AB u_Update_Count_From_AB (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.A(Select_AB_out1),
.B(Select_AB_out2),
.index(Detect_Change_To_One_out1),
.count_max(Counter_Max_out1), // int16
.count(Update_Count_From_AB_out1) // int16
);
// <S1>/Data Type Conversion
assign Data_Type_Conversion_out1 = Update_Count_From_AB_out1;
assign count = Data_Type_Conversion_out1;
endmodule // Encoder_Peripheral_Hardware_Specification

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Latch_Index_Pulse.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Latch_Index_Pulse
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Latch_Index_Pulse
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Latch_Index_Pulse
(
CLK_IN,
reset,
enb,
In1,
Out1
);
input CLK_IN;
input reset;
input enb;
input In1;
output Out1;
wire Constant1_out1;
wire Switch_out1;
reg Delay_out1;
// <S7>/Constant1
assign Constant1_out1 = 1'b1;
// <S7>/Delay
always @(posedge CLK_IN)
begin : Delay_process
if (reset == 1'b1) begin
Delay_out1 <= 1'b0;
end
else if (enb) begin
Delay_out1 <= Switch_out1;
end
end
// <S7>/Switch
assign Switch_out1 = (Delay_out1 == 1'b0 ? In1 :
Constant1_out1);
assign Out1 = Switch_out1;
endmodule // Latch_Index_Pulse

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\PWM.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: PWM
// Source Path: controllerPeripheralHdlAdi/PWM
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module PWM
(
CLK_IN,
reset,
enb,
c_0,
c_1,
c_2,
pwm_0,
pwm_1,
pwm_2
);
input CLK_IN;
input reset;
input enb;
input [15:0] c_0; // uint16
input [15:0] c_1; // uint16
input [15:0] c_2; // uint16
output pwm_0; // boolean
output pwm_1; // boolean
output pwm_2; // boolean
wire [15:0] Timer_Period_Clock_Cycles_out1; // uint16
wire [15:0] Chart_out1; // uint16
wire [15:0] c [0:2]; // uint16 [3]
wire [15:0] Add_out1 [0:2]; // uint16 [3]
wire [15:0] Add_out1_0; // uint16
wire Relational_Operator_relop1;
wire [15:0] Add_out1_1; // uint16
wire Relational_Operator_relop2;
wire [15:0] Add_out1_2; // uint16
wire Relational_Operator_relop3;
wire [0:2] Relational_Operator_out1; // boolean [3]
wire Relational_Operator_out1_0;
wire [0:2] Compare_To_Zero_out1; // boolean [3]
wire Compare_To_Zero_out1_0;
wire Relational_Operator_out1_0_1;
wire Relational_Operator_out1_1;
wire Compare_To_Zero_out1_1;
wire Relational_Operator_out1_1_1;
wire Relational_Operator_out1_2;
wire Compare_To_Zero_out1_2;
wire Relational_Operator_out1_2_1;
// <S2>/Timer Period Clock Cycles
assign Timer_Period_Clock_Cycles_out1 = 16'd1000;
// <S2>/Chart
Chart u_Chart (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.CounterMax(Timer_Period_Clock_Cycles_out1), // uint16
.count(Chart_out1) // uint16
);
assign c[0] = c_0;
assign c[1] = c_1;
assign c[2] = c_2;
// <S2>/Add
assign Add_out1[0] = Timer_Period_Clock_Cycles_out1 - c[0];
assign Add_out1[1] = Timer_Period_Clock_Cycles_out1 - c[1];
assign Add_out1[2] = Timer_Period_Clock_Cycles_out1 - c[2];
assign Add_out1_0 = Add_out1[0];
assign Relational_Operator_relop1 = (Chart_out1 >= Add_out1_0 ? 1'b1 :
1'b0);
assign Add_out1_1 = Add_out1[1];
assign Relational_Operator_relop2 = (Chart_out1 >= Add_out1_1 ? 1'b1 :
1'b0);
assign Add_out1_2 = Add_out1[2];
// <S2>/Relational Operator
assign Relational_Operator_relop3 = (Chart_out1 >= Add_out1_2 ? 1'b1 :
1'b0);
assign Relational_Operator_out1[0] = Relational_Operator_relop1;
assign Relational_Operator_out1[1] = Relational_Operator_relop2;
assign Relational_Operator_out1[2] = Relational_Operator_relop3;
assign Relational_Operator_out1_0 = Relational_Operator_out1[0];
// <S2>/Compare To Zero
assign Compare_To_Zero_out1[0] = (c[0] != 16'b0000000000000000 ? 1'b1 :
1'b0);
assign Compare_To_Zero_out1[1] = (c[1] != 16'b0000000000000000 ? 1'b1 :
1'b0);
assign Compare_To_Zero_out1[2] = (c[2] != 16'b0000000000000000 ? 1'b1 :
1'b0);
assign Compare_To_Zero_out1_0 = Compare_To_Zero_out1[0];
assign Relational_Operator_out1_0_1 = Relational_Operator_out1_0 & Compare_To_Zero_out1_0;
assign pwm_0 = Relational_Operator_out1_0_1;
assign Relational_Operator_out1_1 = Relational_Operator_out1[1];
assign Compare_To_Zero_out1_1 = Compare_To_Zero_out1[1];
assign Relational_Operator_out1_1_1 = Relational_Operator_out1_1 & Compare_To_Zero_out1_1;
assign pwm_1 = Relational_Operator_out1_1_1;
assign Relational_Operator_out1_2 = Relational_Operator_out1[2];
assign Compare_To_Zero_out1_2 = Compare_To_Zero_out1[2];
// <S2>/Logical Operator
assign Relational_Operator_out1_2_1 = Relational_Operator_out1_2 & Compare_To_Zero_out1_2;
assign pwm_2 = Relational_Operator_out1_2_1;
endmodule // PWM

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Select_AB.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Select_AB
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Select AB
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Select_AB
(
in_select,
in1,
in2,
A,
B
);
input in_select;
input in1;
input in2;
output A;
output B;
wire Switch_out1;
wire Switch1_out1;
// <S8>/Switch
assign Switch_out1 = (in_select == 1'b0 ? in2 :
in1);
assign A = Switch_out1;
// <S8>/Switch1
assign Switch1_out1 = (in_select == 1'b0 ? in1 :
in2);
assign B = Switch1_out1;
endmodule // Select_AB

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Update_Count_From_AB.v
// Created: 2014-08-28 10:13:58
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Update_Count_From_AB
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Update_Count_From_AB
(
CLK_IN,
reset,
enb,
A,
B,
index,
count_max,
count
);
input CLK_IN;
input reset;
input enb;
input A;
input B;
input index;
input signed [15:0] count_max; // int16
output signed [15:0] count; // int16
parameter IN_NO_ACTIVE_CHILD = 0, IN_A0_B0 = 1, IN_A0_B1 = 2, IN_A1_B0 = 3, IN_A1_B1 = 4;
parameter IN_INDEX = 0, IN_INIT = 1;
reg [1:0] is_libEncoderPeripheralHdl_c7_Update_Count_From_AB; // uint8
reg [2:0] is_INDEX; // uint8
reg signed [15:0] count_reg; // int16
reg [1:0] is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next; // enumerated type (2 enums)
reg [2:0] is_INDEX_next; // enumerated type (5 enums)
reg signed [15:0] count_reg_next; // int16
always @(posedge CLK_IN)
begin : libEncoderPeripheralHdl_c7_Update_Count_From_AB_process
if (reset == 1'b1) begin
is_INDEX <= IN_NO_ACTIVE_CHILD;
count_reg <= 16'sd0;
//Entry: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB
//Entry Internal: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB
//Transition: '<S9>:30'
is_libEncoderPeripheralHdl_c7_Update_Count_From_AB <= IN_INIT;
end
else if (enb) begin
is_libEncoderPeripheralHdl_c7_Update_Count_From_AB <= is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next;
is_INDEX <= is_INDEX_next;
count_reg <= count_reg_next;
end
end
always @(is_libEncoderPeripheralHdl_c7_Update_Count_From_AB, is_INDEX, A, B, index,
count_max, count_reg) begin
count_reg_next = count_reg;
is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next = is_libEncoderPeripheralHdl_c7_Update_Count_From_AB;
is_INDEX_next = is_INDEX;
//Gateway: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB
//During: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB
case ( is_libEncoderPeripheralHdl_c7_Update_Count_From_AB)
IN_INDEX :
begin
//During 'INDEX': '<S9>:29'
if (index == 1'b1) begin
//Transition: '<S9>:34'
//Transition: '<S9>:35'
count_reg_next = 16'sd0;
//Transition: '<S9>:37'
//Exit Internal 'INDEX': '<S9>:29'
is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next = IN_INDEX;
is_INDEX_next = IN_A0_B0;
end
else begin
case ( is_INDEX)
IN_A0_B0 :
begin
//During 'A0_B0': '<S9>:1'
if (A && ( ~ B)) begin
//Transition: '<S9>:14'
//Graphical Function 'incrementCount': '<S9>:42'
//Transition: '<S9>:44'
count_reg_next = count_reg + 1;
if ((count_reg + 16'sd1) > count_max) begin
//Transition: '<S9>:46'
//Transition: '<S9>:48'
count_reg_next = 16'sd0;
//Transition: '<S9>:51'
end
else begin
//Transition: '<S9>:50'
end
//Transition: '<S9>:13'
is_INDEX_next = IN_A1_B0;
end
else if (( ~ A) && B) begin
//Transition: '<S9>:8'
//Graphical Function 'decrementCount': '<S9>:55'
//Transition: '<S9>:60'
count_reg_next = count_reg - 1;
if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin
//Transition: '<S9>:61'
//Transition: '<S9>:63'
count_reg_next = count_max;
//Transition: '<S9>:64'
end
else begin
//Transition: '<S9>:62'
end
is_INDEX_next = IN_A0_B1;
end
end
IN_A0_B1 :
begin
//During 'A0_B1': '<S9>:5'
if (A && B) begin
//Transition: '<S9>:10'
//Graphical Function 'decrementCount': '<S9>:55'
//Transition: '<S9>:60'
count_reg_next = count_reg - 1;
if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin
//Transition: '<S9>:61'
//Transition: '<S9>:63'
count_reg_next = count_max;
//Transition: '<S9>:64'
end
else begin
//Transition: '<S9>:62'
end
is_INDEX_next = IN_A1_B1;
end
else begin
//Transition: '<S9>:16'
if (( ~ A) && ( ~ B)) begin
//Transition: '<S9>:17'
//Graphical Function 'incrementCount': '<S9>:42'
//Transition: '<S9>:44'
count_reg_next = count_reg + 1;
if ((count_reg + 16'sd1) > count_max) begin
//Transition: '<S9>:46'
//Transition: '<S9>:48'
count_reg_next = 16'sd0;
//Transition: '<S9>:51'
end
else begin
//Transition: '<S9>:50'
end
is_INDEX_next = IN_A0_B0;
end
end
end
IN_A1_B0 :
begin
//During 'A1_B0': '<S9>:2'
if (( ~ A) && ( ~ B)) begin
//Transition: '<S9>:7'
//Graphical Function 'decrementCount': '<S9>:55'
//Transition: '<S9>:60'
count_reg_next = count_reg - 1;
if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin
//Transition: '<S9>:61'
//Transition: '<S9>:63'
count_reg_next = count_max;
//Transition: '<S9>:64'
end
else begin
//Transition: '<S9>:62'
end
is_INDEX_next = IN_A0_B0;
end
else begin
//Transition: '<S9>:24'
if (A && B) begin
//Transition: '<S9>:25'
//Graphical Function 'incrementCount': '<S9>:42'
//Transition: '<S9>:44'
count_reg_next = count_reg + 1;
if ((count_reg + 16'sd1) > count_max) begin
//Transition: '<S9>:46'
//Transition: '<S9>:48'
count_reg_next = 16'sd0;
//Transition: '<S9>:51'
end
else begin
//Transition: '<S9>:50'
end
is_INDEX_next = IN_A1_B1;
end
end
end
default :
begin
//During 'A1_B1': '<S9>:4'
if (( ~ A) && B) begin
//Transition: '<S9>:19'
//Graphical Function 'incrementCount': '<S9>:42'
//Transition: '<S9>:44'
count_reg_next = count_reg + 1;
if ((count_reg + 16'sd1) > count_max) begin
//Transition: '<S9>:46'
//Transition: '<S9>:48'
count_reg_next = 16'sd0;
//Transition: '<S9>:51'
end
else begin
//Transition: '<S9>:50'
end
//Transition: '<S9>:21'
is_INDEX_next = IN_A0_B1;
end
else if (A && ( ~ B)) begin
//Transition: '<S9>:22'
//Graphical Function 'decrementCount': '<S9>:55'
//Transition: '<S9>:60'
count_reg_next = count_reg - 1;
if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin
//Transition: '<S9>:61'
//Transition: '<S9>:63'
count_reg_next = count_max;
//Transition: '<S9>:64'
end
else begin
//Transition: '<S9>:62'
end
is_INDEX_next = IN_A1_B0;
end
end
endcase
end
end
default :
begin
//During 'INIT': '<S9>:68'
//Transition: '<S9>:70'
//Transition: '<S9>:35'
count_reg_next = 16'sd0;
//Transition: '<S9>:37'
is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next = IN_INDEX;
is_INDEX_next = IN_A0_B0;
end
endcase
end
assign count = count_reg_next;
endmodule // Update_Count_From_AB

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_ADC_Peripheral_To_Phase_Current.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_ADC_Peripheral_To_Phase_Current
// Source Path: controllerHdl/ADC_Peripheral_To_Phase_Current
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_ADC_Peripheral_To_Phase_Current
(
adc_0,
adc_1,
phase_currents_0,
phase_currents_1
);
input signed [17:0] adc_0; // sfix18_En17
input signed [17:0] adc_1; // sfix18_En17
output signed [17:0] phase_currents_0; // sfix18_En15
output signed [17:0] phase_currents_1; // sfix18_En15
wire signed [17:0] adc [0:1]; // sfix18_En17 [2]
wire signed [17:0] ADC_Zero_Offset_out1; // sfix18_En16
wire signed [19:0] Add_v; // sfix20_En17
wire signed [19:0] Add_sub_cast; // sfix20_En17
wire signed [19:0] Add_sub_cast_1; // sfix20_En17
wire signed [19:0] Add_out1 [0:1]; // sfix20_En17 [2]
wire signed [17:0] ADC_Amps_Per_Driver_Unit_out1; // sfix18_En15
wire signed [37:0] Product_mul_temp; // sfix38_En32
wire signed [37:0] Product_mul_temp_1; // sfix38_En32
wire signed [17:0] phase_currents [0:1]; // sfix18_En15 [2]
assign adc[0] = adc_0;
assign adc[1] = adc_1;
// <S1>/ADC_Zero_Offset
assign ADC_Zero_Offset_out1 = 18'sb000000000000000000;
// <S1>/Add
assign Add_v = {ADC_Zero_Offset_out1[17], {ADC_Zero_Offset_out1, 1'b0}};
assign Add_sub_cast = adc[0];
assign Add_out1[0] = Add_sub_cast - Add_v;
assign Add_sub_cast_1 = adc[1];
assign Add_out1[1] = Add_sub_cast_1 - Add_v;
// <S1>/ADC_Amps_Per_Driver_Unit
assign ADC_Amps_Per_Driver_Unit_out1 = 18'sb010100000000000000;
// <S1>/Product
assign Product_mul_temp = Add_out1[0] * ADC_Amps_Per_Driver_Unit_out1;
assign phase_currents[0] = ((Product_mul_temp[37] == 1'b0) && (Product_mul_temp[36:34] != 3'b000) ? 18'sb011111111111111111 :
((Product_mul_temp[37] == 1'b1) && (Product_mul_temp[36:34] != 3'b111) ? 18'sb100000000000000000 :
$signed(Product_mul_temp[34:17])));
assign Product_mul_temp_1 = Add_out1[1] * ADC_Amps_Per_Driver_Unit_out1;
assign phase_currents[1] = ((Product_mul_temp_1[37] == 1'b0) && (Product_mul_temp_1[36:34] != 3'b000) ? 18'sb011111111111111111 :
((Product_mul_temp_1[37] == 1'b1) && (Product_mul_temp_1[36:34] != 3'b111) ? 18'sb100000000000000000 :
$signed(Product_mul_temp_1[34:17])));
assign phase_currents_0 = phase_currents[0];
assign phase_currents_1 = phase_currents[1];
endmodule // controllerHdl_ADC_Peripheral_To_Phase_Current

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Calculate_Rotor_Velocity.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Calculate_Rotor_Velocity
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Calculate_Rotor_Velocity
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Calculate_Rotor_Velocity
(
CLK_IN,
reset,
enb_1_2000_0,
valid,
position,
rotor_velocity
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input valid;
input signed [17:0] position; // sfix18_En14
output signed [17:0] rotor_velocity; // sfix18_En8
wire Constant_out1;
reg Delay3_out1;
reg [0:1] Delay2_reg; // ufix1 [2]
wire [0:1] Delay2_reg_next; // ufix1 [2]
wire Delay2_out1;
wire Detect_Rise_relop1;
wire Detect_Rise_out1;
wire Delay2_out1_1;
wire update_velocity;
reg signed [17:0] Delay1_out1; // sfix18_En14
wire signed [18:0] Add_sub_cast; // sfix19_En14
wire signed [18:0] Add_sub_cast_1; // sfix19_En14
wire signed [18:0] Add_out1; // sfix19_En14
wire signed [17:0] position_delta; // sfix18_En15
wire [17:0] time_delta_1; // ufix18_En3
wire signed [18:0] Product_cast; // sfix19_En3
wire signed [36:0] Product_mul_temp; // sfix37_En18
wire signed [35:0] velocity; // sfix36_En18
wire signed [35:0] Switch_out1; // sfix36_En18
reg signed [35:0] Delay_out1; // sfix36_En18
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En8
// First two velocity calculations are not valid
//
// If detect positive rise in valid, this is a bad sample
// since encoder index just reset. In this case hold the last value
//
// Calculate Velocity
// <S6>/Constant
assign Constant_out1 = 1'b1;
// <S6>/Delay3
always @(posedge CLK_IN)
begin : Delay3_process
if (reset == 1'b1) begin
Delay3_out1 <= 1'b0;
end
else if (enb_1_2000_0) begin
Delay3_out1 <= valid;
end
end
// <S6>/Delay2
always @(posedge CLK_IN)
begin : Delay2_process
if (reset == 1'b1) begin
Delay2_reg[0] <= 1'b0;
Delay2_reg[1] <= 1'b0;
end
else if (enb_1_2000_0) begin
Delay2_reg[0] <= Delay2_reg_next[0];
Delay2_reg[1] <= Delay2_reg_next[1];
end
end
assign Delay2_out1 = Delay2_reg[1];
assign Delay2_reg_next[0] = Constant_out1;
assign Delay2_reg_next[1] = Delay2_reg[0];
// <S6>/Detect_Rise
assign Detect_Rise_relop1 = (valid > Delay3_out1 ? 1'b1 :
1'b0);
// <S6>/No_Rise_Detected
assign Detect_Rise_out1 = ~ Detect_Rise_relop1;
// <S6>/Logical Operator
assign Delay2_out1_1 = Delay2_out1 & Detect_Rise_out1;
assign update_velocity = Delay2_out1_1;
// <S6>/Delay1
always @(posedge CLK_IN)
begin : Delay1_process
if (reset == 1'b1) begin
Delay1_out1 <= 18'sb000000000000000000;
end
else if (enb_1_2000_0) begin
Delay1_out1 <= position;
end
end
// <S6>/Add
assign Add_sub_cast = position;
assign Add_sub_cast_1 = Delay1_out1;
assign Add_out1 = Add_sub_cast - Add_sub_cast_1;
// <S6>/Wrap_NegPi_To_Pi
controllerHdl_Wrap_NegPi_To_Pi u_Wrap_NegPi_To_Pi (.position(Add_out1), // sfix19_En14
.wrap(position_delta) // sfix18_En15
);
// <S6>/Time_Delta
assign time_delta_1 = 18'b110000110101000000;
// <S6>/Product
assign Product_cast = time_delta_1;
assign Product_mul_temp = position_delta * Product_cast;
assign velocity = Product_mul_temp[35:0];
// <S6>/Delay
always @(posedge CLK_IN)
begin : Delay_process
if (reset == 1'b1) begin
Delay_out1 <= 36'sh000000000;
end
else if (enb_1_2000_0) begin
Delay_out1 <= Switch_out1;
end
end
// <S6>/Switch
assign Switch_out1 = (update_velocity == 1'b0 ? Delay_out1 :
velocity);
// <S6>/Data Type Conversion
assign Data_Type_Conversion_out1 = Switch_out1[27:10];
assign rotor_velocity = Data_Type_Conversion_out1;
endmodule // controllerHdl_Calculate_Rotor_Velocity

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Complex_Multiply.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Complex_Multiply
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Complex_Multiply
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Complex_Multiply
(
In1_re,
In1_im,
In2_re,
In2_im,
Re,
Im
);
input signed [17:0] In1_re; // sfix18_En16
input signed [17:0] In1_im; // sfix18_En16
input signed [17:0] In2_re; // sfix18_En16
input signed [17:0] In2_im; // sfix18_En16
output signed [35:0] Re; // sfix36_En32
output signed [35:0] Im; // sfix36_En32
wire signed [35:0] Product_out1; // sfix36_En32
wire signed [35:0] Product1_out1; // sfix36_En32
wire signed [35:0] Add1_out1; // sfix36_En32
wire signed [35:0] Product2_out1; // sfix36_En32
wire signed [35:0] Product3_out1; // sfix36_En32
wire signed [35:0] Add2_out1; // sfix36_En32
// <S33>/Product
//
// <S33>/Complex to Real-Imag1
//
// <S33>/Complex to Real-Imag2
assign Product_out1 = In1_re * In2_re;
// <S33>/Product1
assign Product1_out1 = In1_im * In2_im;
// <S33>/Add1
assign Add1_out1 = Product_out1 - Product1_out1;
assign Re = Add1_out1;
// <S33>/Product2
assign Product2_out1 = In1_re * In2_im;
// <S33>/Product3
assign Product3_out1 = In1_im * In2_re;
// <S33>/Add2
assign Add2_out1 = Product2_out1 + Product3_out1;
assign Im = Add2_out1;
endmodule // controllerHdl_Complex_Multiply

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Convert_Data_Type.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Convert_Data_Type
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Frequency_To_Volts/Convert_Data_Type
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Convert_Data_Type
(
In1,
Out1
);
input signed [31:0] In1; // sfix32_En21
output signed [17:0] Out1; // sfix18_En7
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En7
// <S26>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[31:14];
assign Out1 = Data_Type_Conversion_out1;
endmodule // controllerHdl_Convert_Data_Type

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Convert_Data_Type1.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Convert_Data_Type1
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Park_Transform/Convert_Data_Type1
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Convert_Data_Type1
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En28
output signed [17:0] Out1; // sfix18_En10
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En10
// <S42>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[35:18];
assign Out1 = Data_Type_Conversion_out1;
endmodule // controllerHdl_Convert_Data_Type1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Convert_Data_Type_block.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Convert_Data_Type_block
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_To_Electical_Velocity/Convert_Data_Type
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Convert_Data_Type_block
(
In1,
Out1
);
input signed [31:0] In1; // sfix32_En22
output signed [17:0] Out1; // sfix18_En8
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En8
// <S32>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[31:14];
assign Out1 = Data_Type_Conversion_out1;
endmodule // controllerHdl_Convert_Data_Type_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Convert_Data_Type_block1.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Convert_Data_Type_block1
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Convert_Data_Type
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Convert_Data_Type_block1
(
In1,
Out1
);
input signed [17:0] In1; // sfix18_En14
output signed [17:0] Out1; // sfix18_En14
// <S34>/Data Type Conversion
assign Out1 = In1;
endmodule // controllerHdl_Convert_Data_Type_block1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Convert_Data_Type_block2.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Convert_Data_Type_block2
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Park_Transform/Convert_Data_Type
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Convert_Data_Type_block2
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En28
output signed [17:0] Out1; // sfix18_En10
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En10
// <S41>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[35:18];
assign Out1 = Data_Type_Conversion_out1;
endmodule // controllerHdl_Convert_Data_Type_block2

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Detect_Change.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Detect_Change
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity/Set_Acceleration/Detect_Change
// Hierarchy Level: 7
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Detect_Change
(
CLK_IN,
reset,
enb_1_2000_0,
x,
y
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input signed [17:0] x; // sfix18_En8
output y;
reg signed [17:0] Delay_out1; // sfix18_En8
wire signed [18:0] Add_sub_cast; // sfix19_En8
wire signed [18:0] Add_sub_cast_1; // sfix19_En8
wire signed [18:0] Add_out1; // sfix19_En8
wire Compare_To_Zero2_out1;
// <S30>/Delay
always @(posedge CLK_IN)
begin : Delay_process
if (reset == 1'b1) begin
Delay_out1 <= 18'sb000000000000000000;
end
else if (enb_1_2000_0) begin
Delay_out1 <= x;
end
end
// <S30>/Add
assign Add_sub_cast = x;
assign Add_sub_cast_1 = Delay_out1;
assign Add_out1 = Add_sub_cast - Add_sub_cast_1;
// <S30>/Compare To Zero2
assign Compare_To_Zero2_out1 = (Add_out1 != 19'sb0000000000000000000 ? 1'b1 :
1'b0);
assign y = Compare_To_Zero2_out1;
endmodule // controllerHdl_Detect_Change

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Double_Range.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Double_Range
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Frequency_To_Volts/Double_Range
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Double_Range
(
In1,
Out1
);
input signed [31:0] In1; // sfix32_En22
output signed [31:0] Out1; // sfix32_En21
wire signed [31:0] Data_Type_Conversion_out1; // sfix32_En21
// <S27>/Data Type Conversion
assign Data_Type_Conversion_out1 = {In1[31], In1[31:1]};
assign Out1 = Data_Type_Conversion_out1;
endmodule // controllerHdl_Double_Range

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Electrical_Velocity_To_Position.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Electrical_Velocity_To_Position
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Electrical_Velocity_To_Position
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Electrical_Velocity_To_Position
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
EV,
EP
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [17:0] EV; // sfix18_En6
output signed [17:0] EP; // sfix18_En14
wire signed [35:0] Gain_out1; // sfix36_En37
wire signed [31:0] Data_Type_Conversion2_out1; // sfix32_En27
wire signed [31:0] Reset_Delay_out1; // sfix32_En27
wire signed [31:0] Add3_out1; // sfix32_En27
wire signed [31:0] Wrap_2pi_Once_out1; // sfix32_En27
wire signed [17:0] Data_Type_Conversion1_out1; // sfix18_En14
// Electrical Velocity To Position
// <S20>/Gain
assign Gain_out1 = 85899 * EV;
// <S20>/Data Type Conversion2
assign Data_Type_Conversion2_out1 = {{6{Gain_out1[35]}}, Gain_out1[35:10]};
// <S20>/Add3
assign Add3_out1 = Data_Type_Conversion2_out1 + Reset_Delay_out1;
// <S20>/Wrap_2pi_Once
controllerHdl_Wrap_2pi_Once u_Wrap_2pi_Once (.x(Add3_out1), // sfix32_En27
.wrap(Wrap_2pi_Once_out1) // sfix32_En27
);
// <S20>/Reset_Delay
controllerHdl_Reset_Delay u_Reset_Delay (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reset_1),
.In(Wrap_2pi_Once_out1), // sfix32_En27
.Out(Reset_Delay_out1) // sfix32_En27
);
// <S20>/Data Type Conversion1
assign Data_Type_Conversion1_out1 = Reset_Delay_out1[30:13];
assign EP = Data_Type_Conversion1_out1;
endmodule // controllerHdl_Electrical_Velocity_To_Position

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Encoder_To_Position_And_Velocity.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Encoder_To_Position_And_Velocity
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Encoder_To_Position_And_Velocity
(
CLK_IN,
reset,
enb_1_2000_0,
encoder_valid,
encoder_counter,
param_zero_offset,
position_valid,
rotor_position,
electrical_position,
rotor_velocity
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input encoder_valid;
input [15:0] encoder_counter; // uint16
input signed [17:0] param_zero_offset; // sfix18_En14
output position_valid;
output signed [17:0] rotor_position; // sfix18_En14
output signed [17:0] electrical_position; // sfix18_En14
output signed [17:0] rotor_velocity; // sfix18_En8
wire signed [17:0] Rotor_To_Electrical_Position_out1; // sfix18_En14
wire signed [17:0] Calculate_Rotor_Velocity_out1; // sfix18_En8
assign position_valid = encoder_valid;
// <S2>/Encoder_To_Rotor_Position
controllerHdl_Encoder_To_Rotor_Position u_Encoder_To_Rotor_Position (.counter(encoder_counter), // uint16
.param_zero_offset(param_zero_offset), // sfix18_En14
.position(rotor_position) // sfix18_En14
);
// <S2>/Rotor_To_Electrical_Position
controllerHdl_Rotor_To_Electrical_Position u_Rotor_To_Electrical_Position (.R(rotor_position), // sfix18_En14
.E(Rotor_To_Electrical_Position_out1) // sfix18_En14
);
assign electrical_position = Rotor_To_Electrical_Position_out1;
// <S2>/Calculate_Rotor_Velocity
controllerHdl_Calculate_Rotor_Velocity u_Calculate_Rotor_Velocity (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.valid(encoder_valid),
.position(rotor_position), // sfix18_En14
.rotor_velocity(Calculate_Rotor_Velocity_out1) // sfix18_En8
);
assign rotor_velocity = Calculate_Rotor_Velocity_out1;
endmodule // controllerHdl_Encoder_To_Position_And_Velocity

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Encoder_To_Rotor_Position.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Encoder_To_Rotor_Position
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Encoder_To_Rotor_Position
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Encoder_To_Rotor_Position
(
counter,
param_zero_offset,
position
);
input [15:0] counter; // uint16
input signed [17:0] param_zero_offset; // sfix18_En14
output signed [17:0] position; // sfix18_En14
wire [31:0] radians_per_counts_mul_temp; // ufix32_En25
wire signed [17:0] encoder_angle; // sfix18_En14
wire signed [18:0] Add_sub_cast; // sfix19_En14
wire signed [18:0] Add_sub_cast_1; // sfix19_En14
wire signed [18:0] Add_out1; // sfix19_En14
wire signed [17:0] rotor_position; // sfix18_En14
// Encoder to Rotor Position
//
// The encoder counts increase with positive rotation of the rotor.
// <S7>/radians_per_counts
assign radians_per_counts_mul_temp = 42166 * counter;
assign encoder_angle = $signed(radians_per_counts_mul_temp[28:11]);
// <S7>/Add
assign Add_sub_cast = encoder_angle;
assign Add_sub_cast_1 = param_zero_offset;
assign Add_out1 = Add_sub_cast - Add_sub_cast_1;
// <S7>/Wrap_2pi
controllerHdl_Wrap_2pi u_Wrap_2pi (.x(Add_out1), // sfix19_En14
.wrap(rotor_position) // sfix18_En14
);
assign position = rotor_position;
endmodule // controllerHdl_Encoder_To_Rotor_Position

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Field_Oriented_Control.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Field_Oriented_Control
// Source Path: controllerHdl/Field_Oriented_Control
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Field_Oriented_Control
(
CLK_IN,
reset,
enb_1_2000_0,
controller_mode,
command,
electrical_postion,
rotor_velocity,
phase_currents_0,
phase_currents_1,
param_velocity_p_gain,
param_velocity_i_gain,
param_current_p_gain,
param_current_i_gain,
param_open_loop_bias,
param_open_loop_scalar,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2,
dq_current_0,
dq_current_1,
electrical_position_ol
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input [1:0] controller_mode; // ufix2
input signed [17:0] command; // sfix18_En8
input signed [17:0] electrical_postion; // sfix18_En14
input signed [17:0] rotor_velocity; // sfix18_En8
input signed [17:0] phase_currents_0; // sfix18_En15
input signed [17:0] phase_currents_1; // sfix18_En15
input signed [17:0] param_velocity_p_gain; // sfix18_En16
input signed [17:0] param_velocity_i_gain; // sfix18_En15
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
input signed [17:0] param_open_loop_bias; // sfix18_En14
input signed [17:0] param_open_loop_scalar; // sfix18_En16
output signed [19:0] phase_voltages_0; // sfix20_En12
output signed [19:0] phase_voltages_1; // sfix20_En12
output signed [19:0] phase_voltages_2; // sfix20_En12
output signed [17:0] dq_current_0; // sfix18_En15
output signed [17:0] dq_current_1; // sfix18_En15
output signed [17:0] electrical_position_ol; // sfix18_En14
wire MATLAB_Function_out2;
wire signed [19:0] Velocity_Control_out1_0; // sfix20_En12
wire signed [19:0] Velocity_Control_out1_1; // sfix20_En12
wire signed [19:0] Velocity_Control_out1_2; // sfix20_En12
wire signed [17:0] Velocity_Control_out2_0; // sfix18_En15
wire signed [17:0] Velocity_Control_out2_1; // sfix18_En15
wire [1:0] MATLAB_Function_out1; // ufix2
wire signed [17:0] Open_Loop_Control_out1_0; // sfix18_En13
wire signed [17:0] Open_Loop_Control_out1_1; // sfix18_En13
wire signed [17:0] Open_Loop_Control_out1_2; // sfix18_En13
wire signed [17:0] Open_Loop_Control_out2; // sfix18_En14
wire signed [17:0] Open_Loop_Control_out1 [0:2]; // sfix18_En13 [3]
wire signed [19:0] Open_Loop_Control_out1_dtc [0:2]; // sfix20_En12 [3]
wire signed [19:0] Velocity_Control_out1 [0:2]; // sfix20_En12 [3]
wire signed [19:0] StandBy_out1_0; // sfix20_En12
wire signed [19:0] StandBy_out1_1; // sfix20_En12
wire signed [19:0] StandBy_out1_2; // sfix20_En12
wire signed [19:0] StandBy_out1 [0:2]; // sfix20_En12 [3]
wire signed [19:0] Multiport_Switch_out1 [0:2]; // sfix20_En12 [3]
// Field Oriented Control
// <S3>/MATLAB Function
controllerHdl_MATLAB_Function_block2 u_MATLAB_Function (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.cMode(controller_mode), // ufix2
.index(MATLAB_Function_out1), // ufix2
.reset_1(MATLAB_Function_out2)
);
// <S3>/Open_Loop_Control
controllerHdl_Open_Loop_Control u_Open_Loop_Control (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.reset_1(MATLAB_Function_out2),
.command_value(command), // sfix18_En8
.param_open_loop_bias(param_open_loop_bias), // sfix18_En14
.param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16
.phase_voltages_0(Open_Loop_Control_out1_0), // sfix18_En13
.phase_voltages_1(Open_Loop_Control_out1_1), // sfix18_En13
.phase_voltages_2(Open_Loop_Control_out1_2), // sfix18_En13
.electrical_position(Open_Loop_Control_out2) // sfix18_En14
);
assign Open_Loop_Control_out1[0] = Open_Loop_Control_out1_0;
assign Open_Loop_Control_out1[1] = Open_Loop_Control_out1_1;
assign Open_Loop_Control_out1[2] = Open_Loop_Control_out1_2;
assign Open_Loop_Control_out1_dtc[0] = {{3{Open_Loop_Control_out1[0][17]}}, Open_Loop_Control_out1[0][17:1]};
assign Open_Loop_Control_out1_dtc[1] = {{3{Open_Loop_Control_out1[1][17]}}, Open_Loop_Control_out1[1][17:1]};
assign Open_Loop_Control_out1_dtc[2] = {{3{Open_Loop_Control_out1[2][17]}}, Open_Loop_Control_out1[2][17:1]};
// <S3>/Velocity_Control
velocityControlHdl_velocityControlHdl u_Velocity_Control (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.reset_1(MATLAB_Function_out2),
.command(command), // sfix18_En8
.measured(rotor_velocity), // sfix18_En8
.phase_currents_0(phase_currents_0), // sfix18_En15
.phase_currents_1(phase_currents_1), // sfix18_En15
.electrical_position(electrical_postion), // sfix18_En14
.param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16
.param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15
.param_current_p_gain(param_current_p_gain), // sfix18_En10
.param_current_i_gain(param_current_i_gain), // sfix18_En2
.phase_voltages_0(Velocity_Control_out1_0), // sfix20_En12
.phase_voltages_1(Velocity_Control_out1_1), // sfix20_En12
.phase_voltages_2(Velocity_Control_out1_2), // sfix20_En12
.dq_currents_0(Velocity_Control_out2_0), // sfix18_En15
.dq_currents_1(Velocity_Control_out2_1) // sfix18_En15
);
assign Velocity_Control_out1[0] = Velocity_Control_out1_0;
assign Velocity_Control_out1[1] = Velocity_Control_out1_1;
assign Velocity_Control_out1[2] = Velocity_Control_out1_2;
// Stand By mode for controller outputs constant phase voltages.
//
// <S3>/StandBy
controllerHdl_StandBy u_StandBy (.Phase_Voltages_0(StandBy_out1_0), // sfix20_En12
.Phase_Voltages_1(StandBy_out1_1), // sfix20_En12
.Phase_Voltages_2(StandBy_out1_2) // sfix20_En12
);
assign StandBy_out1[0] = StandBy_out1_0;
assign StandBy_out1[1] = StandBy_out1_1;
assign StandBy_out1[2] = StandBy_out1_2;
// <S3>/Multiport Switch
assign Multiport_Switch_out1[0] = (MATLAB_Function_out1 == 2'b00 ? Open_Loop_Control_out1_dtc[0] :
(MATLAB_Function_out1 == 2'b01 ? Velocity_Control_out1[0] :
StandBy_out1[0]));
assign Multiport_Switch_out1[1] = (MATLAB_Function_out1 == 2'b00 ? Open_Loop_Control_out1_dtc[1] :
(MATLAB_Function_out1 == 2'b01 ? Velocity_Control_out1[1] :
StandBy_out1[1]));
assign Multiport_Switch_out1[2] = (MATLAB_Function_out1 == 2'b00 ? Open_Loop_Control_out1_dtc[2] :
(MATLAB_Function_out1 == 2'b01 ? Velocity_Control_out1[2] :
StandBy_out1[2]));
assign phase_voltages_0 = Multiport_Switch_out1[0];
assign phase_voltages_1 = Multiport_Switch_out1[1];
assign phase_voltages_2 = Multiport_Switch_out1[2];
assign dq_current_0 = Velocity_Control_out2_0;
assign dq_current_1 = Velocity_Control_out2_1;
assign electrical_position_ol = Open_Loop_Control_out2;
endmodule // controllerHdl_Field_Oriented_Control

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Frequency_To_Volts.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Frequency_To_Volts
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Frequency_To_Volts
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Frequency_To_Volts
(
F,
param_open_loop_bias,
param_open_loop_scalar,
V
);
input signed [31:0] F; // sfix32_En22
input signed [17:0] param_open_loop_bias; // sfix18_En14
input signed [17:0] param_open_loop_scalar; // sfix18_En16
output signed [17:0] V; // sfix18_En12
wire signed [31:0] Double_Range_out1; // sfix32_En21
wire signed [17:0] Convert_Data_Type_out1; // sfix18_En7
wire signed [18:0] Abs1_cast; // sfix19_En7
wire signed [18:0] Abs1_cast_1; // sfix19_En7
wire signed [17:0] Abs1_out1; // sfix18_En7
wire signed [35:0] freq_to_volts; // sfix36_En23
wire signed [36:0] Add_add_cast; // sfix37_En23
wire signed [36:0] Add_add_cast_1; // sfix37_En23
wire signed [36:0] volts; // sfix37_En23
wire signed [17:0] volts_dt; // sfix18_En12
// Frequency To Volts
// <S21>/Double_Range
controllerHdl_Double_Range u_Double_Range (.In1(F), // sfix32_En22
.Out1(Double_Range_out1) // sfix32_En21
);
// <S21>/Convert_Data_Type
controllerHdl_Convert_Data_Type u_Convert_Data_Type (.In1(Double_Range_out1), // sfix32_En21
.Out1(Convert_Data_Type_out1) // sfix18_En7
);
// <S21>/Abs1
assign Abs1_cast = Convert_Data_Type_out1;
assign Abs1_cast_1 = - (Abs1_cast);
assign Abs1_out1 = (Convert_Data_Type_out1 < 18'sb000000000000000000 ? $signed(Abs1_cast_1[17:0]) :
Convert_Data_Type_out1);
// <S21>/Product
assign freq_to_volts = Abs1_out1 * param_open_loop_scalar;
// <S21>/Add
assign Add_add_cast = freq_to_volts;
assign Add_add_cast_1 = {{10{param_open_loop_bias[17]}}, {param_open_loop_bias, 9'b000000000}};
assign volts = Add_add_cast + Add_add_cast_1;
// <S21>/Voltage_Data_Type
assign volts_dt = volts[28:11];
assign V = volts_dt;
endmodule // controllerHdl_Frequency_To_Volts

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Generate_Position_And_Voltage_Ramp.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Generate_Position_And_Voltage_Ramp
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Generate_Position_And_Voltage_Ramp
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
target_velocity,
param_open_loop_bias,
param_open_loop_scalar,
Q_Voltage,
Position
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [17:0] target_velocity; // sfix18_En8
input signed [17:0] param_open_loop_bias; // sfix18_En14
input signed [17:0] param_open_loop_scalar; // sfix18_En16
output signed [17:0] Q_Voltage; // sfix18_En12
output signed [17:0] Position; // sfix18_En14
wire signed [31:0] rotor_velocity; // sfix32_En22
wire signed [17:0] volts_dt; // sfix18_En12
wire signed [17:0] electrical_velocity; // sfix18_En6
wire signed [17:0] electrical_position; // sfix18_En14
// Generate Position And Voltage
// <S17>/Rotor_Acceleration_To_Velocity
controllerHdl_Rotor_Acceleration_To_Velocity u_Rotor_Acceleration_To_Velocity (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reset_1),
.Vel_Target(target_velocity), // sfix18_En8
.RV(rotor_velocity) // sfix32_En22
);
// <S17>/Frequency_To_Volts
controllerHdl_Frequency_To_Volts u_Frequency_To_Volts (.F(rotor_velocity), // sfix32_En22
.param_open_loop_bias(param_open_loop_bias), // sfix18_En14
.param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16
.V(volts_dt) // sfix18_En12
);
assign Q_Voltage = volts_dt;
// <S17>/Rotor_To_Electical_Velocity
controllerHdl_Rotor_To_Electical_Velocity u_Rotor_To_Electical_Velocity (.RV(rotor_velocity), // sfix32_En22
.EV(electrical_velocity) // sfix18_En6
);
// <S17>/Electrical_Velocity_To_Position
controllerHdl_Electrical_Velocity_To_Position u_Electrical_Velocity_To_Position (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reset_1),
.EV(electrical_velocity), // sfix18_En6
.EP(electrical_position) // sfix18_En14
);
assign Position = electrical_position;
endmodule // controllerHdl_Generate_Position_And_Voltage_Ramp

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Inverse_Clarke_Transform.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Inverse_Clarke_Transform
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Clarke_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Inverse_Clarke_Transform
(
alpha_voltage,
beta_voltage,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2
);
input signed [17:0] alpha_voltage; // sfix18_En10
input signed [17:0] beta_voltage; // sfix18_En10
output signed [17:0] phase_voltages_0; // sfix18_En13
output signed [17:0] phase_voltages_1; // sfix18_En13
output signed [17:0] phase_voltages_2; // sfix18_En13
wire signed [35:0] voltage_phase_a; // sfix36_En26
wire signed [35:0] Gain1_out1; // sfix36_En26
wire signed [35:0] Gain_out1; // sfix36_En26
wire signed [35:0] voltage_phase_b; // sfix36_En26
wire signed [37:0] Add1_cast; // sfix38_En26
wire signed [37:0] Add1_cast_1; // sfix38_En26
wire signed [37:0] Add1_sub_cast; // sfix38_En26
wire signed [37:0] Add1_sub_temp; // sfix38_En26
wire signed [35:0] voltage_phase_c; // sfix36_En26
wire signed [35:0] Mux_out1 [0:2]; // sfix36_En26 [3]
wire signed [17:0] Current_Data_Type_out1 [0:2]; // sfix18_En13 [3]
// Inverse Clarke Transform
//
// Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities
// The alpha and beta components are dependent on time and speed.
// <S39>/Data Type Conversion
assign voltage_phase_a = {{2{alpha_voltage[17]}}, {alpha_voltage, 16'b0000000000000000}};
// <S39>/Gain1
assign Gain1_out1 = 56756 * beta_voltage;
// <S39>/Gain
assign Gain_out1 = {{3{alpha_voltage[17]}}, {alpha_voltage, 15'b000000000000000}};
// <S39>/Add
assign voltage_phase_b = Gain1_out1 - Gain_out1;
// <S39>/Add1
assign Add1_cast = Gain_out1;
assign Add1_cast_1 = - (Add1_cast);
assign Add1_sub_cast = Gain1_out1;
assign Add1_sub_temp = Add1_cast_1 - Add1_sub_cast;
assign voltage_phase_c = Add1_sub_temp[35:0];
// <S39>/Mux
assign Mux_out1[0] = voltage_phase_a;
assign Mux_out1[1] = voltage_phase_b;
assign Mux_out1[2] = voltage_phase_c;
// <S39>/Current_Data_Type
assign Current_Data_Type_out1[0] = ((Mux_out1[0][35] == 1'b0) && (Mux_out1[0][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[0][35] == 1'b1) && (Mux_out1[0][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[0][30:13])));
assign Current_Data_Type_out1[1] = ((Mux_out1[1][35] == 1'b0) && (Mux_out1[1][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[1][35] == 1'b1) && (Mux_out1[1][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[1][30:13])));
assign Current_Data_Type_out1[2] = ((Mux_out1[2][35] == 1'b0) && (Mux_out1[2][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[2][35] == 1'b1) && (Mux_out1[2][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[2][30:13])));
assign phase_voltages_0 = Current_Data_Type_out1[0];
assign phase_voltages_1 = Current_Data_Type_out1[1];
assign phase_voltages_2 = Current_Data_Type_out1[2];
endmodule // controllerHdl_Inverse_Clarke_Transform

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Inverse_Park_Transform.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Inverse_Park_Transform
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Park_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Inverse_Park_Transform
(
direct_voltage,
quadrature_voltage,
sin_coefficient,
cos_coefficient,
alpha_voltage,
beta_voltage
);
input signed [17:0] direct_voltage; // sfix18_En12
input signed [17:0] quadrature_voltage; // sfix18_En12
input signed [17:0] sin_coefficient; // sfix18_En16
input signed [17:0] cos_coefficient; // sfix18_En16
output signed [17:0] alpha_voltage; // sfix18_En10
output signed [17:0] beta_voltage; // sfix18_En10
wire signed [35:0] Product2_out1; // sfix36_En28
wire signed [35:0] Product3_out1; // sfix36_En28
wire signed [35:0] alpha_voltage_1; // sfix36_En28
wire signed [17:0] Convert_Data_Type_out1; // sfix18_En10
wire signed [35:0] Product_out1; // sfix36_En28
wire signed [35:0] Product1_out1; // sfix36_En28
wire signed [35:0] beta_voltage_1; // sfix36_En28
wire signed [17:0] Convert_Data_Type1_out1; // sfix18_En10
// Inverse Park Transform
//
// Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta)
// <S40>/Product2
assign Product2_out1 = direct_voltage * cos_coefficient;
// <S40>/Product3
assign Product3_out1 = quadrature_voltage * sin_coefficient;
// <S40>/Add1
assign alpha_voltage_1 = Product2_out1 - Product3_out1;
// <S40>/Convert_Data_Type
controllerHdl_Convert_Data_Type_block2 u_Convert_Data_Type (.In1(alpha_voltage_1), // sfix36_En28
.Out1(Convert_Data_Type_out1) // sfix18_En10
);
assign alpha_voltage = Convert_Data_Type_out1;
// <S40>/Product
assign Product_out1 = direct_voltage * sin_coefficient;
// <S40>/Product1
assign Product1_out1 = quadrature_voltage * cos_coefficient;
// <S40>/Add
assign beta_voltage_1 = Product_out1 + Product1_out1;
// <S40>/Convert_Data_Type1
controllerHdl_Convert_Data_Type1 u_Convert_Data_Type1 (.In1(beta_voltage_1), // sfix36_En28
.Out1(Convert_Data_Type1_out1) // sfix18_En10
);
assign beta_voltage = Convert_Data_Type1_out1;
endmodule // controllerHdl_Inverse_Park_Transform

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function
(
u,
y
);
input [35:0] u; // ufix36
output [17:0] y; // ufix18
//MATLAB Function 'Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits/MATLAB Function': '<S13>:1'
// Non-tunable mask parameter
//'<S13>:1:8'
//'<S13>:1:10'
assign y = u[17:0];
//'<S13>:1:14'
endmodule // controllerHdl_MATLAB_Function

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function_block
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function_block
(
u,
y
);
input [17:0] u; // ufix18
output [8:0] y; // ufix9
wire [8:0] y1; // ufix9_E9
//MATLAB Function 'Open_Loop_Control/Sin_Cos/Mark_Extract_Bits/MATLAB Function': '<S37>:1'
// Non-tunable mask parameter
//'<S37>:1:8'
//'<S37>:1:10'
assign y1 = u[17:9];
//'<S37>:1:14'
assign y = y1;
endmodule // controllerHdl_MATLAB_Function_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block1.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function_block1
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits1/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function_block1
(
u,
y
);
input [17:0] u; // ufix18
output [8:0] y; // ufix9
//MATLAB Function 'Open_Loop_Control/Sin_Cos/Mark_Extract_Bits1/MATLAB Function': '<S38>:1'
// Non-tunable mask parameter
//'<S38>:1:8'
//'<S38>:1:10'
assign y = u[8:0];
//'<S38>:1:14'
endmodule // controllerHdl_MATLAB_Function_block1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block2.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function_block2
// Source Path: controllerHdl/Field_Oriented_Control/MATLAB Function
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function_block2
(
CLK_IN,
reset,
enb_1_2000_0,
cMode,
index,
reset_1
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input [1:0] cMode; // ufix2
output [1:0] index; // ufix2
output reset_1;
parameter [1:0] controllerModeEnum_VelocityControl = 2; // ufix2
parameter [1:0] controllerModeEnum_OpenLoopVelocityControl = 3; // ufix2
reg [1:0] index_1; // ufix2
reg reset_2;
reg [1:0] index_n1; // ufix2
reg [1:0] index_n1_next; // ufix2
reg [1:0] index_2; // ufix2
always @(posedge CLK_IN)
begin : MATLAB_Function_process
if (reset == 1'b1) begin
index_n1 <= 2'b10;
end
else if (enb_1_2000_0) begin
index_n1 <= index_n1_next;
end
end
always @(cMode, index_n1) begin
//MATLAB Function 'Field_Oriented_Control/MATLAB Function': '<S14>:1'
//.
if (cMode == controllerModeEnum_OpenLoopVelocityControl) begin
//'<S14>:1:17'
index_2 = 2'b00;
end
else if (cMode == controllerModeEnum_VelocityControl) begin
//'<S14>:1:19'
index_2 = 2'b01;
end
else begin
//'<S14>:1:21'
index_2 = 2'b10;
end
if (index_2 != index_n1) begin
//'<S14>:1:25'
reset_2 = 1'b1;
end
else begin
//'<S14>:1:27'
reset_2 = 1'b0;
end
//'<S14>:1:29'
index_n1_next = index_2;
index_1 = index_2;
end
assign index = index_1;
assign reset_1 = reset_2;
endmodule // controllerHdl_MATLAB_Function_block2

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block3.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function_block3
// Source Path: controllerHdl/MATLAB Function
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function_block3
(
CLK_IN,
reset,
enb_1_2000_0,
u,
y
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input signed [18:0] u; // sfix19_En14
output signed [18:0] y; // sfix19_En14
reg signed [18:0] y_1; // sfix19_En14
reg sel;
reg [15:0] count_n; // ufix16
reg [15:0] count_p; // ufix16
reg signed [18:0] u_n1; // sfix19
reg signed [18:0] u_filter_p; // sfix19
reg signed [18:0] u_filter_n; // sfix19
reg sel_next;
reg [15:0] count_n_next; // ufix16
reg [15:0] count_p_next; // ufix16
reg signed [18:0] u_n1_next; // sfix19_En14
reg signed [18:0] u_filter_p_next; // sfix19_En14
reg signed [18:0] u_filter_n_next; // sfix19_En14
reg signed [37:0] a1_1; // sfix38_En28
reg signed [37:0] b1_1; // sfix38_En28
reg signed [37:0] c1_1; // sfix38_En28
reg signed [37:0] a1_0_1; // sfix38_En28
reg signed [37:0] b1_0_1; // sfix38_En28
reg signed [37:0] c1_0_1; // sfix38_En28
reg sel_temp_1;
reg signed [18:0] u_filter_p_temp_1; // sfix19_En14
reg signed [18:0] u_filter_n_temp_1; // sfix19_En14
always @(posedge CLK_IN)
begin : MATLAB_Function_process
if (reset == 1'b1) begin
sel <= 1'b0;
u_n1 <= 19'sb0000000000000000000;
u_filter_p <= 19'sb0000000000000000000;
u_filter_n <= 19'sb0000000000000000000;
count_n <= 16'b0000000000000000;
count_p <= 16'b0000000000000000;
end
else if (enb_1_2000_0) begin
sel <= sel_next;
count_n <= count_n_next;
count_p <= count_p_next;
u_n1 <= u_n1_next;
u_filter_p <= u_filter_p_next;
u_filter_n <= u_filter_n_next;
end
end
always @(u, sel, count_n, count_p, u_n1, u_filter_p, u_filter_n) begin
sel_temp_1 = sel;
u_filter_p_temp_1 = u_filter_p;
u_filter_n_temp_1 = u_filter_n;
count_n_next = count_n;
count_p_next = count_p;
//MATLAB Function 'MATLAB Function': '<S4>:1'
if ((u < 19'sb0000000000000000000) && (u_n1 > 19'sb0000000000000000000)) begin
//'<S4>:1:25'
sel_temp_1 = count_p > count_n;
//'<S4>:1:26'
count_n_next = 16'b0000000000000000;
//'<S4>:1:27'
count_p_next = 16'b0000000000000000;
end
else if (u > 19'sb0000000000000000000) begin
//'<S4>:1:31'
a1_0_1 = 14336 * u_filter_p;
b1_0_1 = {{8{u[18]}}, {u, 11'b00000000000}};
c1_0_1 = a1_0_1 + b1_0_1;
if (((c1_0_1[37] == 1'b0) && (c1_0_1[36:32] != 5'b00000)) || ((c1_0_1[37] == 1'b0) && (c1_0_1[32:14] == 19'sb0111111111111111111))) begin
u_filter_p_temp_1 = 19'sb0111111111111111111;
end
else if ((c1_0_1[37] == 1'b1) && (c1_0_1[36:32] != 5'b11111)) begin
u_filter_p_temp_1 = 19'sb1000000000000000000;
end
else begin
u_filter_p_temp_1 = c1_0_1[32:14] + $signed({1'b0, c1_0_1[13]});
end
//'<S4>:1:32'
count_p_next = count_p + 1;
end
else begin
//'<S4>:1:34'
a1_1 = 14336 * u_filter_n;
b1_1 = {{8{u[18]}}, {u, 11'b00000000000}};
c1_1 = a1_1 + b1_1;
if (((c1_1[37] == 1'b0) && (c1_1[36:32] != 5'b00000)) || ((c1_1[37] == 1'b0) && (c1_1[32:14] == 19'sb0111111111111111111))) begin
u_filter_n_temp_1 = 19'sb0111111111111111111;
end
else if ((c1_1[37] == 1'b1) && (c1_1[36:32] != 5'b11111)) begin
u_filter_n_temp_1 = 19'sb1000000000000000000;
end
else begin
u_filter_n_temp_1 = c1_1[32:14] + $signed({1'b0, c1_1[13]});
end
//'<S4>:1:35'
count_n_next = count_n + 1;
end
//'<S4>:1:39'
u_n1_next = u;
if (sel_temp_1) begin
//'<S4>:1:40'
//'<S4>:1:41'
y_1 = u_filter_p_temp_1;
end
else begin
//'<S4>:1:43'
y_1 = u_filter_n_temp_1;
end
sel_next = sel_temp_1;
u_filter_p_next = u_filter_p_temp_1;
u_filter_n_next = u_filter_n_temp_1;
end
assign y = y_1;
endmodule // controllerHdl_MATLAB_Function_block3

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mark_Extract_Bits.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Mark_Extract_Bits
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Mark_Extract_Bits
(
In1,
Out1
);
input [35:0] In1; // ufix36
output [17:0] Out1; // ufix18
wire [17:0] MATLAB_Function_out1; // ufix18
// <S12>/MATLAB Function
controllerHdl_MATLAB_Function u_MATLAB_Function (.u(In1), // ufix36
.y(MATLAB_Function_out1) // ufix18
);
assign Out1 = MATLAB_Function_out1;
endmodule // controllerHdl_Mark_Extract_Bits

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mark_Extract_Bits1.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Mark_Extract_Bits1
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits1
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Mark_Extract_Bits1
(
In1,
Out1
);
input [17:0] In1; // ufix18
output [8:0] Out1; // ufix9
wire [8:0] MATLAB_Function_out1; // ufix9
// <S36>/MATLAB Function
controllerHdl_MATLAB_Function_block1 u_MATLAB_Function (.u(In1), // ufix18
.y(MATLAB_Function_out1) // ufix9
);
assign Out1 = MATLAB_Function_out1;
endmodule // controllerHdl_Mark_Extract_Bits1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mark_Extract_Bits_block.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Mark_Extract_Bits_block
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Mark_Extract_Bits_block
(
In1,
Out1
);
input [17:0] In1; // ufix18
output [8:0] Out1; // ufix9
wire [8:0] MATLAB_Function_out1; // ufix9
// <S35>/MATLAB Function
controllerHdl_MATLAB_Function_block u_MATLAB_Function (.u(In1), // ufix18
.y(MATLAB_Function_out1) // ufix9
);
assign Out1 = MATLAB_Function_out1;
endmodule // controllerHdl_Mark_Extract_Bits_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mod_2pi_Scale_And_Bit_Slice.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Mod_2pi_Scale_And_Bit_Slice
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Mod_2pi_Scale_And_Bit_Slice
(
u,
y
);
input signed [17:0] u; // sfix18_En12
output signed [17:0] y; // sfix18_En14
wire signed [35:0] Pre_Scale_mul_temp; // sfix36_En13
wire [35:0] Pre_Scale_out1; // ufix36
wire [17:0] y_1; // ufix18
wire [35:0] Post_Scale_mul_temp; // ufix36_En33
wire signed [17:0] Post_Scale_out1; // sfix18_En14
// <S11>/Pre_Scale
//
// <S11>/Remove Scaling
assign Pre_Scale_mul_temp = 83443 * u;
assign Pre_Scale_out1 = {{13{Pre_Scale_mul_temp[35]}}, Pre_Scale_mul_temp[35:13]};
// <S11>/Mark_Extract_Bits
controllerHdl_Mark_Extract_Bits u_Mark_Extract_Bits (.In1(Pre_Scale_out1), // ufix36
.Out1(y_1) // ufix18
);
// <S11>/Post_Scale
assign Post_Scale_mul_temp = 205888 * y_1;
assign Post_Scale_out1 = Post_Scale_mul_temp[35:19];
assign y = Post_Scale_out1;
endmodule // controllerHdl_Mod_2pi_Scale_And_Bit_Slice

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Open_Loop_Control.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Open_Loop_Control
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Open_Loop_Control
(
CLK_IN,
reset,
enb_1_2000_0,
reset_1,
command_value,
param_open_loop_bias,
param_open_loop_scalar,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2,
electrical_position
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input reset_1;
input signed [17:0] command_value; // sfix18_En8
input signed [17:0] param_open_loop_bias; // sfix18_En14
input signed [17:0] param_open_loop_scalar; // sfix18_En16
output signed [17:0] phase_voltages_0; // sfix18_En13
output signed [17:0] phase_voltages_1; // sfix18_En13
output signed [17:0] phase_voltages_2; // sfix18_En13
output signed [17:0] electrical_position; // sfix18_En14
wire signed [17:0] direct_voltage; // sfix18_En12
wire signed [17:0] volts_dt; // sfix18_En12
wire signed [17:0] Generate_Position_And_Voltage_Ramp_out2; // sfix18_En14
wire signed [17:0] sin_coefficient; // sfix18_En16
wire signed [17:0] cos_coefficient; // sfix18_En16
wire signed [17:0] Transform_dq_to_ABC_out1_0; // sfix18_En13
wire signed [17:0] Transform_dq_to_ABC_out1_1; // sfix18_En13
wire signed [17:0] Transform_dq_to_ABC_out1_2; // sfix18_En13
// <S15>/Zero
assign direct_voltage = 18'sb000000000000000000;
// <S15>/Generate_Position_And_Voltage_Ramp
controllerHdl_Generate_Position_And_Voltage_Ramp u_Generate_Position_And_Voltage_Ramp (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(reset_1),
.target_velocity(command_value), // sfix18_En8
.param_open_loop_bias(param_open_loop_bias), // sfix18_En14
.param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16
.Q_Voltage(volts_dt), // sfix18_En12
.Position(Generate_Position_And_Voltage_Ramp_out2) // sfix18_En14
);
// <S15>/Sin_Cos
controllerHdl_Sin_Cos u_Sin_Cos (.x(Generate_Position_And_Voltage_Ramp_out2), // sfix18_En14
.sin(sin_coefficient), // sfix18_En16
.cos(cos_coefficient) // sfix18_En16
);
// <S15>/Transform_dq_to_ABC
controllerHdl_Transform_dq_to_ABC u_Transform_dq_to_ABC (.d(direct_voltage), // sfix18_En12
.q(volts_dt), // sfix18_En12
.sin(sin_coefficient), // sfix18_En16
.cos(cos_coefficient), // sfix18_En16
.ABC_0(Transform_dq_to_ABC_out1_0), // sfix18_En13
.ABC_1(Transform_dq_to_ABC_out1_1), // sfix18_En13
.ABC_2(Transform_dq_to_ABC_out1_2) // sfix18_En13
);
assign phase_voltages_0 = Transform_dq_to_ABC_out1_0;
assign phase_voltages_1 = Transform_dq_to_ABC_out1_1;
assign phase_voltages_2 = Transform_dq_to_ABC_out1_2;
assign electrical_position = Generate_Position_And_Voltage_Ramp_out2;
endmodule // controllerHdl_Open_Loop_Control

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Phase_Voltages_To_Compare_Values.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Phase_Voltages_To_Compare_Values
// Source Path: controllerHdl/Phase_Voltages_To_Compare_Values
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Phase_Voltages_To_Compare_Values
(
V_0,
V_1,
V_2,
C_0,
C_1,
C_2
);
input signed [19:0] V_0; // sfix20_En12
input signed [19:0] V_1; // sfix20_En12
input signed [19:0] V_2; // sfix20_En12
output [15:0] C_0; // uint16
output [15:0] C_1; // uint16
output [15:0] C_2; // uint16
wire signed [19:0] V [0:2]; // sfix20_En12 [3]
wire signed [19:0] Half_Bus_Voltage_out1; // sfix20_En12
wire signed [20:0] Add2_v; // sfix21_En12
wire signed [20:0] Add2_add_cast; // sfix21_En12
wire signed [20:0] Add2_add_temp; // sfix21_En12
wire signed [20:0] Add2_add_cast_1; // sfix21_En12
wire signed [20:0] Add2_add_temp_1; // sfix21_En12
wire signed [20:0] Add2_add_cast_2; // sfix21_En12
wire signed [20:0] Add2_add_temp_2; // sfix21_En12
wire signed [19:0] Add2_out1 [0:2]; // sfix20_En12 [3]
wire signed [39:0] Voltage_To_PWM_Compare_Units_out1 [0:2]; // sfix40_En24 [3]
wire signed [39:0] Saturation1_out1 [0:2]; // sfix40_En24 [3]
wire [15:0] pwm_compare [0:2]; // uint16 [3]
assign V[0] = V_0;
assign V[1] = V_1;
assign V[2] = V_2;
// <S5>/Half_Bus_Voltage
assign Half_Bus_Voltage_out1 = 20'sb00000110000000000000;
// <S5>/Add2
assign Add2_v = Half_Bus_Voltage_out1;
assign Add2_add_cast = V[0];
assign Add2_add_temp = Add2_add_cast + Add2_v;
assign Add2_out1[0] = Add2_add_temp[19:0];
assign Add2_add_cast_1 = V[1];
assign Add2_add_temp_1 = Add2_add_cast_1 + Add2_v;
assign Add2_out1[1] = Add2_add_temp_1[19:0];
assign Add2_add_cast_2 = V[2];
assign Add2_add_temp_2 = Add2_add_cast_2 + Add2_v;
assign Add2_out1[2] = Add2_add_temp_2[19:0];
// <S5>/Voltage_To_PWM_Compare_Units
assign Voltage_To_PWM_Compare_Units_out1[0] = 341333 * Add2_out1[0];
assign Voltage_To_PWM_Compare_Units_out1[1] = 341333 * Add2_out1[1];
assign Voltage_To_PWM_Compare_Units_out1[2] = 341333 * Add2_out1[2];
// <S5>/Saturation1
assign Saturation1_out1[0] = (Voltage_To_PWM_Compare_Units_out1[0] > 40'sh03E8000000 ? 40'sh03E8000000 :
(Voltage_To_PWM_Compare_Units_out1[0] < 40'sh0000000000 ? 40'sh0000000000 :
Voltage_To_PWM_Compare_Units_out1[0]));
assign Saturation1_out1[1] = (Voltage_To_PWM_Compare_Units_out1[1] > 40'sh03E8000000 ? 40'sh03E8000000 :
(Voltage_To_PWM_Compare_Units_out1[1] < 40'sh0000000000 ? 40'sh0000000000 :
Voltage_To_PWM_Compare_Units_out1[1]));
assign Saturation1_out1[2] = (Voltage_To_PWM_Compare_Units_out1[2] > 40'sh03E8000000 ? 40'sh03E8000000 :
(Voltage_To_PWM_Compare_Units_out1[2] < 40'sh0000000000 ? 40'sh0000000000 :
Voltage_To_PWM_Compare_Units_out1[2]));
// <S5>/Data Type Conversion1
assign pwm_compare[0] = Saturation1_out1[0][39:24];
assign pwm_compare[1] = Saturation1_out1[1][39:24];
assign pwm_compare[2] = Saturation1_out1[2][39:24];
assign C_0 = pwm_compare[0];
assign C_1 = pwm_compare[1];
assign C_2 = pwm_compare[2];
endmodule // controllerHdl_Phase_Voltages_To_Compare_Values

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Reset_Delay.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Reset_Delay
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Electrical_Velocity_To_Position/Reset_Delay
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Reset_Delay
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
In,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [31:0] In; // sfix32_En27
output signed [31:0] Out; // sfix32_En27
wire signed [31:0] Constant1_out1; // sfix32_En27
wire signed [31:0] Reset_Switch1_out1; // sfix32_En27
reg signed [31:0] In_Delay_out1; // sfix32_En27
wire signed [31:0] Constant_out1; // sfix32_En27
wire signed [31:0] Reset_Switch_out1; // sfix32_En27
// <S24>/Constant1
assign Constant1_out1 = 32'sb00000000000000000000000000000000;
// <S24>/Reset_Switch1
assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In :
Constant1_out1);
// <S24>/In_Delay
always @(posedge CLK_IN)
begin : In_Delay_process
if (reset == 1'b1) begin
In_Delay_out1 <= 32'sb00000000000000000000000000000000;
end
else if (enb_1_2000_0) begin
In_Delay_out1 <= Reset_Switch1_out1;
end
end
// <S24>/Constant
assign Constant_out1 = 32'sb00000000000000000000000000000000;
// <S24>/Reset_Switch
assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 :
Constant_out1);
assign Out = Reset_Switch_out1;
endmodule // controllerHdl_Reset_Delay

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Reset_Delay_block.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Reset_Delay_block
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity/Reset_Delay
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Reset_Delay_block
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
In,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [31:0] In; // sfix32_En22
output signed [31:0] Out; // sfix32_En22
wire signed [31:0] Constant1_out1; // sfix32_En22
wire signed [31:0] Reset_Switch1_out1; // sfix32_En22
reg signed [31:0] In_Delay_out1; // sfix32_En22
wire signed [31:0] Constant_out1; // sfix32_En22
wire signed [31:0] Reset_Switch_out1; // sfix32_En22
// <S28>/Constant1
assign Constant1_out1 = 32'sb00000000000000000000000000000000;
// <S28>/Reset_Switch1
assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In :
Constant1_out1);
// <S28>/In_Delay
always @(posedge CLK_IN)
begin : In_Delay_process
if (reset == 1'b1) begin
In_Delay_out1 <= 32'sb00000000000000000000000000000000;
end
else if (enb_1_2000_0) begin
In_Delay_out1 <= Reset_Switch1_out1;
end
end
// <S28>/Constant
assign Constant_out1 = 32'sb00000000000000000000000000000000;
// <S28>/Reset_Switch
assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 :
Constant_out1);
assign Out = Reset_Switch_out1;
endmodule // controllerHdl_Reset_Delay_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Rotor_Acceleration_To_Velocity.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Rotor_Acceleration_To_Velocity
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Rotor_Acceleration_To_Velocity
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
Vel_Target,
RV
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [17:0] Vel_Target; // sfix18_En8
output signed [31:0] RV; // sfix32_En22
wire signed [31:0] Reset_Delay_out1; // sfix32_En22
wire signed [17:0] Set_Acceleration_out1; // sfix18_En10
wire signed [35:0] Gain_out1; // sfix36_En41
wire signed [31:0] Convert_out1; // sfix32_En22
wire signed [32:0] Sum_add_cast; // sfix33_En22
wire signed [32:0] Sum_add_cast_1; // sfix33_En22
wire signed [32:0] Sum_add_temp; // sfix33_En22
wire signed [31:0] Sum_out1; // sfix32_En22
// Rotor Acceleration To Velocity
// <S22>/Set_Acceleration
controllerHdl_Set_Acceleration u_Set_Acceleration (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.v_target(Vel_Target), // sfix18_En8
.v_current(Reset_Delay_out1), // sfix32_En22
.a(Set_Acceleration_out1) // sfix18_En10
);
// <S22>/Gain
assign Gain_out1 = 85899 * Set_Acceleration_out1;
// <S22>/Convert
assign Convert_out1 = {{15{Gain_out1[35]}}, Gain_out1[35:19]};
// <S22>/Sum
assign Sum_add_cast = Convert_out1;
assign Sum_add_cast_1 = Reset_Delay_out1;
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = ((Sum_add_temp[32] == 1'b0) && (Sum_add_temp[31] != 1'b0) ? 32'sb01111111111111111111111111111111 :
((Sum_add_temp[32] == 1'b1) && (Sum_add_temp[31] != 1'b1) ? 32'sb10000000000000000000000000000000 :
$signed(Sum_add_temp[31:0])));
// <S22>/Reset_Delay
controllerHdl_Reset_Delay_block u_Reset_Delay (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reset_1),
.In(Sum_out1), // sfix32_En22
.Out(Reset_Delay_out1) // sfix32_En22
);
assign RV = Reset_Delay_out1;
endmodule // controllerHdl_Rotor_Acceleration_To_Velocity

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Rotor_To_Electical_Velocity.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Rotor_To_Electical_Velocity
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_To_Electical_Velocity
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Rotor_To_Electical_Velocity
(
RV,
EV
);
input signed [31:0] RV; // sfix32_En22
output signed [17:0] EV; // sfix18_En6
wire signed [17:0] Convert_Data_Type_out1; // sfix18_En8
wire signed [35:0] number_of_pole_pairs_out1; // sfix36_En22
wire signed [17:0] Electrical_Velocity_Data_Type_out1; // sfix18_En6
// Rotor To Electrical Velocity
// <S23>/Convert_Data_Type
controllerHdl_Convert_Data_Type_block u_Convert_Data_Type (.In1(RV), // sfix32_En22
.Out1(Convert_Data_Type_out1) // sfix18_En8
);
// <S23>/number_of_pole_pairs
assign number_of_pole_pairs_out1 = {{2{Convert_Data_Type_out1[17]}}, {Convert_Data_Type_out1, 16'b0000000000000000}};
// <S23>/Electrical_Velocity_Data_Type
assign Electrical_Velocity_Data_Type_out1 = number_of_pole_pairs_out1[33:16];
assign EV = Electrical_Velocity_Data_Type_out1;
endmodule // controllerHdl_Rotor_To_Electical_Velocity

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Rotor_To_Electrical_Position.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Rotor_To_Electrical_Position
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Rotor_To_Electrical_Position
(
R,
E
);
input signed [17:0] R; // sfix18_En14
output signed [17:0] E; // sfix18_En14
wire signed [35:0] number_of_pole_pairs_cast; // sfix36_En28
wire signed [17:0] number_of_pole_pairs_out1; // sfix18_En12
wire signed [17:0] Mod_2pi_Scale_And_Bit_Slice_out1; // sfix18_En14
// Rotor To Electrical Position
// <S8>/number_of_pole_pairs
assign number_of_pole_pairs_cast = {{2{R[17]}}, {R, 16'b0000000000000000}};
assign number_of_pole_pairs_out1 = number_of_pole_pairs_cast[33:16];
// <S8>/Mod_2pi_Scale_And_Bit_Slice
controllerHdl_Mod_2pi_Scale_And_Bit_Slice u_Mod_2pi_Scale_And_Bit_Slice (.u(number_of_pole_pairs_out1), // sfix18_En12
.y(Mod_2pi_Scale_And_Bit_Slice_out1) // sfix18_En14
);
assign E = Mod_2pi_Scale_And_Bit_Slice_out1;
endmodule // controllerHdl_Rotor_To_Electrical_Position

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Set_Acceleration.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Set_Acceleration
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity/Set_Acceleration
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Set_Acceleration
(
CLK_IN,
reset,
enb_1_2000_0,
v_target,
v_current,
a
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input signed [17:0] v_target; // sfix18_En8
input signed [31:0] v_current; // sfix32_En22
output signed [17:0] a; // sfix18_En10
wire signed [31:0] Relational_Operator_1_cast; // sfix32_En22
wire Relational_Operator_relop1;
wire current_less_than_target;
wire current_less_than_target_1;
wire current_greater_than_target;
wire target_has_changed;
wire Latch_out1;
reg Delay1_out1;
wire Latch_out1_1;
wire negative_direction;
wire switch_compare_1;
wire signed [17:0] Acceleration1_out1; // sfix18_En10
wire signed [18:0] Neg_cast; // sfix19_En10
wire signed [18:0] Neg_cast_1; // sfix19_En10
wire signed [35:0] Neg_cast_2; // sfix36_En27
wire signed [17:0] Neg_out1; // sfix18_En10
wire current_greater_than_target_1;
wire stop_positive_acceleration;
wire current_less_than_target_2;
wire stop_negative_acceleration;
wire stop_positive_acceleration_1;
wire stop_accelerating;
wire signed [17:0] positive_accleration; // sfix18_En10
wire signed [17:0] accleration; // sfix18_En10
wire signed [17:0] Constant_out1; // sfix18_En10
wire signed [17:0] Switch_Stop_out1; // sfix18_En10
// Set Acceleration
// <S29>/Relational Operator
assign Relational_Operator_1_cast = {v_target, 14'b00000000000000};
assign Relational_Operator_relop1 = (Relational_Operator_1_cast > v_current ? 1'b1 :
1'b0);
assign current_less_than_target = Relational_Operator_relop1;
// <S29>/NOT2
assign current_less_than_target_1 = ~ current_less_than_target;
assign current_greater_than_target = current_less_than_target_1;
// <S29>/Detect_Change
controllerHdl_Detect_Change u_Detect_Change (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.x(v_target), // sfix18_En8
.y(target_has_changed)
);
// <S29>/Delay1
always @(posedge CLK_IN)
begin : Delay1_process
if (reset == 1'b1) begin
Delay1_out1 <= 1'b0;
end
else if (enb_1_2000_0) begin
Delay1_out1 <= Latch_out1;
end
end
// <S29>/Latch
//
// <S29>/Signal Specification
assign Latch_out1 = (target_has_changed == 1'b0 ? Delay1_out1 :
current_less_than_target);
// <S29>/NOT3
assign Latch_out1_1 = ~ Latch_out1;
assign negative_direction = Latch_out1_1;
assign switch_compare_1 = (Latch_out1 > 1'b0 ? 1'b1 :
1'b0);
// <S29>/Acceleration1
assign Acceleration1_out1 = 18'sb001010000000000000;
// <S29>/Neg
assign Neg_cast = Acceleration1_out1;
assign Neg_cast_1 = - (Neg_cast);
assign Neg_cast_2 = {Neg_cast_1, 17'b00000000000000000};
assign Neg_out1 = Neg_cast_2[34:17];
// <S29>/AND_Pos
assign current_greater_than_target_1 = current_greater_than_target & Latch_out1;
assign stop_positive_acceleration = current_greater_than_target_1;
// <S29>/AND_Neg
assign current_less_than_target_2 = current_less_than_target & negative_direction;
assign stop_negative_acceleration = current_less_than_target_2;
// <S29>/OR_SAT1
assign stop_positive_acceleration_1 = stop_positive_acceleration | stop_negative_acceleration;
assign stop_accelerating = stop_positive_acceleration_1;
// <S29>/Acceleration
assign positive_accleration = 18'sb001010000000000000;
// <S29>/Switch_Dir
assign accleration = (switch_compare_1 == 1'b0 ? Neg_out1 :
positive_accleration);
// <S29>/Constant
assign Constant_out1 = 18'sb000000000000000000;
// <S29>/Switch_Stop
assign Switch_Stop_out1 = (stop_accelerating == 1'b0 ? accleration :
Constant_out1);
assign a = Switch_Stop_out1;
endmodule // controllerHdl_Set_Acceleration

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_StandBy.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_StandBy
// Source Path: controllerHdl/Field_Oriented_Control/StandBy
// Hierarchy Level: 3
//
// Simulink subsystem description for controllerHdl/Field_Oriented_Control/StandBy:
//
// Stand By mode for controller outputs constant phase voltages.
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_StandBy
(
Phase_Voltages_0,
Phase_Voltages_1,
Phase_Voltages_2
);
output signed [19:0] Phase_Voltages_0; // sfix20_En12
output signed [19:0] Phase_Voltages_1; // sfix20_En12
output signed [19:0] Phase_Voltages_2; // sfix20_En12
wire signed [19:0] Constant_out1 [0:2]; // sfix20_En12 [3]
// StandBy
//
// Block Description: Controller outputs constant phase voltages.
// <S16>/Constant
assign Constant_out1[0] = 20'sb00000000000000000000;
assign Constant_out1[1] = 20'sb00000000000000000000;
assign Constant_out1[2] = 20'sb00000000000000000000;
assign Phase_Voltages_0 = Constant_out1[0];
assign Phase_Voltages_1 = Constant_out1[1];
assign Phase_Voltages_2 = Constant_out1[2];
endmodule // controllerHdl_StandBy

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Transform_dq_to_ABC.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Transform_dq_to_ABC
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Transform_dq_to_ABC
(
d,
q,
sin,
cos,
ABC_0,
ABC_1,
ABC_2
);
input signed [17:0] d; // sfix18_En12
input signed [17:0] q; // sfix18_En12
input signed [17:0] sin; // sfix18_En16
input signed [17:0] cos; // sfix18_En16
output signed [17:0] ABC_0; // sfix18_En13
output signed [17:0] ABC_1; // sfix18_En13
output signed [17:0] ABC_2; // sfix18_En13
wire signed [17:0] Inverse_Park_Transform_out1; // sfix18_En10
wire signed [17:0] Inverse_Park_Transform_out2; // sfix18_En10
wire signed [17:0] Inverse_Clarke_Transform_out1_0; // sfix18_En13
wire signed [17:0] Inverse_Clarke_Transform_out1_1; // sfix18_En13
wire signed [17:0] Inverse_Clarke_Transform_out1_2; // sfix18_En13
// Transform Coordinates dq to ABC
//
// Converts the two coordinate time invariant system (dq) to a three-phase time and speed dependent system (ABC).
// <S19>/Inverse_Park_Transform
controllerHdl_Inverse_Park_Transform u_Inverse_Park_Transform (.direct_voltage(d), // sfix18_En12
.quadrature_voltage(q), // sfix18_En12
.sin_coefficient(sin), // sfix18_En16
.cos_coefficient(cos), // sfix18_En16
.alpha_voltage(Inverse_Park_Transform_out1), // sfix18_En10
.beta_voltage(Inverse_Park_Transform_out2) // sfix18_En10
);
// <S19>/Inverse_Clarke_Transform
controllerHdl_Inverse_Clarke_Transform u_Inverse_Clarke_Transform (.alpha_voltage(Inverse_Park_Transform_out1), // sfix18_En10
.beta_voltage(Inverse_Park_Transform_out2), // sfix18_En10
.phase_voltages_0(Inverse_Clarke_Transform_out1_0), // sfix18_En13
.phase_voltages_1(Inverse_Clarke_Transform_out1_1), // sfix18_En13
.phase_voltages_2(Inverse_Clarke_Transform_out1_2) // sfix18_En13
);
assign ABC_0 = Inverse_Clarke_Transform_out1_0;
assign ABC_1 = Inverse_Clarke_Transform_out1_1;
assign ABC_2 = Inverse_Clarke_Transform_out1_2;
endmodule // controllerHdl_Transform_dq_to_ABC

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Wrap_2pi.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Wrap_2pi
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Encoder_To_Rotor_Position/Wrap_2pi
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Wrap_2pi
(
x,
wrap
);
input signed [18:0] x; // sfix19_En14
output signed [17:0] wrap; // sfix18_En14
wire signed [18:0] Two_Pi1_out1; // sfix19_En14
wire signed [18:0] Two_Pi3_out1; // sfix19_En14
wire Relational_Operator1_relop1;
wire signed [19:0] x_dtc; // sfix20_En14
wire signed [18:0] Two_Pi2_out1; // sfix19_En14
wire signed [18:0] Two_Pi_out1; // sfix19_En14
wire Relational_Operator_relop1;
wire signed [19:0] Add2_add_cast; // sfix20_En14
wire signed [19:0] Add2_add_cast_1; // sfix20_En14
wire signed [19:0] Add2_out1; // sfix20_En14
wire signed [19:0] Switch1_out1; // sfix20_En14
wire signed [17:0] Switch1_out1_dtc; // sfix18_En14
wire signed [19:0] Add1_sub_cast; // sfix20_En14
wire signed [19:0] Add1_sub_cast_1; // sfix20_En14
wire signed [19:0] Add1_out1; // sfix20_En14
wire signed [17:0] Add1_out1_dtc; // sfix18_En14
wire signed [17:0] Switch_out1; // sfix18_En14
// <S10>/Two Pi1
assign Two_Pi1_out1 = 19'sb0011001001000100000;
// <S10>/Two Pi3
assign Two_Pi3_out1 = 19'sb0000000000000000000;
// <S10>/Relational Operator1
assign Relational_Operator1_relop1 = (x < Two_Pi3_out1 ? 1'b1 :
1'b0);
assign x_dtc = x;
// <S10>/Two Pi2
assign Two_Pi2_out1 = 19'sb0011001001000100000;
// <S10>/Two Pi
assign Two_Pi_out1 = 19'sb0011001001000100000;
// <S10>/Relational Operator
assign Relational_Operator_relop1 = (x >= Two_Pi1_out1 ? 1'b1 :
1'b0);
// <S10>/Add2
assign Add2_add_cast = x;
assign Add2_add_cast_1 = Two_Pi2_out1;
assign Add2_out1 = Add2_add_cast + Add2_add_cast_1;
// <S10>/Switch1
assign Switch1_out1 = (Relational_Operator1_relop1 == 1'b0 ? x_dtc :
Add2_out1);
assign Switch1_out1_dtc = Switch1_out1[17:0];
// <S10>/Add1
assign Add1_sub_cast = x;
assign Add1_sub_cast_1 = Two_Pi_out1;
assign Add1_out1 = Add1_sub_cast - Add1_sub_cast_1;
assign Add1_out1_dtc = Add1_out1[17:0];
// <S10>/Switch
assign Switch_out1 = (Relational_Operator_relop1 == 1'b0 ? Switch1_out1_dtc :
Add1_out1_dtc);
assign wrap = Switch_out1;
endmodule // controllerHdl_Wrap_2pi

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Wrap_2pi_Once.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Wrap_2pi_Once
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Electrical_Velocity_To_Position/Wrap_2pi_Once
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Wrap_2pi_Once
(
x,
wrap
);
input signed [31:0] x; // sfix32_En27
output signed [31:0] wrap; // sfix32_En27
wire signed [31:0] Two_Pi1_out1; // sfix32_En27
wire Relational_Operator_relop1;
wire signed [31:0] Two_Pi3_out1; // sfix32_En27
wire Relational_Operator1_relop1;
wire signed [31:0] Two_Pi2_out1; // sfix32_En27
wire signed [31:0] Add2_out1; // sfix32_En27
wire signed [31:0] Switch1_out1; // sfix32_En27
wire signed [31:0] Two_Pi_out1; // sfix32_En27
wire signed [31:0] Add1_out1; // sfix32_En27
wire signed [31:0] Switch_out1; // sfix32_En27
// Wrap 2pi Once
// <S25>/Two Pi1
assign Two_Pi1_out1 = 32'sb00110010010000111111011010101001;
// <S25>/Relational Operator
assign Relational_Operator_relop1 = (x >= Two_Pi1_out1 ? 1'b1 :
1'b0);
// <S25>/Two Pi3
assign Two_Pi3_out1 = 32'sb00000000000000000000000000000000;
// <S25>/Relational Operator1
assign Relational_Operator1_relop1 = (x < Two_Pi3_out1 ? 1'b1 :
1'b0);
// <S25>/Two Pi2
assign Two_Pi2_out1 = 32'sb00110010010000111111011010101001;
// <S25>/Add2
assign Add2_out1 = x + Two_Pi2_out1;
// <S25>/Switch1
assign Switch1_out1 = (Relational_Operator1_relop1 == 1'b0 ? x :
Add2_out1);
// <S25>/Two Pi
assign Two_Pi_out1 = 32'sb00110010010000111111011010101001;
// <S25>/Add1
//
// <S25>/Position_Hi_Data_Type
assign Add1_out1 = x - Two_Pi_out1;
// <S25>/Switch
assign Switch_out1 = (Relational_Operator_relop1 == 1'b0 ? Switch1_out1 :
Add1_out1);
assign wrap = Switch_out1;
endmodule // controllerHdl_Wrap_2pi_Once

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Wrap_NegPi_To_Pi.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Wrap_NegPi_To_Pi
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Calculate_Rotor_Velocity/Wrap_NegPi_To_Pi
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Wrap_NegPi_To_Pi
(
position,
wrap
);
input signed [18:0] position; // sfix19_En14
output signed [17:0] wrap; // sfix18_En15
wire signed [18:0] Constant1_out1; // sfix19_En14
wire signed [18:0] Constant_out1; // sfix19_En14
wire Relational_Operator1_relop1;
wire position_less_than_pi;
wire signed [19:0] Data_Type_Conversion_out1; // sfix20_En14
wire signed [18:0] Constant3_out1; // sfix19_En14
wire Relational_Operator_relop1;
wire position_greater_than_pi;
wire signed [19:0] Add1_add_cast; // sfix20_En14
wire signed [19:0] Add1_add_cast_1; // sfix20_En14
wire signed [19:0] wrap_position_less_than_neg_pi; // sfix20_En14
wire signed [19:0] Switch2_out1; // sfix20_En14
wire signed [18:0] Constant2_out1; // sfix19_En14
wire signed [19:0] Add_sub_cast; // sfix20_En14
wire signed [19:0] Add_sub_cast_1; // sfix20_En14
wire signed [19:0] wrap_position_greater_than_pi; // sfix20_En14
wire signed [19:0] Switch1_out1; // sfix20_En14
wire signed [17:0] Angle_Data_Type_out1; // sfix18_En15
// Wrap Angle
// <S9>/Constant1
assign Constant1_out1 = 19'sb0001100100100010000;
// <S9>/Constant
assign Constant_out1 = 19'sb1110011011011110000;
// <S9>/Relational Operator1
assign Relational_Operator1_relop1 = (position < Constant_out1 ? 1'b1 :
1'b0);
assign position_less_than_pi = Relational_Operator1_relop1;
// <S9>/Data Type Conversion
assign Data_Type_Conversion_out1 = position;
// <S9>/Constant3
assign Constant3_out1 = 19'sb0011001001000100000;
// <S9>/Relational Operator
assign Relational_Operator_relop1 = (position >= Constant1_out1 ? 1'b1 :
1'b0);
assign position_greater_than_pi = Relational_Operator_relop1;
// <S9>/Add1
assign Add1_add_cast = position;
assign Add1_add_cast_1 = Constant3_out1;
assign wrap_position_less_than_neg_pi = Add1_add_cast + Add1_add_cast_1;
// <S9>/Switch2
assign Switch2_out1 = (position_less_than_pi == 1'b0 ? Data_Type_Conversion_out1 :
wrap_position_less_than_neg_pi);
// <S9>/Constant2
assign Constant2_out1 = 19'sb0011001001000100000;
// <S9>/Add
assign Add_sub_cast = position;
assign Add_sub_cast_1 = Constant2_out1;
assign wrap_position_greater_than_pi = Add_sub_cast - Add_sub_cast_1;
// <S9>/Switch1
assign Switch1_out1 = (position_greater_than_pi == 1'b0 ? Switch2_out1 :
wrap_position_greater_than_pi);
// <S9>/Angle_Data_Type
assign Angle_Data_Type_out1 = {Switch1_out1[16:0], 1'b0};
assign wrap = Angle_Data_Type_out1;
endmodule // controllerHdl_Wrap_NegPi_To_Pi

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_controllerHdl.v
// Created: 2014-08-27 21:15:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_controllerHdl
// Source Path: controllerHdl
// Hierarchy Level: 1
//
// Simulink model description for controllerHdl:
//
// Controller Algorithm for Permanent Magnet Synchronous Machine
//
// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control.
// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals.
// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages.
//
// Simulink subsystem description for controllerHdl:
//
// Controller Algorithm for Permanent Magnet Synchronous Machine
//
// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control.
// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals.
// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages.
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_controllerHdl
(
CLK_IN,
reset,
enb_1_2000_0,
adc_current_0,
adc_current_1,
encoder_valid,
encoder_count,
controller_mode,
command,
param_velocity_p_gain,
param_velocity_i_gain,
param_current_p_gain,
param_current_i_gain,
param_open_loop_bias,
param_open_loop_scalar,
param_encoder_zero_offset,
pwm_compare_0,
pwm_compare_1,
pwm_compare_2,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2,
phase_currents_0,
phase_currents_1,
rotor_position,
electrical_position,
rotor_velocity,
dq_currents_0,
dq_currents_1,
electrical_position_err_reg
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input signed [17:0] adc_current_0; // sfix18_En17
input signed [17:0] adc_current_1; // sfix18_En17
input encoder_valid;
input [15:0] encoder_count; // uint16
input [1:0] controller_mode; // ufix2
input signed [17:0] command; // sfix18_En8
input signed [17:0] param_velocity_p_gain; // sfix18_En16
input signed [17:0] param_velocity_i_gain; // sfix18_En15
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
input signed [17:0] param_open_loop_bias; // sfix18_En14
input signed [17:0] param_open_loop_scalar; // sfix18_En16
input signed [17:0] param_encoder_zero_offset; // sfix18_En14
output [15:0] pwm_compare_0; // uint16
output [15:0] pwm_compare_1; // uint16
output [15:0] pwm_compare_2; // uint16
output signed [19:0] phase_voltages_0; // sfix20_En12
output signed [19:0] phase_voltages_1; // sfix20_En12
output signed [19:0] phase_voltages_2; // sfix20_En12
output signed [17:0] phase_currents_0; // sfix18_En15
output signed [17:0] phase_currents_1; // sfix18_En15
output signed [17:0] rotor_position; // sfix18_En14
output signed [17:0] electrical_position; // sfix18_En14
output signed [17:0] rotor_velocity; // sfix18_En8
output signed [17:0] dq_currents_0; // sfix18_En15
output signed [17:0] dq_currents_1; // sfix18_En15
output signed [18:0] electrical_position_err_reg; // sfix19_En14
wire Encoder_To_Position_And_Velocity_out1;
wire signed [17:0] Encoder_To_Position_And_Velocity_out2; // sfix18_En14
wire signed [17:0] Encoder_To_Position_And_Velocity_out3; // sfix18_En14
wire signed [17:0] Encoder_To_Position_And_Velocity_out4; // sfix18_En8
wire signed [17:0] phase_currents_0_1; // sfix18_En15
wire signed [17:0] phase_currents_1_1; // sfix18_En15
wire signed [17:0] phase_currents [0:1]; // sfix18_En15 [2]
wire signed [19:0] Field_Oriented_Control_out1_0; // sfix20_En12
wire signed [19:0] Field_Oriented_Control_out1_1; // sfix20_En12
wire signed [19:0] Field_Oriented_Control_out1_2; // sfix20_En12
wire signed [17:0] Field_Oriented_Control_out2_0; // sfix18_En15
wire signed [17:0] Field_Oriented_Control_out2_1; // sfix18_En15
wire signed [17:0] Field_Oriented_Control_out3; // sfix18_En14
wire [15:0] pwm_compare_0_1; // uint16
wire [15:0] pwm_compare_1_1; // uint16
wire [15:0] pwm_compare_2_1; // uint16
wire [15:0] pwm_compare [0:2]; // uint16 [3]
wire signed [18:0] Add_sub_cast; // sfix19_En14
wire signed [18:0] Add_sub_cast_1; // sfix19_En14
wire signed [18:0] Add_out1; // sfix19_En14
wire signed [18:0] MATLAB_Function_out1; // sfix19_En14
// Controller HDL
//
// Copyright 2013 The MathWorks, Inc.
// <Root>/Encoder_To_Position_And_Velocity
controllerHdl_Encoder_To_Position_And_Velocity u_Encoder_To_Position_And_Velocity (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.encoder_valid(encoder_valid),
.encoder_counter(encoder_count), // uint16
.param_zero_offset(param_encoder_zero_offset), // sfix18_En14
.position_valid(Encoder_To_Position_And_Velocity_out1),
.rotor_position(Encoder_To_Position_And_Velocity_out2), // sfix18_En14
.electrical_position(Encoder_To_Position_And_Velocity_out3), // sfix18_En14
.rotor_velocity(Encoder_To_Position_And_Velocity_out4) // sfix18_En8
);
// <Root>/ADC_Peripheral_To_Phase_Current
controllerHdl_ADC_Peripheral_To_Phase_Current u_ADC_Peripheral_To_Phase_Current (.adc_0(adc_current_0), // sfix18_En17
.adc_1(adc_current_1), // sfix18_En17
.phase_currents_0(phase_currents_0_1), // sfix18_En15
.phase_currents_1(phase_currents_1_1) // sfix18_En15
);
assign phase_currents[0] = phase_currents_0_1;
assign phase_currents[1] = phase_currents_1_1;
// <Root>/Field_Oriented_Control
controllerHdl_Field_Oriented_Control u_Field_Oriented_Control (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.controller_mode(controller_mode), // ufix2
.command(command), // sfix18_En8
.electrical_postion(Encoder_To_Position_And_Velocity_out3), // sfix18_En14
.rotor_velocity(Encoder_To_Position_And_Velocity_out4), // sfix18_En8
.phase_currents_0(phase_currents[0]), // sfix18_En15
.phase_currents_1(phase_currents[1]), // sfix18_En15
.param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16
.param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15
.param_current_p_gain(param_current_p_gain), // sfix18_En10
.param_current_i_gain(param_current_i_gain), // sfix18_En2
.param_open_loop_bias(param_open_loop_bias), // sfix18_En14
.param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16
.phase_voltages_0(Field_Oriented_Control_out1_0), // sfix20_En12
.phase_voltages_1(Field_Oriented_Control_out1_1), // sfix20_En12
.phase_voltages_2(Field_Oriented_Control_out1_2), // sfix20_En12
.dq_current_0(Field_Oriented_Control_out2_0), // sfix18_En15
.dq_current_1(Field_Oriented_Control_out2_1), // sfix18_En15
.electrical_position_ol(Field_Oriented_Control_out3) // sfix18_En14
);
// <Root>/Phase_Voltages_To_Compare_Values
controllerHdl_Phase_Voltages_To_Compare_Values u_Phase_Voltages_To_Compare_Values (.V_0(Field_Oriented_Control_out1_0), // sfix20_En12
.V_1(Field_Oriented_Control_out1_1), // sfix20_En12
.V_2(Field_Oriented_Control_out1_2), // sfix20_En12
.C_0(pwm_compare_0_1), // uint16
.C_1(pwm_compare_1_1), // uint16
.C_2(pwm_compare_2_1) // uint16
);
assign pwm_compare[0] = pwm_compare_0_1;
assign pwm_compare[1] = pwm_compare_1_1;
assign pwm_compare[2] = pwm_compare_2_1;
assign pwm_compare_0 = pwm_compare[0];
assign pwm_compare_1 = pwm_compare[1];
assign pwm_compare_2 = pwm_compare[2];
assign phase_voltages_0 = Field_Oriented_Control_out1_0;
assign phase_voltages_1 = Field_Oriented_Control_out1_1;
assign phase_voltages_2 = Field_Oriented_Control_out1_2;
assign phase_currents_0 = phase_currents[0];
assign phase_currents_1 = phase_currents[1];
assign rotor_position = Encoder_To_Position_And_Velocity_out2;
assign electrical_position = Encoder_To_Position_And_Velocity_out3;
assign rotor_velocity = Encoder_To_Position_And_Velocity_out4;
assign dq_currents_0 = Field_Oriented_Control_out2_0;
assign dq_currents_1 = Field_Oriented_Control_out2_1;
// <Root>/Add
assign Add_sub_cast = Field_Oriented_Control_out3;
assign Add_sub_cast_1 = Encoder_To_Position_And_Velocity_out3;
assign Add_out1 = Add_sub_cast - Add_sub_cast_1;
// <Root>/MATLAB Function
controllerHdl_MATLAB_Function_block3 u_MATLAB_Function (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.u(Add_out1), // sfix19_En14
.y(MATLAB_Function_out1) // sfix19_En14
);
assign electrical_position_err_reg = MATLAB_Function_out1;
endmodule // controllerHdl_controllerHdl

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerPeripheralHdlAdi.v
// Created: 2014-08-28 10:13:59
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
//
// -- -------------------------------------------------------------
// -- Rate and Clocking Details
// -- -------------------------------------------------------------
// Model base rate: 2e-08
// Target subsystem base rate: 2e-08
//
//
// Clock Enable Sample Time
// -- -------------------------------------------------------------
// ce_out_0 2e-08
// ce_out_1 4e-05
// -- -------------------------------------------------------------
//
//
// Output Signal Clock Enable Sample Time
// -- -------------------------------------------------------------
// pwm_a ce_out_0 2e-08
// pwm_b ce_out_0 2e-08
// pwm_c ce_out_0 2e-08
// mon_phase_voltage_a ce_out_1 4e-05
// mon_phase_voltage_b ce_out_1 4e-05
// mon_phase_current_a ce_out_1 4e-05
// mon_phase_current_b ce_out_1 4e-05
// mon_rotor_position ce_out_1 4e-05
// mon_electrical_position ce_out_1 4e-05
// mon_rotor_velocity ce_out_1 4e-05
// mon_d_current ce_out_1 4e-05
// mon_q_current ce_out_1 4e-05
// axi_electrical_pos_err ce_out_1 4e-05
// -- -------------------------------------------------------------
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerPeripheralHdlAdi
// Source Path: controllerPeripheralHdlAdi
// Hierarchy Level: 0
//
// Simulink model description for controllerPeripheralHdlAdi:
//
// Controller Algorithm for Permanent Magnet Synchronous Machine
//
// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control.
// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals.
// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages.
//
// Simulink subsystem description for controllerPeripheralHdlAdi:
//
// Controller Algorithm for Permanent Magnet Synchronous Machine
//
// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control.
// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals.
// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages.
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerPeripheralHdlAdi
(
CLK_IN,
reset,
clk_enable,
adc_current1,
adc_current2,
encoder_a,
encoder_b,
encoder_index,
axi_controller_mode,
axi_command,
axi_velocity_p_gain,
axi_velocity_i_gain,
axi_current_p_gain,
axi_current_i_gain,
axi_open_loop_bias,
axi_open_loop_scalar,
axi_encoder_zero_offset,
ce_out_0,
ce_out_1,
pwm_a,
pwm_b,
pwm_c,
mon_phase_voltage_a,
mon_phase_voltage_b,
mon_phase_current_a,
mon_phase_current_b,
mon_rotor_position,
mon_electrical_position,
mon_rotor_velocity,
mon_d_current,
mon_q_current,
axi_electrical_pos_err
);
input CLK_IN;
input reset;
input clk_enable;
input signed [17:0] adc_current1; // sfix18_En17
input signed [17:0] adc_current2; // sfix18_En17
input encoder_a;
input encoder_b;
input encoder_index;
input [1:0] axi_controller_mode; // ufix2
input signed [17:0] axi_command; // sfix18_En8
input signed [17:0] axi_velocity_p_gain; // sfix18_En16
input signed [17:0] axi_velocity_i_gain; // sfix18_En15
input signed [17:0] axi_current_p_gain; // sfix18_En10
input signed [17:0] axi_current_i_gain; // sfix18_En2
input signed [17:0] axi_open_loop_bias; // sfix18_En14
input signed [17:0] axi_open_loop_scalar; // sfix18_En16
input signed [17:0] axi_encoder_zero_offset; // sfix18_En14
output ce_out_0;
output ce_out_1;
output pwm_a;
output pwm_b;
output pwm_c;
output signed [31:0] mon_phase_voltage_a; // int32
output signed [31:0] mon_phase_voltage_b; // int32
output signed [31:0] mon_phase_current_a; // int32
output signed [31:0] mon_phase_current_b; // int32
output signed [31:0] mon_rotor_position; // int32
output signed [31:0] mon_electrical_position; // int32
output signed [31:0] mon_rotor_velocity; // int32
output signed [31:0] mon_d_current; // int32
output signed [31:0] mon_q_current; // int32
output signed [18:0] axi_electrical_pos_err; // sfix19_En14
wire enb_1_2000_0;
wire enb_1_2000_1;
wire enb;
wire enb_1_1_1;
reg signed [17:0] Delay1_out1; // sfix18_En17
reg signed [17:0] Delay7_out1; // sfix18_En17
wire Rate_Transition2_out1;
wire [15:0] Rate_Transition6_out1; // uint16
wire [15:0] Controller_out1_0; // uint16
wire [15:0] Controller_out1_1; // uint16
wire [15:0] Controller_out1_2; // uint16
wire signed [19:0] Controller_out2_0; // sfix20_En12
wire signed [19:0] Controller_out2_1; // sfix20_En12
wire signed [19:0] Controller_out2_2; // sfix20_En12
wire signed [17:0] Controller_out3_0; // sfix18_En15
wire signed [17:0] Controller_out3_1; // sfix18_En15
wire signed [17:0] Controller_out4; // sfix18_En14
wire signed [17:0] Controller_out5; // sfix18_En14
wire signed [17:0] Controller_out6; // sfix18_En8
wire signed [17:0] Controller_out7_0; // sfix18_En15
wire signed [17:0] Controller_out7_1; // sfix18_En15
wire signed [18:0] Controller_out8; // sfix19_En14
reg Delay2_out1;
reg Delay3_out1;
reg Delay4_out1;
wire Encoder_Peripheral_Hardware_Specification_out1;
wire [15:0] Encoder_Peripheral_Hardware_Specification_out2; // uint16
reg Rate_Transition2_bypass_reg; // ufix1
reg [15:0] Rate_Transition6_bypass_reg; // ufix16
wire [15:0] Controller_out1 [0:2]; // uint16 [3]
reg [15:0] Rate_Transition1_out1 [0:2]; // uint16 [3]
wire PWM_out1_0;
wire PWM_out1_1;
wire PWM_out1_2;
wire [0:2] PWM_out1; // boolean [3]
reg [0:2] Delay5_out1; // boolean [3]
wire signed [19:0] Controller_out2 [0:2]; // sfix20_En12 [3]
wire signed [31:0] Data_Type_Conversion_cast; // sfix32_En12
wire signed [31:0] Data_Type_Conversion_cast_1; // sfix32_En12
wire signed [31:0] Data_Type_Conversion_cast_2; // sfix32_En12
wire signed [31:0] Data_Type_Conversion_out1 [0:2]; // int32 [3]
wire signed [17:0] Controller_out3 [0:1]; // sfix18_En15 [2]
wire signed [31:0] Data_Type_Conversion1_cast; // sfix32_En15
wire signed [31:0] Data_Type_Conversion1_cast_1; // sfix32_En15
wire signed [31:0] Data_Type_Conversion1_out1 [0:1]; // int32 [2]
wire signed [31:0] Data_Type_Conversion2_out1; // int32
wire signed [31:0] Data_Type_Conversion3_out1; // int32
wire signed [31:0] Data_Type_Conversion4_out1; // int32
wire signed [17:0] Controller_out7 [0:1]; // sfix18_En15 [2]
wire signed [31:0] Data_Type_Conversion5_cast; // sfix32_En15
wire signed [31:0] Data_Type_Conversion5_cast_1; // sfix32_En15
wire signed [31:0] Data_Type_Conversion5_out1 [0:1]; // int32 [2]
// Controller Peripheral HDL
// Analog Devices Reference Framework
//
// Copyright 2013 The MathWorks, Inc.
controllerPeripheralHdlAdi_tc u_controllerPeripheralHdlAdi_tc (.CLK_IN(CLK_IN),
.reset(reset),
.clk_enable(clk_enable),
.enb(enb),
.enb_1_1_1(enb_1_1_1),
.enb_1_2000_0(enb_1_2000_0),
.enb_1_2000_1(enb_1_2000_1)
);
// <Root>/Delay1
//
// <Root>/Mux
always @(posedge CLK_IN)
begin : Delay1_process
if (reset == 1'b1) begin
Delay1_out1 <= 18'sb000000000000000000;
end
else if (enb_1_2000_0) begin
Delay1_out1 <= adc_current1;
end
end
// <Root>/Delay7
always @(posedge CLK_IN)
begin : Delay7_process
if (reset == 1'b1) begin
Delay7_out1 <= 18'sb000000000000000000;
end
else if (enb_1_2000_0) begin
Delay7_out1 <= adc_current2;
end
end
// <Root>/Delay2
always @(posedge CLK_IN)
begin : Delay2_process
if (reset == 1'b1) begin
Delay2_out1 <= 1'b0;
end
else if (enb) begin
Delay2_out1 <= encoder_a;
end
end
// <Root>/Delay3
always @(posedge CLK_IN)
begin : Delay3_process
if (reset == 1'b1) begin
Delay3_out1 <= 1'b0;
end
else if (enb) begin
Delay3_out1 <= encoder_b;
end
end
// <Root>/Delay4
always @(posedge CLK_IN)
begin : Delay4_process
if (reset == 1'b1) begin
Delay4_out1 <= 1'b0;
end
else if (enb) begin
Delay4_out1 <= encoder_index;
end
end
// <Root>/Encoder_Peripheral_Hardware_Specification
Encoder_Peripheral_Hardware_Specification u_Encoder_Peripheral_Hardware_Specification (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.a(Delay2_out1),
.b(Delay3_out1),
.index(Delay4_out1),
.valid(Encoder_Peripheral_Hardware_Specification_out1),
.count(Encoder_Peripheral_Hardware_Specification_out2) // uint16
);
// <Root>/Rate Transition2
always @(posedge CLK_IN)
begin : Rate_Transition2_bypass_process
if (reset == 1'b1) begin
Rate_Transition2_bypass_reg <= 1'b0;
end
else if (enb_1_2000_1) begin
Rate_Transition2_bypass_reg <= Encoder_Peripheral_Hardware_Specification_out1;
end
end
assign Rate_Transition2_out1 = (enb_1_2000_1 == 1'b1 ? Encoder_Peripheral_Hardware_Specification_out1 :
Rate_Transition2_bypass_reg);
// <Root>/Rate Transition6
always @(posedge CLK_IN)
begin : Rate_Transition6_bypass_process
if (reset == 1'b1) begin
Rate_Transition6_bypass_reg <= 16'b0000000000000000;
end
else if (enb_1_2000_1) begin
Rate_Transition6_bypass_reg <= Encoder_Peripheral_Hardware_Specification_out2;
end
end
assign Rate_Transition6_out1 = (enb_1_2000_1 == 1'b1 ? Encoder_Peripheral_Hardware_Specification_out2 :
Rate_Transition6_bypass_reg);
// <Root>/Controller
controllerHdl_controllerHdl u_Controller (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.adc_current_0(Delay1_out1), // sfix18_En17
.adc_current_1(Delay7_out1), // sfix18_En17
.encoder_valid(Rate_Transition2_out1),
.encoder_count(Rate_Transition6_out1), // uint16
.controller_mode(axi_controller_mode), // ufix2
.command(axi_command), // sfix18_En8
.param_velocity_p_gain(axi_velocity_p_gain), // sfix18_En16
.param_velocity_i_gain(axi_velocity_i_gain), // sfix18_En15
.param_current_p_gain(axi_current_p_gain), // sfix18_En10
.param_current_i_gain(axi_current_i_gain), // sfix18_En2
.param_open_loop_bias(axi_open_loop_bias), // sfix18_En14
.param_open_loop_scalar(axi_open_loop_scalar), // sfix18_En16
.param_encoder_zero_offset(axi_encoder_zero_offset), // sfix18_En14
.pwm_compare_0(Controller_out1_0), // uint16
.pwm_compare_1(Controller_out1_1), // uint16
.pwm_compare_2(Controller_out1_2), // uint16
.phase_voltages_0(Controller_out2_0), // sfix20_En12
.phase_voltages_1(Controller_out2_1), // sfix20_En12
.phase_voltages_2(Controller_out2_2), // sfix20_En12
.phase_currents_0(Controller_out3_0), // sfix18_En15
.phase_currents_1(Controller_out3_1), // sfix18_En15
.rotor_position(Controller_out4), // sfix18_En14
.electrical_position(Controller_out5), // sfix18_En14
.rotor_velocity(Controller_out6), // sfix18_En8
.dq_currents_0(Controller_out7_0), // sfix18_En15
.dq_currents_1(Controller_out7_1), // sfix18_En15
.electrical_position_err_reg(Controller_out8) // sfix19_En14
);
assign Controller_out1[0] = Controller_out1_0;
assign Controller_out1[1] = Controller_out1_1;
assign Controller_out1[2] = Controller_out1_2;
// <Root>/Rate Transition1
always @(posedge CLK_IN)
begin : Rate_Transition1_process
if (reset == 1'b1) begin
Rate_Transition1_out1[0] <= 16'b0000000000000000;
Rate_Transition1_out1[1] <= 16'b0000000000000000;
Rate_Transition1_out1[2] <= 16'b0000000000000000;
end
else if (enb_1_2000_0) begin
Rate_Transition1_out1[0] <= Controller_out1[0];
Rate_Transition1_out1[1] <= Controller_out1[1];
Rate_Transition1_out1[2] <= Controller_out1[2];
end
end
// <Root>/PWM
PWM u_PWM (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.c_0(Rate_Transition1_out1[0]), // uint16
.c_1(Rate_Transition1_out1[1]), // uint16
.c_2(Rate_Transition1_out1[2]), // uint16
.pwm_0(PWM_out1_0), // boolean
.pwm_1(PWM_out1_1), // boolean
.pwm_2(PWM_out1_2) // boolean
);
assign PWM_out1[0] = PWM_out1_0;
assign PWM_out1[1] = PWM_out1_1;
assign PWM_out1[2] = PWM_out1_2;
// <Root>/Delay5
always @(posedge CLK_IN)
begin : Delay5_process
if (reset == 1'b1) begin
Delay5_out1[0] <= 1'b0;
Delay5_out1[1] <= 1'b0;
Delay5_out1[2] <= 1'b0;
end
else if (enb) begin
Delay5_out1[0] <= PWM_out1[0];
Delay5_out1[1] <= PWM_out1[1];
Delay5_out1[2] <= PWM_out1[2];
end
end
// <Root>/Demux
assign pwm_a = Delay5_out1[0];
assign pwm_b = Delay5_out1[1];
assign pwm_c = Delay5_out1[2];
assign Controller_out2[0] = Controller_out2_0;
assign Controller_out2[1] = Controller_out2_1;
assign Controller_out2[2] = Controller_out2_2;
// <Root>/Data Type Conversion
assign Data_Type_Conversion_cast = Controller_out2[0];
assign Data_Type_Conversion_out1[0] = Data_Type_Conversion_cast;
assign Data_Type_Conversion_cast_1 = Controller_out2[1];
assign Data_Type_Conversion_out1[1] = Data_Type_Conversion_cast_1;
assign Data_Type_Conversion_cast_2 = Controller_out2[2];
assign Data_Type_Conversion_out1[2] = Data_Type_Conversion_cast_2;
// <Root>/Selector
assign mon_phase_voltage_a = Data_Type_Conversion_out1[0];
// <Root>/Selector1
assign mon_phase_voltage_b = Data_Type_Conversion_out1[1];
assign Controller_out3[0] = Controller_out3_0;
assign Controller_out3[1] = Controller_out3_1;
// <Root>/Data Type Conversion1
assign Data_Type_Conversion1_cast = Controller_out3[0];
assign Data_Type_Conversion1_out1[0] = Data_Type_Conversion1_cast;
assign Data_Type_Conversion1_cast_1 = Controller_out3[1];
assign Data_Type_Conversion1_out1[1] = Data_Type_Conversion1_cast_1;
// <Root>/Demux2
assign mon_phase_current_a = Data_Type_Conversion1_out1[0];
assign mon_phase_current_b = Data_Type_Conversion1_out1[1];
// <Root>/Data Type Conversion2
assign Data_Type_Conversion2_out1 = Controller_out4;
assign mon_rotor_position = Data_Type_Conversion2_out1;
// <Root>/Data Type Conversion3
assign Data_Type_Conversion3_out1 = Controller_out5;
assign mon_electrical_position = Data_Type_Conversion3_out1;
// <Root>/Data Type Conversion4
assign Data_Type_Conversion4_out1 = Controller_out6;
assign mon_rotor_velocity = Data_Type_Conversion4_out1;
assign Controller_out7[0] = Controller_out7_0;
assign Controller_out7[1] = Controller_out7_1;
// <Root>/Data Type Conversion5
assign Data_Type_Conversion5_cast = Controller_out7[0];
assign Data_Type_Conversion5_out1[0] = Data_Type_Conversion5_cast;
assign Data_Type_Conversion5_cast_1 = Controller_out7[1];
assign Data_Type_Conversion5_out1[1] = Data_Type_Conversion5_cast_1;
// <Root>/Demux1
assign mon_d_current = Data_Type_Conversion5_out1[0];
assign mon_q_current = Data_Type_Conversion5_out1[1];
assign axi_electrical_pos_err = Controller_out8;
assign ce_out_0 = enb_1_1_1;
assign ce_out_1 = enb_1_2000_1;
endmodule // controllerPeripheralHdlAdi

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerPeripheralHdlAdi_tc.v
// Created: 2014-08-28 10:13:59
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerPeripheralHdlAdi_tc
// Source Path: controllerPeripheralHdlAdi_tc
// Hierarchy Level: 1
//
// Master clock enable input: clk_enable
//
// enb : identical to clk_enable
// enb_1_1_1 : identical to clk_enable
// enb_1_2000_0: 2000x slower than clk_enable with last phase
// enb_1_2000_1: 2000x slower than clk_enable with phase 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerPeripheralHdlAdi_tc
(
CLK_IN,
reset,
clk_enable,
enb,
enb_1_1_1,
enb_1_2000_0,
enb_1_2000_1
);
input CLK_IN;
input reset;
input clk_enable;
output enb;
output enb_1_1_1;
output enb_1_2000_0;
output enb_1_2000_1;
reg [10:0] count2000; // ufix11
wire phase_all;
reg phase_0;
wire phase_0_tmp;
reg phase_1;
wire phase_1_tmp;
always @ ( posedge CLK_IN)
begin: Counter2000
if (reset == 1'b1) begin
count2000 <= 11'b00000000001;
end
else begin
if (clk_enable == 1'b1) begin
if (count2000 == 11'b11111001111) begin
count2000 <= 11'b00000000000;
end
else begin
count2000 <= count2000 + 1;
end
end
end
end // Counter2000
assign phase_all = clk_enable? 1 : 0;
always @ ( posedge CLK_IN)
begin: temp_process1
if (reset == 1'b1) begin
phase_0 <= 1'b0;
end
else begin
if (clk_enable == 1'b1) begin
phase_0 <= phase_0_tmp;
end
end
end // temp_process1
assign phase_0_tmp = (count2000 == 11'b11111001111 && clk_enable == 1'b1)? 1 : 0;
always @ ( posedge CLK_IN)
begin: temp_process2
if (reset == 1'b1) begin
phase_1 <= 1'b1;
end
else begin
if (clk_enable == 1'b1) begin
phase_1 <= phase_1_tmp;
end
end
end // temp_process2
assign phase_1_tmp = (count2000 == 11'b00000000000 && clk_enable == 1'b1)? 1 : 0;
assign enb = phase_all & clk_enable;
assign enb_1_1_1 = phase_all & clk_enable;
assign enb_1_2000_0 = phase_0 & clk_enable;
assign enb_1_2000_1 = phase_1 & clk_enable;
endmodule // controllerPeripheralHdlAdi_tc

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create controllerperipheralhdladi_pcore
adi_ip_files controllerperipheralhdladi_pcore [list \
"velocityControlHdl_Clamp.v" \
"velocityControlHdl_Convert_Data_Type1.v" \
"velocityControlHdl_Maintain_Range.v" \
"velocityControlHdl_Dynamic_Saturation.v" \
"velocityControlHdl_PI_Sat.v" \
"velocityControlHdl_Reset_Delay.v" \
"velocityControlHdl_Control_Current.v" \
"velocityControlHdl_Clamp_block.v" \
"velocityControlHdl_Convert_Data_Type1_block.v" \
"velocityControlHdl_Maintain_Range_block.v" \
"velocityControlHdl_Dynamic_Saturation_block.v" \
"velocityControlHdl_PI_Sat_block.v" \
"velocityControlHdl_Reset_Delay_block.v" \
"velocityControlHdl_Control_Current1.v" \
"velocityControlHdl_Control_DQ_Currents.v" \
"velocityControlHdl_Clamp_block1.v" \
"velocityControlHdl_Convert_Data_Type.v" \
"velocityControlHdl_Maintain_Range_block1.v" \
"velocityControlHdl_Dynamic_Saturation_block1.v" \
"velocityControlHdl_PI_Sat_block1.v" \
"velocityControlHdl_Reset_Delay_block1.v" \
"velocityControlHdl_Rotor_Velocity_Control.v" \
"velocityControlHdl_Control_Velocity.v" \
"velocityControlHdl_Complex_Multiply.v" \
"velocityControlHdl_Convert_Data_Type_block.v" \
"velocityControlHdl_MATLAB_Function.v" \
"velocityControlHdl_Mark_Extract_Bits.v" \
"velocityControlHdl_MATLAB_Function_block.v" \
"velocityControlHdl_Mark_Extract_Bits1.v" \
"velocityControlHdl_Sin_Cos1.v" \
"velocityControlHdl_Double_Range.v" \
"velocityControlHdl_MinMax.v" \
"velocityControlHdl_MinMax1.v" \
"velocityControlHdl_Space_Vector_Modulation.v" \
"velocityControlHdl_Clarke_Transform.v" \
"velocityControlHdl_Park_Transform.v" \
"velocityControlHdl_Transform_ABC_to_dq.v" \
"velocityControlHdl_Inverse_Clarke_Transform.v" \
"velocityControlHdl_Convert_Data_Type_block1.v" \
"velocityControlHdl_Convert_Data_Type1_block1.v" \
"velocityControlHdl_Inverse_Park_Transform.v" \
"velocityControlHdl_Transform_dq_to_ABC.v" \
"velocityControlHdl_velocityControlHdl.v" \
"controllerHdl_ADC_Peripheral_To_Phase_Current.v" \
"controllerHdl_Wrap_NegPi_To_Pi.v" \
"controllerHdl_Calculate_Rotor_Velocity.v" \
"controllerHdl_Wrap_2pi.v" \
"controllerHdl_Encoder_To_Rotor_Position.v" \
"controllerHdl_MATLAB_Function.v" \
"controllerHdl_Mark_Extract_Bits.v" \
"controllerHdl_Mod_2pi_Scale_And_Bit_Slice.v" \
"controllerHdl_Rotor_To_Electrical_Position.v" \
"controllerHdl_Encoder_To_Position_And_Velocity.v" \
"controllerHdl_Reset_Delay.v" \
"controllerHdl_Wrap_2pi_Once.v" \
"controllerHdl_Electrical_Velocity_To_Position.v" \
"controllerHdl_Convert_Data_Type.v" \
"controllerHdl_Double_Range.v" \
"controllerHdl_Frequency_To_Volts.v" \
"controllerHdl_Reset_Delay_block.v" \
"controllerHdl_Detect_Change.v" \
"controllerHdl_Set_Acceleration.v" \
"controllerHdl_Rotor_Acceleration_To_Velocity.v" \
"controllerHdl_Convert_Data_Type_block.v" \
"controllerHdl_Rotor_To_Electical_Velocity.v" \
"controllerHdl_Generate_Position_And_Voltage_Ramp.v" \
"controllerHdl_Complex_Multiply.v" \
"controllerHdl_Convert_Data_Type_block1.v" \
"controllerHdl_MATLAB_Function_block.v" \
"controllerHdl_Mark_Extract_Bits_block.v" \
"controllerHdl_MATLAB_Function_block1.v" \
"controllerHdl_Mark_Extract_Bits1.v" \
"controllerHdl_Sin_Cos.v" \
"controllerHdl_Inverse_Clarke_Transform.v" \
"controllerHdl_Convert_Data_Type_block2.v" \
"controllerHdl_Convert_Data_Type1.v" \
"controllerHdl_Inverse_Park_Transform.v" \
"controllerHdl_Transform_dq_to_ABC.v" \
"controllerHdl_Open_Loop_Control.v" \
"controllerHdl_StandBy.v" \
"controllerHdl_MATLAB_Function_block2.v" \
"controllerHdl_Field_Oriented_Control.v" \
"controllerHdl_Phase_Voltages_To_Compare_Values.v" \
"controllerHdl_MATLAB_Function_block3.v" \
"controllerHdl_controllerHdl.v" \
"Count_Up_Down.v" \
"Debounce_A.v" \
"Debounce_B.v" \
"Debounce_Index.v" \
"Detect_Change_To_One.v" \
"Latch_Index_Pulse.v" \
"Select_AB.v" \
"Update_Count_From_AB.v" \
"Encoder_Peripheral_Hardware_Specification.v" \
"Chart.v" \
"PWM.v" \
"controllerPeripheralHdlAdi_tc.v" \
"controllerPeripheralHdlAdi.v" \
"controllerperipheralhdladi_pcore_dut.v" \
"controllerperipheralhdladi_pcore_axi_lite_module.v" \
"controllerperipheralhdladi_pcore_addr_decoder.v" \
"controllerperipheralhdladi_pcore_axi_lite.v" \
"controllerperipheralhdladi_pcore.v" ]
adi_ip_properties controllerperipheralhdladi_pcore
ipx::save_core [ipx::current_core]

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore.v
// Created: 2014-08-28 10:14:05
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
//
// -- -------------------------------------------------------------
// -- Rate and Clocking Details
// -- -------------------------------------------------------------
// Model base rate: -1
// Target subsystem base rate: -1
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerperipheralhdladi_pcore
// Source Path: controllerperipheralhdladi_pcore
// Hierarchy Level: 0
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerperipheralhdladi_pcore
(
IPCORE_CLK,
IPCORE_RESETN,
adc_current1,
adc_current2,
encoder_a,
encoder_b,
encoder_index,
AXI_Lite_ACLK,
AXI_Lite_ARESETN,
AXI_Lite_AWADDR,
AXI_Lite_AWVALID,
AXI_Lite_WDATA,
AXI_Lite_WSTRB,
AXI_Lite_WVALID,
AXI_Lite_BREADY,
AXI_Lite_ARADDR,
AXI_Lite_ARVALID,
AXI_Lite_RREADY,
pwm_a,
pwm_b,
pwm_c,
mon_phase_voltage_a,
mon_phase_voltage_b,
mon_phase_current_a,
mon_phase_current_b,
mon_rotor_position,
mon_electrical_position,
mon_rotor_velocity,
mon_d_current,
mon_q_current,
AXI_Lite_AWREADY,
AXI_Lite_WREADY,
AXI_Lite_BRESP,
AXI_Lite_BVALID,
AXI_Lite_ARREADY,
AXI_Lite_RDATA,
AXI_Lite_RRESP,
AXI_Lite_RVALID
);
input IPCORE_CLK; // ufix1
input IPCORE_RESETN; // ufix1
input [17:0] adc_current1; // ufix18
input [17:0] adc_current2; // ufix18
input encoder_a; // ufix1
input encoder_b; // ufix1
input encoder_index; // ufix1
input AXI_Lite_ACLK; // ufix1
input AXI_Lite_ARESETN; // ufix1
input [31:0] AXI_Lite_AWADDR; // ufix32
input AXI_Lite_AWVALID; // ufix1
input [31:0] AXI_Lite_WDATA; // ufix32
input [3:0] AXI_Lite_WSTRB; // ufix4
input AXI_Lite_WVALID; // ufix1
input AXI_Lite_BREADY; // ufix1
input [31:0] AXI_Lite_ARADDR; // ufix32
input AXI_Lite_ARVALID; // ufix1
input AXI_Lite_RREADY; // ufix1
output pwm_a; // ufix1
output pwm_b; // ufix1
output pwm_c; // ufix1
output [31:0] mon_phase_voltage_a; // ufix32
output [31:0] mon_phase_voltage_b; // ufix32
output [31:0] mon_phase_current_a; // ufix32
output [31:0] mon_phase_current_b; // ufix32
output [31:0] mon_rotor_position; // ufix32
output [31:0] mon_electrical_position; // ufix32
output [31:0] mon_rotor_velocity; // ufix32
output [31:0] mon_d_current; // ufix32
output [31:0] mon_q_current; // ufix32
output AXI_Lite_AWREADY; // ufix1
output AXI_Lite_WREADY; // ufix1
output [1:0] AXI_Lite_BRESP; // ufix2
output AXI_Lite_BVALID; // ufix1
output AXI_Lite_ARREADY; // ufix1
output [31:0] AXI_Lite_RDATA; // ufix32
output [1:0] AXI_Lite_RRESP; // ufix2
output AXI_Lite_RVALID; // ufix1
wire reset;
wire reset_cm; // ufix1
wire reset_internal; // ufix1
wire signed [18:0] axi_electrical_pos_err_sig; // sfix19_En14
wire dut_enable; // ufix1
wire [1:0] axi_controller_mode_sig; // ufix2
wire signed [17:0] axi_command_sig; // sfix18_En8
wire signed [17:0] axi_velocity_p_gain_sig; // sfix18_En16
wire signed [17:0] axi_velocity_i_gain_sig; // sfix18_En15
wire signed [17:0] axi_current_p_gain_sig; // sfix18_En10
wire signed [17:0] axi_current_i_gain_sig; // sfix18_En2
wire signed [17:0] axi_open_loop_bias_sig; // sfix18_En14
wire signed [17:0] axi_open_loop_scalar_sig; // sfix18_En16
wire signed [17:0] axi_encoder_zero_offset_sig; // sfix18_En14
wire ce_out_0_sig; // ufix1
wire ce_out_1_sig; // ufix1
wire pwm_a_sig; // ufix1
wire pwm_b_sig; // ufix1
wire pwm_c_sig; // ufix1
wire signed [31:0] mon_phase_voltage_a_sig; // sfix32
wire signed [31:0] mon_phase_voltage_b_sig; // sfix32
wire signed [31:0] mon_phase_current_a_sig; // sfix32
wire signed [31:0] mon_phase_current_b_sig; // sfix32
wire signed [31:0] mon_rotor_position_sig; // sfix32
wire signed [31:0] mon_electrical_position_sig; // sfix32
wire signed [31:0] mon_rotor_velocity_sig; // sfix32
wire signed [31:0] mon_d_current_sig; // sfix32
wire signed [31:0] mon_q_current_sig; // sfix32
assign reset_cm = ~ IPCORE_RESETN;
assign reset = reset_cm | reset_internal;
controllerperipheralhdladi_pcore_axi_lite u_controllerperipheralhdladi_pcore_axi_lite_inst (.reset(reset),
.AXI_Lite_ACLK(AXI_Lite_ACLK), // ufix1
.AXI_Lite_ARESETN(AXI_Lite_ARESETN), // ufix1
.AXI_Lite_AWADDR(AXI_Lite_AWADDR), // ufix32
.AXI_Lite_AWVALID(AXI_Lite_AWVALID), // ufix1
.AXI_Lite_WDATA(AXI_Lite_WDATA), // ufix32
.AXI_Lite_WSTRB(AXI_Lite_WSTRB), // ufix4
.AXI_Lite_WVALID(AXI_Lite_WVALID), // ufix1
.AXI_Lite_BREADY(AXI_Lite_BREADY), // ufix1
.AXI_Lite_ARADDR(AXI_Lite_ARADDR), // ufix32
.AXI_Lite_ARVALID(AXI_Lite_ARVALID), // ufix1
.AXI_Lite_RREADY(AXI_Lite_RREADY), // ufix1
.read_axi_electrical_pos_err(axi_electrical_pos_err_sig), // sfix19_En14
.AXI_Lite_AWREADY(AXI_Lite_AWREADY), // ufix1
.AXI_Lite_WREADY(AXI_Lite_WREADY), // ufix1
.AXI_Lite_BRESP(AXI_Lite_BRESP), // ufix2
.AXI_Lite_BVALID(AXI_Lite_BVALID), // ufix1
.AXI_Lite_ARREADY(AXI_Lite_ARREADY), // ufix1
.AXI_Lite_RDATA(AXI_Lite_RDATA), // ufix32
.AXI_Lite_RRESP(AXI_Lite_RRESP), // ufix2
.AXI_Lite_RVALID(AXI_Lite_RVALID), // ufix1
.write_axi_enable(dut_enable), // ufix1
.write_axi_controller_mode(axi_controller_mode_sig), // ufix2
.write_axi_command(axi_command_sig), // sfix18_En8
.write_axi_velocity_p_gain(axi_velocity_p_gain_sig), // sfix18_En16
.write_axi_velocity_i_gain(axi_velocity_i_gain_sig), // sfix18_En15
.write_axi_current_p_gain(axi_current_p_gain_sig), // sfix18_En10
.write_axi_current_i_gain(axi_current_i_gain_sig), // sfix18_En2
.write_axi_open_loop_bias(axi_open_loop_bias_sig), // sfix18_En14
.write_axi_open_loop_scalar(axi_open_loop_scalar_sig), // sfix18_En16
.write_axi_encoder_zero_offset(axi_encoder_zero_offset_sig), // sfix18_En14
.reset_internal(reset_internal) // ufix1
);
controllerperipheralhdladi_pcore_dut u_controllerperipheralhdladi_pcore_dut_inst (.CLK_IN(IPCORE_CLK), // ufix1
.reset(reset),
.dut_enable(dut_enable), // ufix1
.adc_current1(adc_current1), // sfix18_En17
.adc_current2(adc_current2), // sfix18_En17
.encoder_a(encoder_a), // ufix1
.encoder_b(encoder_b), // ufix1
.encoder_index(encoder_index), // ufix1
.axi_controller_mode(axi_controller_mode_sig), // ufix2
.axi_command(axi_command_sig), // sfix18_En8
.axi_velocity_p_gain(axi_velocity_p_gain_sig), // sfix18_En16
.axi_velocity_i_gain(axi_velocity_i_gain_sig), // sfix18_En15
.axi_current_p_gain(axi_current_p_gain_sig), // sfix18_En10
.axi_current_i_gain(axi_current_i_gain_sig), // sfix18_En2
.axi_open_loop_bias(axi_open_loop_bias_sig), // sfix18_En14
.axi_open_loop_scalar(axi_open_loop_scalar_sig), // sfix18_En16
.axi_encoder_zero_offset(axi_encoder_zero_offset_sig), // sfix18_En14
.ce_out_0(ce_out_0_sig), // ufix1
.ce_out_1(ce_out_1_sig), // ufix1
.pwm_a(pwm_a_sig), // ufix1
.pwm_b(pwm_b_sig), // ufix1
.pwm_c(pwm_c_sig), // ufix1
.mon_phase_voltage_a(mon_phase_voltage_a_sig), // sfix32
.mon_phase_voltage_b(mon_phase_voltage_b_sig), // sfix32
.mon_phase_current_a(mon_phase_current_a_sig), // sfix32
.mon_phase_current_b(mon_phase_current_b_sig), // sfix32
.mon_rotor_position(mon_rotor_position_sig), // sfix32
.mon_electrical_position(mon_electrical_position_sig), // sfix32
.mon_rotor_velocity(mon_rotor_velocity_sig), // sfix32
.mon_d_current(mon_d_current_sig), // sfix32
.mon_q_current(mon_q_current_sig), // sfix32
.axi_electrical_pos_err(axi_electrical_pos_err_sig) // sfix19_En14
);
assign pwm_a = pwm_a_sig;
assign pwm_b = pwm_b_sig;
assign pwm_c = pwm_c_sig;
assign mon_phase_voltage_a = mon_phase_voltage_a_sig;
assign mon_phase_voltage_b = mon_phase_voltage_b_sig;
assign mon_phase_current_a = mon_phase_current_a_sig;
assign mon_phase_current_b = mon_phase_current_b_sig;
assign mon_rotor_position = mon_rotor_position_sig;
assign mon_electrical_position = mon_electrical_position_sig;
assign mon_rotor_velocity = mon_rotor_velocity_sig;
assign mon_d_current = mon_d_current_sig;
assign mon_q_current = mon_q_current_sig;
endmodule // controllerperipheralhdladi_pcore

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore_addr_decoder.v
// Created: 2014-08-28 10:14:05
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerperipheralhdladi_pcore_addr_decoder
// Source Path: controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite/controllerperipheralhdladi_pcore_addr_decoder
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerperipheralhdladi_pcore_addr_decoder
(
CLK_IN,
reset,
data_write,
addr_sel,
wr_enb,
rd_enb,
read_axi_electrical_pos_err,
data_read,
write_axi_enable,
write_axi_controller_mode,
write_axi_command,
write_axi_velocity_p_gain,
write_axi_velocity_i_gain,
write_axi_current_p_gain,
write_axi_current_i_gain,
write_axi_open_loop_bias,
write_axi_open_loop_scalar,
write_axi_encoder_zero_offset
);
input CLK_IN;
input reset;
input [31:0] data_write; // ufix32
input [13:0] addr_sel; // ufix14
input wr_enb; // ufix1
input rd_enb; // ufix1
input signed [18:0] read_axi_electrical_pos_err; // sfix19_En14
output [31:0] data_read; // ufix32
output write_axi_enable; // ufix1
output [1:0] write_axi_controller_mode; // ufix2
output signed [17:0] write_axi_command; // sfix18_En8
output signed [17:0] write_axi_velocity_p_gain; // sfix18_En16
output signed [17:0] write_axi_velocity_i_gain; // sfix18_En15
output signed [17:0] write_axi_current_p_gain; // sfix18_En10
output signed [17:0] write_axi_current_i_gain; // sfix18_En2
output signed [17:0] write_axi_open_loop_bias; // sfix18_En14
output signed [17:0] write_axi_open_loop_scalar; // sfix18_En16
output signed [17:0] write_axi_encoder_zero_offset; // sfix18_En14
wire enb;
wire decode_sel_axi_electrical_pos_err; // ufix1
wire const_1; // ufix1
wire [31:0] const_z; // ufix32
reg signed [18:0] read_reg_axi_electrical_pos_err; // sfix19_En14
wire [31:0] data_in_axi_electrical_pos_err; // ufix32
wire [31:0] decode_rd_axi_electrical_pos_err; // ufix32
wire data_in_axi_enable; // ufix1
wire decode_sel_axi_enable; // ufix1
wire reg_enb_axi_enable; // ufix1
reg write_reg_axi_enable; // ufix1
wire [1:0] data_in_axi_controller_mode; // ufix2
wire decode_sel_axi_controller_mode; // ufix1
wire reg_enb_axi_controller_mode; // ufix1
reg [1:0] write_reg_axi_controller_mode; // ufix2
wire signed [17:0] data_in_axi_command; // sfix18_En8
wire decode_sel_axi_command; // ufix1
wire reg_enb_axi_command; // ufix1
reg signed [17:0] write_reg_axi_command; // sfix18_En8
wire signed [17:0] data_in_axi_velocity_p_gain; // sfix18_En16
wire decode_sel_axi_velocity_p_gain; // ufix1
wire reg_enb_axi_velocity_p_gain; // ufix1
reg signed [17:0] write_reg_axi_velocity_p_gain; // sfix18_En16
wire signed [17:0] data_in_axi_velocity_i_gain; // sfix18_En15
wire decode_sel_axi_velocity_i_gain; // ufix1
wire reg_enb_axi_velocity_i_gain; // ufix1
reg signed [17:0] write_reg_axi_velocity_i_gain; // sfix18_En15
wire signed [17:0] data_in_axi_current_p_gain; // sfix18_En10
wire decode_sel_axi_current_p_gain; // ufix1
wire reg_enb_axi_current_p_gain; // ufix1
reg signed [17:0] write_reg_axi_current_p_gain; // sfix18_En10
wire signed [17:0] data_in_axi_current_i_gain; // sfix18_En2
wire decode_sel_axi_current_i_gain; // ufix1
wire reg_enb_axi_current_i_gain; // ufix1
reg signed [17:0] write_reg_axi_current_i_gain; // sfix18_En2
wire signed [17:0] data_in_axi_open_loop_bias; // sfix18_En14
wire decode_sel_axi_open_loop_bias; // ufix1
wire reg_enb_axi_open_loop_bias; // ufix1
reg signed [17:0] write_reg_axi_open_loop_bias; // sfix18_En14
wire signed [17:0] data_in_axi_open_loop_scalar; // sfix18_En16
wire decode_sel_axi_open_loop_scalar; // ufix1
wire reg_enb_axi_open_loop_scalar; // ufix1
reg signed [17:0] write_reg_axi_open_loop_scalar; // sfix18_En16
wire signed [17:0] data_in_axi_encoder_zero_offset; // sfix18_En14
wire decode_sel_axi_encoder_zero_offset; // ufix1
wire reg_enb_axi_encoder_zero_offset; // ufix1
reg signed [17:0] write_reg_axi_encoder_zero_offset; // sfix18_En14
assign decode_sel_axi_electrical_pos_err = (addr_sel == 14'b00000001001001 ? 1'b1 :
1'b0);
assign const_1 = 1'b1;
assign enb = const_1;
assign const_z = 32'bz;
always @(posedge CLK_IN)
begin : reg_axi_electrical_pos_err_process
if (reset == 1'b1) begin
read_reg_axi_electrical_pos_err <= 19'sb0000000000000000000;
end
else if (enb) begin
read_reg_axi_electrical_pos_err <= read_axi_electrical_pos_err;
end
end
assign data_in_axi_electrical_pos_err = {{13{read_reg_axi_electrical_pos_err[18]}}, read_reg_axi_electrical_pos_err};
assign decode_rd_axi_electrical_pos_err = (decode_sel_axi_electrical_pos_err == 1'b0 ? const_z :
data_in_axi_electrical_pos_err);
assign data_read = decode_rd_axi_electrical_pos_err;
assign data_in_axi_enable = data_write[0];
assign decode_sel_axi_enable = (addr_sel == 14'b00000000000001 ? 1'b1 :
1'b0);
assign reg_enb_axi_enable = decode_sel_axi_enable & wr_enb;
always @(posedge CLK_IN)
begin : reg_axi_enable_process
if (reset == 1'b1) begin
write_reg_axi_enable <= 1'b1;
end
else if (enb && reg_enb_axi_enable) begin
write_reg_axi_enable <= data_in_axi_enable;
end
end
assign write_axi_enable = write_reg_axi_enable;
assign data_in_axi_controller_mode = data_write[1:0];
assign decode_sel_axi_controller_mode = (addr_sel == 14'b00000001000000 ? 1'b1 :
1'b0);
assign reg_enb_axi_controller_mode = decode_sel_axi_controller_mode & wr_enb;
always @(posedge CLK_IN)
begin : reg_axi_controller_mode_process
if (reset == 1'b1) begin
write_reg_axi_controller_mode <= 2'b00;
end
else if (enb && reg_enb_axi_controller_mode) begin
write_reg_axi_controller_mode <= data_in_axi_controller_mode;
end
end
assign write_axi_controller_mode = write_reg_axi_controller_mode;
assign data_in_axi_command = $signed(data_write[17:0]);
assign decode_sel_axi_command = (addr_sel == 14'b00000001000001 ? 1'b1 :
1'b0);
assign reg_enb_axi_command = decode_sel_axi_command & wr_enb;
always @(posedge CLK_IN)
begin : reg_axi_command_process
if (reset == 1'b1) begin
write_reg_axi_command <= 18'sb000000000000000000;
end
else if (enb && reg_enb_axi_command) begin
write_reg_axi_command <= data_in_axi_command;
end
end
assign write_axi_command = write_reg_axi_command;
assign data_in_axi_velocity_p_gain = $signed(data_write[17:0]);
assign decode_sel_axi_velocity_p_gain = (addr_sel == 14'b00000001000010 ? 1'b1 :
1'b0);
assign reg_enb_axi_velocity_p_gain = decode_sel_axi_velocity_p_gain & wr_enb;
always @(posedge CLK_IN)
begin : reg_axi_velocity_p_gain_process
if (reset == 1'b1) begin
write_reg_axi_velocity_p_gain <= 18'sb000000000000000000;
end
else if (enb && reg_enb_axi_velocity_p_gain) begin
write_reg_axi_velocity_p_gain <= data_in_axi_velocity_p_gain;
end
end
assign write_axi_velocity_p_gain = write_reg_axi_velocity_p_gain;
assign data_in_axi_velocity_i_gain = $signed(data_write[17:0]);
assign decode_sel_axi_velocity_i_gain = (addr_sel == 14'b00000001000011 ? 1'b1 :
1'b0);
assign reg_enb_axi_velocity_i_gain = decode_sel_axi_velocity_i_gain & wr_enb;
always @(posedge CLK_IN)
begin : reg_axi_velocity_i_gain_process
if (reset == 1'b1) begin
write_reg_axi_velocity_i_gain <= 18'sb000000000000000000;
end
else if (enb && reg_enb_axi_velocity_i_gain) begin
write_reg_axi_velocity_i_gain <= data_in_axi_velocity_i_gain;
end
end
assign write_axi_velocity_i_gain = write_reg_axi_velocity_i_gain;
assign data_in_axi_current_p_gain = $signed(data_write[17:0]);
assign decode_sel_axi_current_p_gain = (addr_sel == 14'b00000001000100 ? 1'b1 :
1'b0);
assign reg_enb_axi_current_p_gain = decode_sel_axi_current_p_gain & wr_enb;
always @(posedge CLK_IN)
begin : reg_axi_current_p_gain_process
if (reset == 1'b1) begin
write_reg_axi_current_p_gain <= 18'sb000000000000000000;
end
else if (enb && reg_enb_axi_current_p_gain) begin
write_reg_axi_current_p_gain <= data_in_axi_current_p_gain;
end
end
assign write_axi_current_p_gain = write_reg_axi_current_p_gain;
assign data_in_axi_current_i_gain = $signed(data_write[17:0]);
assign decode_sel_axi_current_i_gain = (addr_sel == 14'b00000001000101 ? 1'b1 :
1'b0);
assign reg_enb_axi_current_i_gain = decode_sel_axi_current_i_gain & wr_enb;
always @(posedge CLK_IN)
begin : reg_axi_current_i_gain_process
if (reset == 1'b1) begin
write_reg_axi_current_i_gain <= 18'sb000000000000000000;
end
else if (enb && reg_enb_axi_current_i_gain) begin
write_reg_axi_current_i_gain <= data_in_axi_current_i_gain;
end
end
assign write_axi_current_i_gain = write_reg_axi_current_i_gain;
assign data_in_axi_open_loop_bias = $signed(data_write[17:0]);
assign decode_sel_axi_open_loop_bias = (addr_sel == 14'b00000001000110 ? 1'b1 :
1'b0);
assign reg_enb_axi_open_loop_bias = decode_sel_axi_open_loop_bias & wr_enb;
always @(posedge CLK_IN)
begin : reg_axi_open_loop_bias_process
if (reset == 1'b1) begin
write_reg_axi_open_loop_bias <= 18'sb000000000000000000;
end
else if (enb && reg_enb_axi_open_loop_bias) begin
write_reg_axi_open_loop_bias <= data_in_axi_open_loop_bias;
end
end
assign write_axi_open_loop_bias = write_reg_axi_open_loop_bias;
assign data_in_axi_open_loop_scalar = $signed(data_write[17:0]);
assign decode_sel_axi_open_loop_scalar = (addr_sel == 14'b00000001000111 ? 1'b1 :
1'b0);
assign reg_enb_axi_open_loop_scalar = decode_sel_axi_open_loop_scalar & wr_enb;
always @(posedge CLK_IN)
begin : reg_axi_open_loop_scalar_process
if (reset == 1'b1) begin
write_reg_axi_open_loop_scalar <= 18'sb000000000000000000;
end
else if (enb && reg_enb_axi_open_loop_scalar) begin
write_reg_axi_open_loop_scalar <= data_in_axi_open_loop_scalar;
end
end
assign write_axi_open_loop_scalar = write_reg_axi_open_loop_scalar;
assign data_in_axi_encoder_zero_offset = $signed(data_write[17:0]);
assign decode_sel_axi_encoder_zero_offset = (addr_sel == 14'b00000001001000 ? 1'b1 :
1'b0);
assign reg_enb_axi_encoder_zero_offset = decode_sel_axi_encoder_zero_offset & wr_enb;
always @(posedge CLK_IN)
begin : reg_axi_encoder_zero_offset_process
if (reset == 1'b1) begin
write_reg_axi_encoder_zero_offset <= 18'sb000000000000000000;
end
else if (enb && reg_enb_axi_encoder_zero_offset) begin
write_reg_axi_encoder_zero_offset <= data_in_axi_encoder_zero_offset;
end
end
assign write_axi_encoder_zero_offset = write_reg_axi_encoder_zero_offset;
endmodule // controllerperipheralhdladi_pcore_addr_decoder

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore_axi_lite.v
// Created: 2014-08-28 10:14:05
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerperipheralhdladi_pcore_axi_lite
// Source Path: controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerperipheralhdladi_pcore_axi_lite
(
reset,
AXI_Lite_ACLK,
AXI_Lite_ARESETN,
AXI_Lite_AWADDR,
AXI_Lite_AWVALID,
AXI_Lite_WDATA,
AXI_Lite_WSTRB,
AXI_Lite_WVALID,
AXI_Lite_BREADY,
AXI_Lite_ARADDR,
AXI_Lite_ARVALID,
AXI_Lite_RREADY,
read_axi_electrical_pos_err,
AXI_Lite_AWREADY,
AXI_Lite_WREADY,
AXI_Lite_BRESP,
AXI_Lite_BVALID,
AXI_Lite_ARREADY,
AXI_Lite_RDATA,
AXI_Lite_RRESP,
AXI_Lite_RVALID,
write_axi_enable,
write_axi_controller_mode,
write_axi_command,
write_axi_velocity_p_gain,
write_axi_velocity_i_gain,
write_axi_current_p_gain,
write_axi_current_i_gain,
write_axi_open_loop_bias,
write_axi_open_loop_scalar,
write_axi_encoder_zero_offset,
reset_internal
);
input reset;
input AXI_Lite_ACLK; // ufix1
input AXI_Lite_ARESETN; // ufix1
input [31:0] AXI_Lite_AWADDR; // ufix32
input AXI_Lite_AWVALID; // ufix1
input [31:0] AXI_Lite_WDATA; // ufix32
input [3:0] AXI_Lite_WSTRB; // ufix4
input AXI_Lite_WVALID; // ufix1
input AXI_Lite_BREADY; // ufix1
input [31:0] AXI_Lite_ARADDR; // ufix32
input AXI_Lite_ARVALID; // ufix1
input AXI_Lite_RREADY; // ufix1
input signed [18:0] read_axi_electrical_pos_err; // sfix19_En14
output AXI_Lite_AWREADY; // ufix1
output AXI_Lite_WREADY; // ufix1
output [1:0] AXI_Lite_BRESP; // ufix2
output AXI_Lite_BVALID; // ufix1
output AXI_Lite_ARREADY; // ufix1
output [31:0] AXI_Lite_RDATA; // ufix32
output [1:0] AXI_Lite_RRESP; // ufix2
output AXI_Lite_RVALID; // ufix1
output write_axi_enable; // ufix1
output [1:0] write_axi_controller_mode; // ufix2
output signed [17:0] write_axi_command; // sfix18_En8
output signed [17:0] write_axi_velocity_p_gain; // sfix18_En16
output signed [17:0] write_axi_velocity_i_gain; // sfix18_En15
output signed [17:0] write_axi_current_p_gain; // sfix18_En10
output signed [17:0] write_axi_current_i_gain; // sfix18_En2
output signed [17:0] write_axi_open_loop_bias; // sfix18_En14
output signed [17:0] write_axi_open_loop_scalar; // sfix18_En16
output signed [17:0] write_axi_encoder_zero_offset; // sfix18_En14
output reset_internal; // ufix1
wire [31:0] top_data_write; // ufix32
wire [13:0] top_addr_sel; // ufix14
wire top_wr_enb; // ufix1
wire top_rd_enb; // ufix1
wire [31:0] top_data_read; // ufix32
wire inst_axi_enable; // ufix1
wire [1:0] inst_axi_controller_mode; // ufix2
wire signed [17:0] inst_axi_command; // sfix18_En8
wire signed [17:0] inst_axi_velocity_p_gain; // sfix18_En16
wire signed [17:0] inst_axi_velocity_i_gain; // sfix18_En15
wire signed [17:0] inst_axi_current_p_gain; // sfix18_En10
wire signed [17:0] inst_axi_current_i_gain; // sfix18_En2
wire signed [17:0] inst_axi_open_loop_bias; // sfix18_En14
wire signed [17:0] inst_axi_open_loop_scalar; // sfix18_En16
wire signed [17:0] inst_axi_encoder_zero_offset; // sfix18_En14
wire top_reset_internal; // ufix1
controllerperipheralhdladi_pcore_addr_decoder u_controllerperipheralhdladi_pcore_addr_decoder_inst (.CLK_IN(AXI_Lite_ACLK), // ufix1
.reset(reset),
.data_write(top_data_write), // ufix32
.addr_sel(top_addr_sel), // ufix14
.wr_enb(top_wr_enb), // ufix1
.rd_enb(top_rd_enb), // ufix1
.read_axi_electrical_pos_err(read_axi_electrical_pos_err), // sfix19_En14
.data_read(top_data_read), // ufix32
.write_axi_enable(inst_axi_enable), // ufix1
.write_axi_controller_mode(inst_axi_controller_mode), // ufix2
.write_axi_command(inst_axi_command), // sfix18_En8
.write_axi_velocity_p_gain(inst_axi_velocity_p_gain), // sfix18_En16
.write_axi_velocity_i_gain(inst_axi_velocity_i_gain), // sfix18_En15
.write_axi_current_p_gain(inst_axi_current_p_gain), // sfix18_En10
.write_axi_current_i_gain(inst_axi_current_i_gain), // sfix18_En2
.write_axi_open_loop_bias(inst_axi_open_loop_bias), // sfix18_En14
.write_axi_open_loop_scalar(inst_axi_open_loop_scalar), // sfix18_En16
.write_axi_encoder_zero_offset(inst_axi_encoder_zero_offset) // sfix18_En14
);
controllerperipheralhdladi_pcore_axi_lite_module u_controllerperipheralhdladi_pcore_axi_lite_module_inst (.CLK_IN(AXI_Lite_ACLK), // ufix1
.AXI_Lite_ARESETN(AXI_Lite_ARESETN), // ufix1
.AXI_Lite_AWADDR(AXI_Lite_AWADDR), // ufix32
.AXI_Lite_AWVALID(AXI_Lite_AWVALID), // ufix1
.AXI_Lite_WDATA(AXI_Lite_WDATA), // ufix32
.AXI_Lite_WSTRB(AXI_Lite_WSTRB), // ufix4
.AXI_Lite_WVALID(AXI_Lite_WVALID), // ufix1
.AXI_Lite_BREADY(AXI_Lite_BREADY), // ufix1
.AXI_Lite_ARADDR(AXI_Lite_ARADDR), // ufix32
.AXI_Lite_ARVALID(AXI_Lite_ARVALID), // ufix1
.AXI_Lite_RREADY(AXI_Lite_RREADY), // ufix1
.data_read(top_data_read), // ufix32
.AXI_Lite_AWREADY(AXI_Lite_AWREADY), // ufix1
.AXI_Lite_WREADY(AXI_Lite_WREADY), // ufix1
.AXI_Lite_BRESP(AXI_Lite_BRESP), // ufix2
.AXI_Lite_BVALID(AXI_Lite_BVALID), // ufix1
.AXI_Lite_ARREADY(AXI_Lite_ARREADY), // ufix1
.AXI_Lite_RDATA(AXI_Lite_RDATA), // ufix32
.AXI_Lite_RRESP(AXI_Lite_RRESP), // ufix2
.AXI_Lite_RVALID(AXI_Lite_RVALID), // ufix1
.data_write(top_data_write), // ufix32
.addr_sel(top_addr_sel), // ufix14
.wr_enb(top_wr_enb), // ufix1
.rd_enb(top_rd_enb), // ufix1
.reset_internal(top_reset_internal) // ufix1
);
assign write_axi_enable = inst_axi_enable;
assign write_axi_controller_mode = inst_axi_controller_mode;
assign write_axi_command = inst_axi_command;
assign write_axi_velocity_p_gain = inst_axi_velocity_p_gain;
assign write_axi_velocity_i_gain = inst_axi_velocity_i_gain;
assign write_axi_current_p_gain = inst_axi_current_p_gain;
assign write_axi_current_i_gain = inst_axi_current_i_gain;
assign write_axi_open_loop_bias = inst_axi_open_loop_bias;
assign write_axi_open_loop_scalar = inst_axi_open_loop_scalar;
assign write_axi_encoder_zero_offset = inst_axi_encoder_zero_offset;
assign reset_internal = top_reset_internal;
endmodule // controllerperipheralhdladi_pcore_axi_lite

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore_axi_lite_module.v
// Created: 2014-08-28 10:14:05
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerperipheralhdladi_pcore_axi_lite_module
// Source Path: controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite/controllerperipheralhdladi_pcore_axi_lite_module
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerperipheralhdladi_pcore_axi_lite_module
(
CLK_IN,
AXI_Lite_ARESETN,
AXI_Lite_AWADDR,
AXI_Lite_AWVALID,
AXI_Lite_WDATA,
AXI_Lite_WSTRB,
AXI_Lite_WVALID,
AXI_Lite_BREADY,
AXI_Lite_ARADDR,
AXI_Lite_ARVALID,
AXI_Lite_RREADY,
data_read,
AXI_Lite_AWREADY,
AXI_Lite_WREADY,
AXI_Lite_BRESP,
AXI_Lite_BVALID,
AXI_Lite_ARREADY,
AXI_Lite_RDATA,
AXI_Lite_RRESP,
AXI_Lite_RVALID,
data_write,
addr_sel,
wr_enb,
rd_enb,
reset_internal
);
input CLK_IN;
input AXI_Lite_ARESETN; // ufix1
input [31:0] AXI_Lite_AWADDR; // ufix32
input AXI_Lite_AWVALID; // ufix1
input [31:0] AXI_Lite_WDATA; // ufix32
input [3:0] AXI_Lite_WSTRB; // ufix4
input AXI_Lite_WVALID; // ufix1
input AXI_Lite_BREADY; // ufix1
input [31:0] AXI_Lite_ARADDR; // ufix32
input AXI_Lite_ARVALID; // ufix1
input AXI_Lite_RREADY; // ufix1
input [31:0] data_read; // ufix32
output AXI_Lite_AWREADY; // ufix1
output AXI_Lite_WREADY; // ufix1
output [1:0] AXI_Lite_BRESP; // ufix2
output AXI_Lite_BVALID; // ufix1
output AXI_Lite_ARREADY; // ufix1
output [31:0] AXI_Lite_RDATA; // ufix32
output [1:0] AXI_Lite_RRESP; // ufix2
output AXI_Lite_RVALID; // ufix1
output [31:0] data_write; // ufix32
output [13:0] addr_sel; // ufix14
output wr_enb; // ufix1
output rd_enb; // ufix1
output reset_internal; // ufix1
wire reset;
wire enb;
wire const_1; // ufix1
reg [7:0] axi_lite_wstate; // uint8
reg [7:0] axi_lite_rstate; // uint8
reg [7:0] axi_lite_wstate_next; // uint8
reg [7:0] axi_lite_rstate_next; // uint8
reg AXI_Lite_AWREADY_1; // ufix1
reg AXI_Lite_WREADY_1; // ufix1
reg AXI_Lite_BVALID_1; // ufix1
reg AXI_Lite_ARREADY_1; // ufix1
reg AXI_Lite_RVALID_1; // ufix1
reg aw_transfer; // ufix1
reg w_transfer; // ufix1
reg ar_transfer; // ufix1
wire [1:0] const_0_2; // ufix2
reg [31:0] AXI_Lite_RDATA_1; // ufix32
reg [31:0] wdata; // ufix32
reg [31:0] waddr; // ufix32
wire [13:0] waddr_sel; // ufix14
wire [13:0] raddr_sel; // ufix14
reg wr_enb_1; // ufix1
wire strobe_addr; // ufix1
wire strobe_sel; // ufix1
wire const_zero; // ufix1
wire strobe_in; // ufix1
wire strobe_sw; // ufix1
reg soft_reset; // ufix1
reg axi_lite_out0_0_1;
reg axi_lite_out1_0_1;
reg axi_lite_out3_0_1;
reg axi_lite_awvalid_1;
reg axi_lite_wvalid_1;
reg axi_lite_arvalid_1;
assign const_1 = 1'b1;
assign enb = const_1;
assign reset = ~ AXI_Lite_ARESETN;
always @(posedge CLK_IN)
begin : axi_lite_process
if (reset == 1'b1) begin
axi_lite_wstate <= 8'd0;
axi_lite_rstate <= 8'd0;
end
else if (enb) begin
axi_lite_wstate <= axi_lite_wstate_next;
axi_lite_rstate <= axi_lite_rstate_next;
end
end
always @(axi_lite_wstate, axi_lite_rstate, AXI_Lite_AWVALID, AXI_Lite_WVALID,
AXI_Lite_BREADY, AXI_Lite_ARVALID, AXI_Lite_RREADY) begin
axi_lite_wstate_next = axi_lite_wstate;
axi_lite_rstate_next = axi_lite_rstate;
if (AXI_Lite_AWVALID != 1'b0) begin
axi_lite_awvalid_1 = 1'b1;
end
else begin
axi_lite_awvalid_1 = 1'b0;
end
if (AXI_Lite_WVALID != 1'b0) begin
axi_lite_wvalid_1 = 1'b1;
end
else begin
axi_lite_wvalid_1 = 1'b0;
end
if (AXI_Lite_ARVALID != 1'b0) begin
axi_lite_arvalid_1 = 1'b1;
end
else begin
axi_lite_arvalid_1 = 1'b0;
end
case ( axi_lite_wstate)
8'd0 :
begin
axi_lite_out0_0_1 = 1'b1;
axi_lite_out1_0_1 = 1'b0;
AXI_Lite_BVALID_1 = 1'b0;
if (axi_lite_awvalid_1) begin
axi_lite_wstate_next = 8'd1;
end
else begin
axi_lite_wstate_next = 8'd0;
end
end
8'd1 :
begin
axi_lite_out0_0_1 = 1'b0;
axi_lite_out1_0_1 = 1'b1;
AXI_Lite_BVALID_1 = 1'b0;
if (axi_lite_wvalid_1) begin
axi_lite_wstate_next = 8'd2;
end
else begin
axi_lite_wstate_next = 8'd1;
end
end
8'd2 :
begin
axi_lite_out0_0_1 = 1'b0;
axi_lite_out1_0_1 = 1'b0;
AXI_Lite_BVALID_1 = 1'b1;
if (AXI_Lite_BREADY != 1'b0) begin
axi_lite_wstate_next = 8'd0;
end
else begin
axi_lite_wstate_next = 8'd2;
end
end
default :
begin
axi_lite_out0_0_1 = 1'b0;
axi_lite_out1_0_1 = 1'b0;
AXI_Lite_BVALID_1 = 1'b0;
axi_lite_wstate_next = 8'd0;
end
endcase
case ( axi_lite_rstate)
8'd0 :
begin
axi_lite_out3_0_1 = 1'b1;
AXI_Lite_RVALID_1 = 1'b0;
if (axi_lite_arvalid_1) begin
axi_lite_rstate_next = 8'd1;
end
else begin
axi_lite_rstate_next = 8'd0;
end
end
8'd1 :
begin
axi_lite_out3_0_1 = 1'b0;
AXI_Lite_RVALID_1 = 1'b1;
if (AXI_Lite_RREADY != 1'b0) begin
axi_lite_rstate_next = 8'd0;
end
else begin
axi_lite_rstate_next = 8'd1;
end
end
default :
begin
axi_lite_out3_0_1 = 1'b0;
AXI_Lite_RVALID_1 = 1'b0;
axi_lite_rstate_next = 8'd0;
end
endcase
AXI_Lite_AWREADY_1 = axi_lite_out0_0_1;
AXI_Lite_WREADY_1 = axi_lite_out1_0_1;
AXI_Lite_ARREADY_1 = axi_lite_out3_0_1;
aw_transfer = axi_lite_awvalid_1 && axi_lite_out0_0_1;
w_transfer = axi_lite_wvalid_1 && axi_lite_out1_0_1;
ar_transfer = axi_lite_arvalid_1 && axi_lite_out3_0_1;
end
assign const_0_2 = 2'b00;
assign AXI_Lite_BRESP = const_0_2;
always @(posedge CLK_IN)
begin : reg_rdata_process
if (reset == 1'b1) begin
AXI_Lite_RDATA_1 <= 32'b00000000000000000000000000000000;
end
else if (enb && ar_transfer) begin
AXI_Lite_RDATA_1 <= data_read;
end
end
assign AXI_Lite_RRESP = const_0_2;
always @(posedge CLK_IN)
begin : reg_wdata_process
if (reset == 1'b1) begin
wdata <= 32'b00000000000000000000000000000000;
end
else if (enb && w_transfer) begin
wdata <= AXI_Lite_WDATA;
end
end
assign data_write = wdata;
always @(posedge CLK_IN)
begin : reg_waddr_process
if (reset == 1'b1) begin
waddr <= 32'b00000000000000000000000000000000;
end
else if (enb && aw_transfer) begin
waddr <= AXI_Lite_AWADDR;
end
end
assign waddr_sel = waddr[15:2];
assign raddr_sel = AXI_Lite_ARADDR[15:2];
assign addr_sel = (AXI_Lite_ARVALID == 1'b0 ? waddr_sel :
raddr_sel);
always @(posedge CLK_IN)
begin : reg_wr_enb_process
if (reset == 1'b1) begin
wr_enb_1 <= 1'b0;
end
else if (enb) begin
wr_enb_1 <= w_transfer;
end
end
assign rd_enb = ar_transfer;
assign strobe_addr = (waddr_sel == 14'b00000000000000 ? 1'b1 :
1'b0);
assign strobe_sel = strobe_addr & wr_enb_1;
assign const_zero = 1'b0;
assign strobe_in = wdata[0];
assign strobe_sw = (strobe_sel == 1'b0 ? const_zero :
strobe_in);
always @(posedge CLK_IN)
begin : reg_rsvd_process
if (reset == 1'b1) begin
soft_reset <= 1'b0;
end
else if (enb) begin
soft_reset <= strobe_sw;
end
end
assign reset_internal = reset | soft_reset;
assign AXI_Lite_AWREADY = AXI_Lite_AWREADY_1;
assign AXI_Lite_WREADY = AXI_Lite_WREADY_1;
assign AXI_Lite_BVALID = AXI_Lite_BVALID_1;
assign AXI_Lite_ARREADY = AXI_Lite_ARREADY_1;
assign AXI_Lite_RDATA = AXI_Lite_RDATA_1;
assign AXI_Lite_RVALID = AXI_Lite_RVALID_1;
assign wr_enb = wr_enb_1;
endmodule // controllerperipheralhdladi_pcore_axi_lite_module

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore_dut.v
// Created: 2014-08-28 10:14:05
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerperipheralhdladi_pcore_dut
// Source Path: controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_dut
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerperipheralhdladi_pcore_dut
(
CLK_IN,
reset,
dut_enable,
adc_current1,
adc_current2,
encoder_a,
encoder_b,
encoder_index,
axi_controller_mode,
axi_command,
axi_velocity_p_gain,
axi_velocity_i_gain,
axi_current_p_gain,
axi_current_i_gain,
axi_open_loop_bias,
axi_open_loop_scalar,
axi_encoder_zero_offset,
ce_out_0,
ce_out_1,
pwm_a,
pwm_b,
pwm_c,
mon_phase_voltage_a,
mon_phase_voltage_b,
mon_phase_current_a,
mon_phase_current_b,
mon_rotor_position,
mon_electrical_position,
mon_rotor_velocity,
mon_d_current,
mon_q_current,
axi_electrical_pos_err
);
input CLK_IN;
input reset;
input dut_enable; // ufix1
input signed [17:0] adc_current1; // sfix18_En17
input signed [17:0] adc_current2; // sfix18_En17
input encoder_a; // ufix1
input encoder_b; // ufix1
input encoder_index; // ufix1
input [1:0] axi_controller_mode; // ufix2
input signed [17:0] axi_command; // sfix18_En8
input signed [17:0] axi_velocity_p_gain; // sfix18_En16
input signed [17:0] axi_velocity_i_gain; // sfix18_En15
input signed [17:0] axi_current_p_gain; // sfix18_En10
input signed [17:0] axi_current_i_gain; // sfix18_En2
input signed [17:0] axi_open_loop_bias; // sfix18_En14
input signed [17:0] axi_open_loop_scalar; // sfix18_En16
input signed [17:0] axi_encoder_zero_offset; // sfix18_En14
output ce_out_0; // ufix1
output ce_out_1; // ufix1
output pwm_a; // ufix1
output pwm_b; // ufix1
output pwm_c; // ufix1
output signed [31:0] mon_phase_voltage_a; // sfix32
output signed [31:0] mon_phase_voltage_b; // sfix32
output signed [31:0] mon_phase_current_a; // sfix32
output signed [31:0] mon_phase_current_b; // sfix32
output signed [31:0] mon_rotor_position; // sfix32
output signed [31:0] mon_electrical_position; // sfix32
output signed [31:0] mon_rotor_velocity; // sfix32
output signed [31:0] mon_d_current; // sfix32
output signed [31:0] mon_q_current; // sfix32
output signed [18:0] axi_electrical_pos_err; // sfix19_En14
wire enb;
wire ce_out_0_sig; // ufix1
wire ce_out_1_sig; // ufix1
wire pwm_a_sig; // ufix1
wire pwm_b_sig; // ufix1
wire pwm_c_sig; // ufix1
wire signed [31:0] mon_phase_voltage_a_sig; // sfix32
wire signed [31:0] mon_phase_voltage_b_sig; // sfix32
wire signed [31:0] mon_phase_current_a_sig; // sfix32
wire signed [31:0] mon_phase_current_b_sig; // sfix32
wire signed [31:0] mon_rotor_position_sig; // sfix32
wire signed [31:0] mon_electrical_position_sig; // sfix32
wire signed [31:0] mon_rotor_velocity_sig; // sfix32
wire signed [31:0] mon_d_current_sig; // sfix32
wire signed [31:0] mon_q_current_sig; // sfix32
wire signed [18:0] axi_electrical_pos_err_sig; // sfix19_En14
assign enb = dut_enable;
controllerPeripheralHdlAdi u_controllerPeripheralHdlAdi (.CLK_IN(CLK_IN),
.clk_enable(enb),
.reset(reset),
.adc_current1(adc_current1), // sfix18_En17
.adc_current2(adc_current2), // sfix18_En17
.encoder_a(encoder_a), // ufix1
.encoder_b(encoder_b), // ufix1
.encoder_index(encoder_index), // ufix1
.axi_controller_mode(axi_controller_mode), // ufix2
.axi_command(axi_command), // sfix18_En8
.axi_velocity_p_gain(axi_velocity_p_gain), // sfix18_En16
.axi_velocity_i_gain(axi_velocity_i_gain), // sfix18_En15
.axi_current_p_gain(axi_current_p_gain), // sfix18_En10
.axi_current_i_gain(axi_current_i_gain), // sfix18_En2
.axi_open_loop_bias(axi_open_loop_bias), // sfix18_En14
.axi_open_loop_scalar(axi_open_loop_scalar), // sfix18_En16
.axi_encoder_zero_offset(axi_encoder_zero_offset), // sfix18_En14
.ce_out_0(ce_out_0_sig), // ufix1
.ce_out_1(ce_out_1_sig), // ufix1
.pwm_a(pwm_a_sig), // ufix1
.pwm_b(pwm_b_sig), // ufix1
.pwm_c(pwm_c_sig), // ufix1
.mon_phase_voltage_a(mon_phase_voltage_a_sig), // sfix32
.mon_phase_voltage_b(mon_phase_voltage_b_sig), // sfix32
.mon_phase_current_a(mon_phase_current_a_sig), // sfix32
.mon_phase_current_b(mon_phase_current_b_sig), // sfix32
.mon_rotor_position(mon_rotor_position_sig), // sfix32
.mon_electrical_position(mon_electrical_position_sig), // sfix32
.mon_rotor_velocity(mon_rotor_velocity_sig), // sfix32
.mon_d_current(mon_d_current_sig), // sfix32
.mon_q_current(mon_q_current_sig), // sfix32
.axi_electrical_pos_err(axi_electrical_pos_err_sig) // sfix19_En14
);
assign ce_out_0 = ce_out_0_sig;
assign ce_out_1 = ce_out_1_sig;
assign pwm_a = pwm_a_sig;
assign pwm_b = pwm_b_sig;
assign pwm_c = pwm_c_sig;
assign mon_phase_voltage_a = mon_phase_voltage_a_sig;
assign mon_phase_voltage_b = mon_phase_voltage_b_sig;
assign mon_phase_current_a = mon_phase_current_a_sig;
assign mon_phase_current_b = mon_phase_current_b_sig;
assign mon_rotor_position = mon_rotor_position_sig;
assign mon_electrical_position = mon_electrical_position_sig;
assign mon_rotor_velocity = mon_rotor_velocity_sig;
assign mon_d_current = mon_d_current_sig;
assign mon_q_current = mon_q_current_sig;
assign axi_electrical_pos_err = axi_electrical_pos_err_sig;
endmodule // controllerperipheralhdladi_pcore_dut

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clamp.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Clamp
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Clamp
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Clamp
(
preIntegrator,
preSat,
saturated,
Clamp
);
input signed [35:0] preIntegrator; // sfix36_En29
input signed [35:0] preSat; // sfix36_En23
input saturated;
output Clamp;
wire Compare_To_Zero_out1;
wire Compare_To_Zero1_out1;
wire Compare_To_Zero_out1_1;
wire Logical_Operator_out1;
// <S9>/Compare To Zero
assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S9>/Compare To Zero1
assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S9>/Logical Operator
assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1);
// <S9>/AND
assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated;
assign Clamp = Logical_Operator_out1;
endmodule // velocityControlHdl_Clamp

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clamp_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Clamp_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Clamp
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Clamp_block
(
preIntegrator,
preSat,
saturated,
Clamp
);
input signed [35:0] preIntegrator; // sfix36_En29
input signed [35:0] preSat; // sfix36_En23
input saturated;
output Clamp;
wire Compare_To_Zero_out1;
wire Compare_To_Zero1_out1;
wire Compare_To_Zero_out1_1;
wire Logical_Operator_out1;
// <S17>/Compare To Zero
assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S17>/Compare To Zero1
assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S17>/Logical Operator
assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1);
// <S17>/AND
assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated;
assign Clamp = Logical_Operator_out1;
endmodule // velocityControlHdl_Clamp_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clamp_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Clamp_block1
// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Clamp
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Clamp_block1
(
preSat,
saturated,
preIntegrator,
Clamp
);
input signed [35:0] preSat; // sfix36_En22
input saturated;
input signed [35:0] preIntegrator; // sfix36_En35
output Clamp;
wire Compare_To_Zero_out1;
wire Compare_To_Zero1_out1;
wire Compare_To_Zero_out1_1;
wire Logical_Operator_out1;
// <S26>/Compare To Zero
assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S26>/Compare To Zero1
assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S26>/Logical Operator
assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1);
// <S26>/AND
assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated;
assign Clamp = Logical_Operator_out1;
endmodule // velocityControlHdl_Clamp_block1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clarke_Transform.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Clarke_Transform
// Source Path: velocityControlHdl/Transform_ABC_to_dq/Clarke_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Clarke_Transform
(
phase_currents_0,
phase_currents_1,
alpha_current,
beta_current
);
input signed [17:0] phase_currents_0; // sfix18_En15
input signed [17:0] phase_currents_1; // sfix18_En15
output signed [17:0] alpha_current; // sfix18_En13
output signed [17:0] beta_current; // sfix18_En13
wire signed [17:0] Alpha_Current_Data_Type_out1; // sfix18_En13
wire signed [35:0] Alpha_Gain_With_Headrom_out1; // sfix36_En31
wire signed [35:0] Beta_Gain_With_Headrom_out1; // sfix36_En31
wire signed [35:0] Add_out1; // sfix36_En31
wire signed [17:0] Beta_Current_Data_Type_out1; // sfix18_En13
// Converts balanced three-phase quantities into balanced two-phase quantities.
// The A and B phases are converted to the direct axis (alpha) component and the quadrature axis (beta) component.
// The alpha and beta components are still dependent on time and speed.
//
// Clarke Transform
// <S41>/Alpha_Current_Data_Type
//
// <S41>/A_phase_current
//
// <S41>/B_phase_current
assign Alpha_Current_Data_Type_out1 = {{2{phase_currents_0[17]}}, phase_currents_0[17:2]};
assign alpha_current = Alpha_Current_Data_Type_out1;
// <S41>/Alpha_Gain_With_Headrom
assign Alpha_Gain_With_Headrom_out1 = 37837 * phase_currents_0;
// <S41>/Beta_Gain_With_Headrom
assign Beta_Gain_With_Headrom_out1 = 75674 * phase_currents_1;
// <S41>/Add
assign Add_out1 = Alpha_Gain_With_Headrom_out1 + Beta_Gain_With_Headrom_out1;
// <S41>/Beta_Current_Data_Type
assign Beta_Current_Data_Type_out1 = Add_out1[35:18];
assign beta_current = Beta_Current_Data_Type_out1;
endmodule // velocityControlHdl_Clarke_Transform

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Complex_Multiply.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Complex_Multiply
// Source Path: velocityControlHdl/Sin_Cos1/Complex_Multiply
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Complex_Multiply
(
In1_re,
In1_im,
In2_re,
In2_im,
Re,
Im
);
input signed [17:0] In1_re; // sfix18_En16
input signed [17:0] In1_im; // sfix18_En16
input signed [17:0] In2_re; // sfix18_En16
input signed [17:0] In2_im; // sfix18_En16
output signed [35:0] Re; // sfix36_En32
output signed [35:0] Im; // sfix36_En32
wire signed [35:0] Product_out1; // sfix36_En32
wire signed [35:0] Product1_out1; // sfix36_En32
wire signed [35:0] Add1_out1; // sfix36_En32
wire signed [35:0] Product2_out1; // sfix36_En32
wire signed [35:0] Product3_out1; // sfix36_En32
wire signed [35:0] Add2_out1; // sfix36_En32
// <S34>/Product
//
// <S34>/Complex to Real-Imag1
//
// <S34>/Complex to Real-Imag2
assign Product_out1 = In1_re * In2_re;
// <S34>/Product1
assign Product1_out1 = In1_im * In2_im;
// <S34>/Add1
assign Add1_out1 = Product_out1 - Product1_out1;
assign Re = Add1_out1;
// <S34>/Product2
assign Product2_out1 = In1_re * In2_im;
// <S34>/Product3
assign Product3_out1 = In1_im * In2_re;
// <S34>/Add2
assign Add2_out1 = Product2_out1 + Product3_out1;
assign Im = Add2_out1;
endmodule // velocityControlHdl_Complex_Multiply

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_Current.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Control_Current
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Control_Current
(
CLK_IN,
reset,
enb_1_2000_0,
Reest,
Err,
param_current_p_gain,
param_current_i_gain,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reest;
input signed [17:0] Err; // sfix18_En14
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
output signed [17:0] Out; // sfix18_En12
wire signed [35:0] Product2_out1; // sfix36_En24
wire signed [35:0] Convert_Data_Type1_out1; // sfix36_En23
wire signed [17:0] Constant2_out1; // sfix18_En31
wire signed [35:0] Product_out1; // sfix36_En33
wire signed [17:0] pre_integrator; // sfix18_En15
wire signed [35:0] pre_integrator_1; // sfix36_En29
wire signed [35:0] Constant_out1; // sfix36_En29
wire signed [35:0] u; // sfix36_En23
wire PI_Sat_out2;
wire Clamp_out1;
wire switch_compare_1;
wire signed [35:0] Switch_out1; // sfix36_En29
wire signed [31:0] I_term; // sfix32_En26
wire signed [36:0] Add_add_cast; // sfix37_En29
wire signed [36:0] Add_add_cast_1; // sfix37_En29
wire signed [36:0] Add_add_temp; // sfix37_En29
wire signed [31:0] Add_out1; // sfix32_En26
wire signed [39:0] Sum1_add_cast; // sfix40_En26
wire signed [39:0] Sum1_add_cast_1; // sfix40_En26
wire signed [39:0] Sum1_add_temp; // sfix40_En26
wire signed [35:0] u_sat; // sfix36_En23
wire signed [17:0] D_Data_Type_out1; // sfix18_En12
// Control Current
// <S7>/Product2
assign Product2_out1 = param_current_p_gain * Err;
// <S7>/Convert_Data_Type1
velocityControlHdl_Convert_Data_Type1 u_Convert_Data_Type1 (.In1(Product2_out1), // sfix36_En24
.Out1(Convert_Data_Type1_out1) // sfix36_En23
);
// <S7>/Constant2
assign Constant2_out1 = 18'sb010100111110001011;
// <S7>/Product
assign Product_out1 = param_current_i_gain * Constant2_out1;
// <S7>/Maintain_Range
velocityControlHdl_Maintain_Range u_Maintain_Range (.In1(Product_out1), // sfix36_En33
.Out1(pre_integrator) // sfix18_En15
);
// <S7>/Product1
assign pre_integrator_1 = Err * pre_integrator;
// <S7>/Constant
assign Constant_out1 = 36'sh000000000;
// <S7>/Clamp
velocityControlHdl_Clamp u_Clamp (.preIntegrator(pre_integrator_1), // sfix36_En29
.preSat(u), // sfix36_En23
.saturated(PI_Sat_out2),
.Clamp(Clamp_out1)
);
assign switch_compare_1 = (Clamp_out1 > 1'b0 ? 1'b1 :
1'b0);
// <S7>/Switch
assign Switch_out1 = (switch_compare_1 == 1'b0 ? pre_integrator_1 :
Constant_out1);
// <S7>/Add
assign Add_add_cast = Switch_out1;
assign Add_add_cast_1 = {{2{I_term[31]}}, {I_term, 3'b000}};
assign Add_add_temp = Add_add_cast + Add_add_cast_1;
assign Add_out1 = ((Add_add_temp[36] == 1'b0) && (Add_add_temp[35:34] != 2'b00) ? 32'sb01111111111111111111111111111111 :
((Add_add_temp[36] == 1'b1) && (Add_add_temp[35:34] != 2'b11) ? 32'sb10000000000000000000000000000000 :
$signed(Add_add_temp[34:3])));
// <S7>/Reset_Delay
velocityControlHdl_Reset_Delay u_Reset_Delay (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reest),
.In(Add_out1), // sfix32_En26
.Out(I_term) // sfix32_En26
);
// <S7>/Sum1
assign Sum1_add_cast = {Convert_Data_Type1_out1[35], {Convert_Data_Type1_out1, 3'b000}};
assign Sum1_add_cast_1 = I_term;
assign Sum1_add_temp = Sum1_add_cast + Sum1_add_cast_1;
assign u = Sum1_add_temp[38:3];
// <S7>/PI_Sat
velocityControlHdl_PI_Sat u_PI_Sat (.In1(u), // sfix36_En23
.Out1(u_sat), // sfix36_En23
.saturated(PI_Sat_out2)
);
// <S7>/D_Data_Type
assign D_Data_Type_out1 = u_sat[28:11];
assign Out = D_Data_Type_out1;
endmodule // velocityControlHdl_Control_Current

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_Current1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Control_Current1
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Control_Current1
(
CLK_IN,
reset,
enb_1_2000_0,
Reest,
Err,
param_current_p_gain,
param_current_i_gain,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reest;
input signed [17:0] Err; // sfix18_En14
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
output signed [17:0] Out; // sfix18_En12
wire signed [35:0] Product2_out1; // sfix36_En24
wire signed [35:0] Convert_Data_Type1_out1; // sfix36_En23
wire signed [17:0] Constant2_out1; // sfix18_En31
wire signed [35:0] Product_out1; // sfix36_En33
wire signed [17:0] pre_integrator; // sfix18_En15
wire signed [35:0] pre_integrator_1; // sfix36_En29
wire signed [35:0] Constant_out1; // sfix36_En29
wire signed [35:0] u; // sfix36_En23
wire PI_Sat_out2;
wire Clamp_out1;
wire switch_compare_1;
wire signed [35:0] Switch_out1; // sfix36_En29
wire signed [31:0] I_term; // sfix32_En26
wire signed [36:0] Add_add_cast; // sfix37_En29
wire signed [36:0] Add_add_cast_1; // sfix37_En29
wire signed [36:0] Add_add_temp; // sfix37_En29
wire signed [31:0] Add_out1; // sfix32_En26
wire signed [39:0] Sum1_add_cast; // sfix40_En26
wire signed [39:0] Sum1_add_cast_1; // sfix40_En26
wire signed [39:0] Sum1_add_temp; // sfix40_En26
wire signed [35:0] u_sat; // sfix36_En23
wire signed [17:0] D_Data_Type_out1; // sfix18_En12
// Control Current
// <S8>/Product2
assign Product2_out1 = param_current_p_gain * Err;
// <S8>/Convert_Data_Type1
velocityControlHdl_Convert_Data_Type1_block u_Convert_Data_Type1 (.In1(Product2_out1), // sfix36_En24
.Out1(Convert_Data_Type1_out1) // sfix36_En23
);
// <S8>/Constant2
assign Constant2_out1 = 18'sb010100111110001011;
// <S8>/Product
assign Product_out1 = param_current_i_gain * Constant2_out1;
// <S8>/Maintain_Range
velocityControlHdl_Maintain_Range_block u_Maintain_Range (.In1(Product_out1), // sfix36_En33
.Out1(pre_integrator) // sfix18_En15
);
// <S8>/Product1
assign pre_integrator_1 = Err * pre_integrator;
// <S8>/Constant
assign Constant_out1 = 36'sh000000000;
// <S8>/Clamp
velocityControlHdl_Clamp_block u_Clamp (.preIntegrator(pre_integrator_1), // sfix36_En29
.preSat(u), // sfix36_En23
.saturated(PI_Sat_out2),
.Clamp(Clamp_out1)
);
assign switch_compare_1 = (Clamp_out1 > 1'b0 ? 1'b1 :
1'b0);
// <S8>/Switch
assign Switch_out1 = (switch_compare_1 == 1'b0 ? pre_integrator_1 :
Constant_out1);
// <S8>/Add
assign Add_add_cast = Switch_out1;
assign Add_add_cast_1 = {{2{I_term[31]}}, {I_term, 3'b000}};
assign Add_add_temp = Add_add_cast + Add_add_cast_1;
assign Add_out1 = ((Add_add_temp[36] == 1'b0) && (Add_add_temp[35:34] != 2'b00) ? 32'sb01111111111111111111111111111111 :
((Add_add_temp[36] == 1'b1) && (Add_add_temp[35:34] != 2'b11) ? 32'sb10000000000000000000000000000000 :
$signed(Add_add_temp[34:3])));
// <S8>/Reset_Delay
velocityControlHdl_Reset_Delay_block u_Reset_Delay (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reest),
.In(Add_out1), // sfix32_En26
.Out(I_term) // sfix32_En26
);
// <S8>/Sum1
assign Sum1_add_cast = {Convert_Data_Type1_out1[35], {Convert_Data_Type1_out1, 3'b000}};
assign Sum1_add_cast_1 = I_term;
assign Sum1_add_temp = Sum1_add_cast + Sum1_add_cast_1;
assign u = Sum1_add_temp[38:3];
// <S8>/PI_Sat
velocityControlHdl_PI_Sat_block u_PI_Sat (.In1(u), // sfix36_En23
.Out1(u_sat), // sfix36_En23
.saturated(PI_Sat_out2)
);
// <S8>/D_Data_Type
assign D_Data_Type_out1 = u_sat[28:11];
assign Out = D_Data_Type_out1;
endmodule // velocityControlHdl_Control_Current1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_DQ_Currents.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Control_DQ_Currents
// Source Path: velocityControlHdl/Control_DQ_Currents
// Hierarchy Level: 4
//
// Simulink subsystem description for velocityControlHdl/Control_DQ_Currents:
//
// Linear Current Controllers
//
// PID Blocks used for Control Design of Current Loop controllers.
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Control_DQ_Currents
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
q_current_command,
d_current_measured,
q_current_measured,
param_current_p_gain,
param_current_i_gain,
d_voltage,
q_voltage
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [17:0] q_current_command; // sfix18_En15
input signed [17:0] d_current_measured; // sfix18_En15
input signed [17:0] q_current_measured; // sfix18_En15
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
output signed [17:0] d_voltage; // sfix18_En12
output signed [17:0] q_voltage; // sfix18_En12
wire signed [17:0] d_current_command_1; // sfix18_En15
wire signed [18:0] D_Error_sub_cast; // sfix19_En15
wire signed [18:0] D_Error_sub_cast_1; // sfix19_En15
wire signed [18:0] D_Error_sub_temp; // sfix19_En15
wire signed [17:0] d_current_error; // sfix18_En14
wire signed [17:0] direct_voltage; // sfix18_En12
wire signed [18:0] Q_Error_sub_cast; // sfix19_En15
wire signed [18:0] Q_Error_sub_cast_1; // sfix19_En15
wire signed [18:0] Q_Error_sub_temp; // sfix19_En15
wire signed [17:0] q_current_error; // sfix18_En14
wire signed [17:0] quadrature_voltage; // sfix18_En12
// The controller regulates direct and quadrature currents.
//
// Current Controllers
// <S1>/d_current_command
assign d_current_command_1 = 18'sb000000000000000000;
// <S1>/D_Error
assign D_Error_sub_cast = d_current_command_1;
assign D_Error_sub_cast_1 = d_current_measured;
assign D_Error_sub_temp = D_Error_sub_cast - D_Error_sub_cast_1;
assign d_current_error = D_Error_sub_temp[18:1];
// <S1>/Control_Current
velocityControlHdl_Control_Current u_Control_Current (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reest(Reset_1),
.Err(d_current_error), // sfix18_En14
.param_current_p_gain(param_current_p_gain), // sfix18_En10
.param_current_i_gain(param_current_i_gain), // sfix18_En2
.Out(direct_voltage) // sfix18_En12
);
assign d_voltage = direct_voltage;
// <S1>/Q_Error
assign Q_Error_sub_cast = q_current_command;
assign Q_Error_sub_cast_1 = q_current_measured;
assign Q_Error_sub_temp = Q_Error_sub_cast - Q_Error_sub_cast_1;
assign q_current_error = Q_Error_sub_temp[18:1];
// <S1>/Control_Current1
velocityControlHdl_Control_Current1 u_Control_Current1 (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reest(Reset_1),
.Err(q_current_error), // sfix18_En14
.param_current_p_gain(param_current_p_gain), // sfix18_En10
.param_current_i_gain(param_current_i_gain), // sfix18_En2
.Out(quadrature_voltage) // sfix18_En12
);
assign q_voltage = quadrature_voltage;
endmodule // velocityControlHdl_Control_DQ_Currents

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_Velocity.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Control_Velocity
// Source Path: velocityControlHdl/Control_Velocity
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Control_Velocity
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
velocity_command,
velocity_measured,
param_velocity_p_gain,
param_velocity_i_gain,
q_command
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [17:0] velocity_command; // sfix18_En8
input signed [17:0] velocity_measured; // sfix18_En8
input signed [17:0] param_velocity_p_gain; // sfix18_En16
input signed [17:0] param_velocity_i_gain; // sfix18_En15
output signed [17:0] q_command; // sfix18_En15
wire signed [18:0] Error_Sum_sub_cast; // sfix19_En8
wire signed [18:0] Error_Sum_sub_cast_1; // sfix19_En8
wire signed [18:0] Error_Sum_sub_temp; // sfix19_En8
wire signed [17:0] velocity_error; // sfix18_En7
// Velocity Controller
//
// The controller regulates motor velocity using rotor velocity feedback compared to a commanded velocity.
// The output of the controller is the quadrature-winding current command which is directly proportional to the electromagnetic torque of the motor.
// Since the motor being controlled is a Permanent Magnet Synchronous Machine, the rotor flux linkage is fixed (determined by the magnets),
// hence the commanded direct-winding current is always zero.
// <S2>/Error Sum
assign Error_Sum_sub_cast = velocity_command;
assign Error_Sum_sub_cast_1 = velocity_measured;
assign Error_Sum_sub_temp = Error_Sum_sub_cast - Error_Sum_sub_cast_1;
assign velocity_error = Error_Sum_sub_temp[18:1];
// <S2>/Rotor_Velocity_Control
velocityControlHdl_Rotor_Velocity_Control u_Rotor_Velocity_Control (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reset_1),
.Err(velocity_error), // sfix18_En7
.param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16
.param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15
.Out(q_command) // sfix18_En15
);
endmodule // velocityControlHdl_Control_Velocity

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Convert_Data_Type
// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Convert_Data_Type
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Convert_Data_Type
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En23
output signed [35:0] Out1; // sfix36_En22
wire signed [35:0] Data_Type_Conversion_out1; // sfix36_En22
// <S27>/Data Type Conversion
assign Data_Type_Conversion_out1 = {In1[35], In1[35:1]};
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Convert_Data_Type

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Convert_Data_Type1
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Convert_Data_Type1
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Convert_Data_Type1
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En24
output signed [35:0] Out1; // sfix36_En23
wire signed [35:0] Data_Type_Conversion_out1; // sfix36_En23
// <S10>/Data Type Conversion
assign Data_Type_Conversion_out1 = {In1[35], In1[35:1]};
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Convert_Data_Type1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type1_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Convert_Data_Type1_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Convert_Data_Type1
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Convert_Data_Type1_block
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En24
output signed [35:0] Out1; // sfix36_En23
wire signed [35:0] Data_Type_Conversion_out1; // sfix36_En23
// <S18>/Data Type Conversion
assign Data_Type_Conversion_out1 = {In1[35], In1[35:1]};
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Convert_Data_Type1_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type1_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Convert_Data_Type1_block1
// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Park_Transform/Convert_Data_Type1
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Convert_Data_Type1_block1
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En28
output signed [17:0] Out1; // sfix18_En10
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En10
// <S46>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[35:18];
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Convert_Data_Type1_block1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Convert_Data_Type_block
// Source Path: velocityControlHdl/Sin_Cos1/Convert_Data_Type
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Convert_Data_Type_block
(
In1,
Out1
);
input signed [17:0] In1; // sfix18_En14
output signed [17:0] Out1; // sfix18_En14
// <S35>/Data Type Conversion
assign Out1 = In1;
endmodule // velocityControlHdl_Convert_Data_Type_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Convert_Data_Type_block1
// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Park_Transform/Convert_Data_Type
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Convert_Data_Type_block1
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En28
output signed [17:0] Out1; // sfix18_En10
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En10
// <S45>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[35:18];
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Convert_Data_Type_block1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Double_Range.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Double_Range
// Source Path: velocityControlHdl/Space_Vector_Modulation/Double_Range
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Double_Range
(
In1_0,
In1_1,
In1_2,
Out1_0,
Out1_1,
Out1_2
);
input signed [17:0] In1_0; // sfix18_En13
input signed [17:0] In1_1; // sfix18_En13
input signed [17:0] In1_2; // sfix18_En13
output signed [17:0] Out1_0; // sfix18_En12
output signed [17:0] Out1_1; // sfix18_En12
output signed [17:0] Out1_2; // sfix18_En12
wire signed [17:0] In1 [0:2]; // sfix18_En13 [3]
wire signed [17:0] Data_Type_Conversion_out1 [0:2]; // sfix18_En12 [3]
assign In1[0] = In1_0;
assign In1[1] = In1_1;
assign In1[2] = In1_2;
// <S40>/Data Type Conversion
assign Data_Type_Conversion_out1[0] = {In1[0][17], In1[0][17:1]};
assign Data_Type_Conversion_out1[1] = {In1[1][17], In1[1][17:1]};
assign Data_Type_Conversion_out1[2] = {In1[2][17], In1[2][17:1]};
assign Out1_0 = Data_Type_Conversion_out1[0];
assign Out1_1 = Data_Type_Conversion_out1[1];
assign Out1_2 = Data_Type_Conversion_out1[2];
endmodule // velocityControlHdl_Double_Range

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Dynamic_Saturation.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Dynamic_Saturation
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/PI_Sat/Dynamic Saturation
// Hierarchy Level: 7
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Dynamic_Saturation
(
up,
u,
lo,
y,
sat_mode
);
input signed [17:0] up; // sfix18_En13
input signed [35:0] u; // sfix36_En23
input signed [17:0] lo; // sfix18_En13
output signed [35:0] y; // sfix36_En23
output sat_mode;
wire signed [35:0] LowerRelop1_1_cast; // sfix36_En23
wire LowerRelop1_relop1;
wire signed [35:0] UpperRelop_1_cast; // sfix36_En23
wire UpperRelop_relop1;
wire signed [35:0] lo_dtc; // sfix36_En23
wire signed [35:0] Switch_out1; // sfix36_En23
wire signed [35:0] up_dtc; // sfix36_En23
wire signed [35:0] Switch2_out1; // sfix36_En23
wire LowerRelop1_out1;
// <S16>/LowerRelop1
assign LowerRelop1_1_cast = {{8{up[17]}}, {up, 10'b0000000000}};
assign LowerRelop1_relop1 = (u > LowerRelop1_1_cast ? 1'b1 :
1'b0);
// <S16>/UpperRelop
assign UpperRelop_1_cast = {{8{lo[17]}}, {lo, 10'b0000000000}};
assign UpperRelop_relop1 = (u < UpperRelop_1_cast ? 1'b1 :
1'b0);
assign lo_dtc = {{8{lo[17]}}, {lo, 10'b0000000000}};
// <S16>/Switch
assign Switch_out1 = (UpperRelop_relop1 == 1'b0 ? u :
lo_dtc);
assign up_dtc = {{8{up[17]}}, {up, 10'b0000000000}};
// <S16>/Switch2
assign Switch2_out1 = (LowerRelop1_relop1 == 1'b0 ? Switch_out1 :
up_dtc);
assign y = Switch2_out1;
// <S16>/Logical Operator
assign LowerRelop1_out1 = LowerRelop1_relop1 | UpperRelop_relop1;
assign sat_mode = LowerRelop1_out1;
endmodule // velocityControlHdl_Dynamic_Saturation

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Dynamic_Saturation_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Dynamic_Saturation_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/PI_Sat/Dynamic Saturation
// Hierarchy Level: 7
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Dynamic_Saturation_block
(
up,
u,
lo,
y,
sat_mode
);
input signed [17:0] up; // sfix18_En13
input signed [35:0] u; // sfix36_En23
input signed [17:0] lo; // sfix18_En13
output signed [35:0] y; // sfix36_En23
output sat_mode;
wire signed [35:0] LowerRelop1_1_cast; // sfix36_En23
wire LowerRelop1_relop1;
wire signed [35:0] UpperRelop_1_cast; // sfix36_En23
wire UpperRelop_relop1;
wire signed [35:0] lo_dtc; // sfix36_En23
wire signed [35:0] Switch_out1; // sfix36_En23
wire signed [35:0] up_dtc; // sfix36_En23
wire signed [35:0] Switch2_out1; // sfix36_En23
wire LowerRelop1_out1;
// <S24>/LowerRelop1
assign LowerRelop1_1_cast = {{8{up[17]}}, {up, 10'b0000000000}};
assign LowerRelop1_relop1 = (u > LowerRelop1_1_cast ? 1'b1 :
1'b0);
// <S24>/UpperRelop
assign UpperRelop_1_cast = {{8{lo[17]}}, {lo, 10'b0000000000}};
assign UpperRelop_relop1 = (u < UpperRelop_1_cast ? 1'b1 :
1'b0);
assign lo_dtc = {{8{lo[17]}}, {lo, 10'b0000000000}};
// <S24>/Switch
assign Switch_out1 = (UpperRelop_relop1 == 1'b0 ? u :
lo_dtc);
assign up_dtc = {{8{up[17]}}, {up, 10'b0000000000}};
// <S24>/Switch2
assign Switch2_out1 = (LowerRelop1_relop1 == 1'b0 ? Switch_out1 :
up_dtc);
assign y = Switch2_out1;
// <S24>/Logical Operator
assign LowerRelop1_out1 = LowerRelop1_relop1 | UpperRelop_relop1;
assign sat_mode = LowerRelop1_out1;
endmodule // velocityControlHdl_Dynamic_Saturation_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Dynamic_Saturation_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Dynamic_Saturation_block1
// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/PI_Sat/Dynamic Saturation
// Hierarchy Level: 7
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Dynamic_Saturation_block1
(
up,
u,
lo,
y,
sat_mode
);
input signed [17:0] up; // sfix18_En15
input signed [35:0] u; // sfix36_En22
input signed [17:0] lo; // sfix18_En15
output signed [35:0] y; // sfix36_En22
output sat_mode;
wire signed [35:0] LowerRelop1_1_cast; // sfix36_En22
wire LowerRelop1_relop1;
wire signed [35:0] UpperRelop_1_cast; // sfix36_En22
wire UpperRelop_relop1;
wire signed [35:0] lo_dtc; // sfix36_En22
wire signed [35:0] Switch_out1; // sfix36_En22
wire signed [35:0] up_dtc; // sfix36_En22
wire signed [35:0] Switch2_out1; // sfix36_En22
wire LowerRelop1_out1;
// <S33>/LowerRelop1
assign LowerRelop1_1_cast = {{11{up[17]}}, {up, 7'b0000000}};
assign LowerRelop1_relop1 = (u > LowerRelop1_1_cast ? 1'b1 :
1'b0);
// <S33>/UpperRelop
assign UpperRelop_1_cast = {{11{lo[17]}}, {lo, 7'b0000000}};
assign UpperRelop_relop1 = (u < UpperRelop_1_cast ? 1'b1 :
1'b0);
assign lo_dtc = {{11{lo[17]}}, {lo, 7'b0000000}};
// <S33>/Switch
assign Switch_out1 = (UpperRelop_relop1 == 1'b0 ? u :
lo_dtc);
assign up_dtc = {{11{up[17]}}, {up, 7'b0000000}};
// <S33>/Switch2
assign Switch2_out1 = (LowerRelop1_relop1 == 1'b0 ? Switch_out1 :
up_dtc);
assign y = Switch2_out1;
// <S33>/Logical Operator
assign LowerRelop1_out1 = LowerRelop1_relop1 | UpperRelop_relop1;
assign sat_mode = LowerRelop1_out1;
endmodule // velocityControlHdl_Dynamic_Saturation_block1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Inverse_Clarke_Transform.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Inverse_Clarke_Transform
// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Clarke_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Inverse_Clarke_Transform
(
alpha_voltage,
beta_voltage,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2
);
input signed [17:0] alpha_voltage; // sfix18_En10
input signed [17:0] beta_voltage; // sfix18_En10
output signed [17:0] phase_voltages_0; // sfix18_En13
output signed [17:0] phase_voltages_1; // sfix18_En13
output signed [17:0] phase_voltages_2; // sfix18_En13
wire signed [35:0] voltage_phase_a; // sfix36_En26
wire signed [35:0] Gain1_out1; // sfix36_En26
wire signed [35:0] Gain_out1; // sfix36_En26
wire signed [35:0] voltage_phase_b; // sfix36_En26
wire signed [37:0] Add1_cast; // sfix38_En26
wire signed [37:0] Add1_cast_1; // sfix38_En26
wire signed [37:0] Add1_sub_cast; // sfix38_En26
wire signed [37:0] Add1_sub_temp; // sfix38_En26
wire signed [35:0] voltage_phase_c; // sfix36_En26
wire signed [35:0] Mux_out1 [0:2]; // sfix36_En26 [3]
wire signed [17:0] Current_Data_Type_out1 [0:2]; // sfix18_En13 [3]
// Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities
// The alpha and beta components are dependent on time and speed.
//
// Inverse Clarke Transform
// <S43>/Data Type Conversion
assign voltage_phase_a = {{2{alpha_voltage[17]}}, {alpha_voltage, 16'b0000000000000000}};
// <S43>/Gain1
assign Gain1_out1 = 56756 * beta_voltage;
// <S43>/Gain
assign Gain_out1 = {{3{alpha_voltage[17]}}, {alpha_voltage, 15'b000000000000000}};
// <S43>/Add
assign voltage_phase_b = Gain1_out1 - Gain_out1;
// <S43>/Add1
assign Add1_cast = Gain_out1;
assign Add1_cast_1 = - (Add1_cast);
assign Add1_sub_cast = Gain1_out1;
assign Add1_sub_temp = Add1_cast_1 - Add1_sub_cast;
assign voltage_phase_c = Add1_sub_temp[35:0];
// <S43>/Mux
assign Mux_out1[0] = voltage_phase_a;
assign Mux_out1[1] = voltage_phase_b;
assign Mux_out1[2] = voltage_phase_c;
// <S43>/Current_Data_Type
assign Current_Data_Type_out1[0] = ((Mux_out1[0][35] == 1'b0) && (Mux_out1[0][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[0][35] == 1'b1) && (Mux_out1[0][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[0][30:13])));
assign Current_Data_Type_out1[1] = ((Mux_out1[1][35] == 1'b0) && (Mux_out1[1][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[1][35] == 1'b1) && (Mux_out1[1][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[1][30:13])));
assign Current_Data_Type_out1[2] = ((Mux_out1[2][35] == 1'b0) && (Mux_out1[2][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[2][35] == 1'b1) && (Mux_out1[2][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[2][30:13])));
assign phase_voltages_0 = Current_Data_Type_out1[0];
assign phase_voltages_1 = Current_Data_Type_out1[1];
assign phase_voltages_2 = Current_Data_Type_out1[2];
endmodule // velocityControlHdl_Inverse_Clarke_Transform

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Inverse_Park_Transform.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Inverse_Park_Transform
// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Park_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Inverse_Park_Transform
(
direct_voltage,
quadrature_voltage,
sin_coefficient,
cos_coefficient,
alpha_voltage,
beta_voltage
);
input signed [17:0] direct_voltage; // sfix18_En12
input signed [17:0] quadrature_voltage; // sfix18_En12
input signed [17:0] sin_coefficient; // sfix18_En16
input signed [17:0] cos_coefficient; // sfix18_En16
output signed [17:0] alpha_voltage; // sfix18_En10
output signed [17:0] beta_voltage; // sfix18_En10
wire signed [35:0] Product2_out1; // sfix36_En28
wire signed [35:0] Product3_out1; // sfix36_En28
wire signed [35:0] alpha_voltage_1; // sfix36_En28
wire signed [17:0] Convert_Data_Type_out1; // sfix18_En10
wire signed [35:0] Product_out1; // sfix36_En28
wire signed [35:0] Product1_out1; // sfix36_En28
wire signed [35:0] beta_voltage_1; // sfix36_En28
wire signed [17:0] Convert_Data_Type1_out1; // sfix18_En10
// Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta)
//
// Inverse Park Transform
// <S44>/Product2
assign Product2_out1 = direct_voltage * cos_coefficient;
// <S44>/Product3
assign Product3_out1 = quadrature_voltage * sin_coefficient;
// <S44>/Add1
assign alpha_voltage_1 = Product2_out1 - Product3_out1;
// <S44>/Convert_Data_Type
velocityControlHdl_Convert_Data_Type_block1 u_Convert_Data_Type (.In1(alpha_voltage_1), // sfix36_En28
.Out1(Convert_Data_Type_out1) // sfix18_En10
);
assign alpha_voltage = Convert_Data_Type_out1;
// <S44>/Product
assign Product_out1 = direct_voltage * sin_coefficient;
// <S44>/Product1
assign Product1_out1 = quadrature_voltage * cos_coefficient;
// <S44>/Add
assign beta_voltage_1 = Product_out1 + Product1_out1;
// <S44>/Convert_Data_Type1
velocityControlHdl_Convert_Data_Type1_block1 u_Convert_Data_Type1 (.In1(beta_voltage_1), // sfix36_En28
.Out1(Convert_Data_Type1_out1) // sfix18_En10
);
assign beta_voltage = Convert_Data_Type1_out1;
endmodule // velocityControlHdl_Inverse_Park_Transform

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MATLAB_Function.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_MATLAB_Function
// Source Path: velocityControlHdl/Sin_Cos1/Mark_Extract_Bits/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_MATLAB_Function
(
u,
y
);
input [17:0] u; // ufix18
output [8:0] y; // ufix9
wire [8:0] y1; // ufix9_E9
//MATLAB Function 'Sin_Cos/Mark_Extract_Bits/MATLAB Function': '<S38>:1'
// Non-tunable mask parameter
//'<S38>:1:8'
//'<S38>:1:10'
assign y1 = u[17:9];
//'<S38>:1:14'
assign y = y1;
endmodule // velocityControlHdl_MATLAB_Function

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MATLAB_Function_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_MATLAB_Function_block
// Source Path: velocityControlHdl/Sin_Cos1/Mark_Extract_Bits1/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_MATLAB_Function_block
(
u,
y
);
input [17:0] u; // ufix18
output [8:0] y; // ufix9
//MATLAB Function 'Sin_Cos/Mark_Extract_Bits1/MATLAB Function': '<S39>:1'
// Non-tunable mask parameter
//'<S39>:1:8'
//'<S39>:1:10'
assign y = u[8:0];
//'<S39>:1:14'
endmodule // velocityControlHdl_MATLAB_Function_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Maintain_Range.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Maintain_Range
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Maintain_Range
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Maintain_Range
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En33
output signed [17:0] Out1; // sfix18_En15
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En15
// <S11>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[35:18];
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Maintain_Range

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Maintain_Range_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Maintain_Range_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Maintain_Range
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Maintain_Range_block
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En33
output signed [17:0] Out1; // sfix18_En15
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En15
// <S19>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[35:18];
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Maintain_Range_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Maintain_Range_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Maintain_Range_block1
// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Maintain_Range
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Maintain_Range_block1
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En46
output signed [17:0] Out1; // sfix18_En28
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En28
// <S28>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[35:18];
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Maintain_Range_block1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Mark_Extract_Bits.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Mark_Extract_Bits
// Source Path: velocityControlHdl/Sin_Cos1/Mark_Extract_Bits
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Mark_Extract_Bits
(
In1,
Out1
);
input [17:0] In1; // ufix18
output [8:0] Out1; // ufix9
wire [8:0] MATLAB_Function_out1; // ufix9
// <S36>/MATLAB Function
velocityControlHdl_MATLAB_Function u_MATLAB_Function (.u(In1), // ufix18
.y(MATLAB_Function_out1) // ufix9
);
assign Out1 = MATLAB_Function_out1;
endmodule // velocityControlHdl_Mark_Extract_Bits

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Mark_Extract_Bits1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Mark_Extract_Bits1
// Source Path: velocityControlHdl/Sin_Cos1/Mark_Extract_Bits1
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Mark_Extract_Bits1
(
In1,
Out1
);
input [17:0] In1; // ufix18
output [8:0] Out1; // ufix9
wire [8:0] MATLAB_Function_out1; // ufix9
// <S37>/MATLAB Function
velocityControlHdl_MATLAB_Function_block u_MATLAB_Function (.u(In1), // ufix18
.y(MATLAB_Function_out1) // ufix9
);
assign Out1 = MATLAB_Function_out1;
endmodule // velocityControlHdl_Mark_Extract_Bits1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MinMax.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_MinMax
// Source Path: velocityControlHdl/Space_Vector_Modulation/MinMax
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_MinMax
(
in0,
in1,
in2,
out0
);
input signed [17:0] in0; // sfix18_En12
input signed [17:0] in1; // sfix18_En12
input signed [17:0] in2; // sfix18_En12
output signed [17:0] out0; // sfix18_En12
wire signed [17:0] MinMax_muxout [0:2]; // sfix18_En12 [3]
wire signed [17:0] MinMax_stage1_val [0:1]; // sfix18_En12 [2]
wire signed [17:0] MinMax_stage2_val; // sfix18_En12
assign MinMax_muxout[0] = in0;
assign MinMax_muxout[1] = in1;
assign MinMax_muxout[2] = in2;
// ---- Tree min implementation ----
// ---- Tree min stage 1 ----
assign MinMax_stage1_val[0] = (MinMax_muxout[0] <= MinMax_muxout[1] ? MinMax_muxout[0] :
MinMax_muxout[1]);
assign MinMax_stage1_val[1] = MinMax_muxout[2];
// ---- Tree min stage 2 ----
assign MinMax_stage2_val = (MinMax_stage1_val[0] <= MinMax_stage1_val[1] ? MinMax_stage1_val[0] :
MinMax_stage1_val[1]);
assign out0 = MinMax_stage2_val;
endmodule // velocityControlHdl_MinMax

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MinMax1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_MinMax1
// Source Path: velocityControlHdl/Space_Vector_Modulation/MinMax1
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_MinMax1
(
in0,
in1,
in2,
out0
);
input signed [17:0] in0; // sfix18_En12
input signed [17:0] in1; // sfix18_En12
input signed [17:0] in2; // sfix18_En12
output signed [17:0] out0; // sfix18_En12
wire signed [17:0] MinMax1_muxout [0:2]; // sfix18_En12 [3]
wire signed [17:0] MinMax1_stage1_val [0:1]; // sfix18_En12 [2]
wire signed [17:0] MinMax1_stage2_val; // sfix18_En12
assign MinMax1_muxout[0] = in0;
assign MinMax1_muxout[1] = in1;
assign MinMax1_muxout[2] = in2;
// ---- Tree max implementation ----
// ---- Tree max stage 1 ----
assign MinMax1_stage1_val[0] = (MinMax1_muxout[0] >= MinMax1_muxout[1] ? MinMax1_muxout[0] :
MinMax1_muxout[1]);
assign MinMax1_stage1_val[1] = MinMax1_muxout[2];
// ---- Tree max stage 2 ----
assign MinMax1_stage2_val = (MinMax1_stage1_val[0] >= MinMax1_stage1_val[1] ? MinMax1_stage1_val[0] :
MinMax1_stage1_val[1]);
assign out0 = MinMax1_stage2_val;
endmodule // velocityControlHdl_MinMax1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_PI_Sat.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_PI_Sat
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/PI_Sat
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_PI_Sat
(
In1,
Out1,
saturated
);
input signed [35:0] In1; // sfix36_En23
output signed [35:0] Out1; // sfix36_En23
output saturated;
wire signed [17:0] PI_Sat_out1; // sfix18_En13
wire signed [18:0] Unary_Minus_cast; // sfix19_En13
wire signed [18:0] Unary_Minus_cast_1; // sfix19_En13
wire signed [17:0] Unary_Minus_out1; // sfix18_En13
wire signed [35:0] Dynamic_Saturation_out1; // sfix36_En23
wire Dynamic_Saturation_out2;
// <S12>/PI_Sat
assign PI_Sat_out1 = 18'sb010101100110011010;
// <S12>/Unary Minus
assign Unary_Minus_cast = PI_Sat_out1;
assign Unary_Minus_cast_1 = - (Unary_Minus_cast);
assign Unary_Minus_out1 = Unary_Minus_cast_1[17:0];
// <S12>/Dynamic Saturation
velocityControlHdl_Dynamic_Saturation u_Dynamic_Saturation (.up(PI_Sat_out1), // sfix18_En13
.u(In1), // sfix36_En23
.lo(Unary_Minus_out1), // sfix18_En13
.y(Dynamic_Saturation_out1), // sfix36_En23
.sat_mode(Dynamic_Saturation_out2)
);
assign Out1 = Dynamic_Saturation_out1;
assign saturated = Dynamic_Saturation_out2;
endmodule // velocityControlHdl_PI_Sat

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_PI_Sat_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_PI_Sat_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/PI_Sat
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_PI_Sat_block
(
In1,
Out1,
saturated
);
input signed [35:0] In1; // sfix36_En23
output signed [35:0] Out1; // sfix36_En23
output saturated;
wire signed [17:0] PI_Sat_out1; // sfix18_En13
wire signed [18:0] Unary_Minus_cast; // sfix19_En13
wire signed [18:0] Unary_Minus_cast_1; // sfix19_En13
wire signed [17:0] Unary_Minus_out1; // sfix18_En13
wire signed [35:0] Dynamic_Saturation_out1; // sfix36_En23
wire Dynamic_Saturation_out2;
// <S20>/PI_Sat
assign PI_Sat_out1 = 18'sb010101100110011010;
// <S20>/Unary Minus
assign Unary_Minus_cast = PI_Sat_out1;
assign Unary_Minus_cast_1 = - (Unary_Minus_cast);
assign Unary_Minus_out1 = Unary_Minus_cast_1[17:0];
// <S20>/Dynamic Saturation
velocityControlHdl_Dynamic_Saturation_block u_Dynamic_Saturation (.up(PI_Sat_out1), // sfix18_En13
.u(In1), // sfix36_En23
.lo(Unary_Minus_out1), // sfix18_En13
.y(Dynamic_Saturation_out1), // sfix36_En23
.sat_mode(Dynamic_Saturation_out2)
);
assign Out1 = Dynamic_Saturation_out1;
assign saturated = Dynamic_Saturation_out2;
endmodule // velocityControlHdl_PI_Sat_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_PI_Sat_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_PI_Sat_block1
// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/PI_Sat
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_PI_Sat_block1
(
In1,
Out1,
saturated
);
input signed [35:0] In1; // sfix36_En22
output signed [35:0] Out1; // sfix36_En22
output saturated;
wire signed [17:0] PI_Sat_out1; // sfix18_En15
wire signed [18:0] Unary_Minus_cast; // sfix19_En15
wire signed [18:0] Unary_Minus_cast_1; // sfix19_En15
wire signed [17:0] Unary_Minus_out1; // sfix18_En15
wire signed [35:0] Dynamic_Saturation_out1; // sfix36_En22
wire Dynamic_Saturation_out2;
// <S29>/PI_Sat
assign PI_Sat_out1 = 18'sb010101100110011010;
// <S29>/Unary Minus
assign Unary_Minus_cast = PI_Sat_out1;
assign Unary_Minus_cast_1 = - (Unary_Minus_cast);
assign Unary_Minus_out1 = Unary_Minus_cast_1[17:0];
// <S29>/Dynamic Saturation
velocityControlHdl_Dynamic_Saturation_block1 u_Dynamic_Saturation (.up(PI_Sat_out1), // sfix18_En15
.u(In1), // sfix36_En22
.lo(Unary_Minus_out1), // sfix18_En15
.y(Dynamic_Saturation_out1), // sfix36_En22
.sat_mode(Dynamic_Saturation_out2)
);
assign Out1 = Dynamic_Saturation_out1;
assign saturated = Dynamic_Saturation_out2;
endmodule // velocityControlHdl_PI_Sat_block1

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Park_Transform.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Park_Transform
// Source Path: velocityControlHdl/Transform_ABC_to_dq/Park_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Park_Transform
(
sin_coefficient,
cos_coefficient,
alpha_current,
beta_current,
direct_current,
quadrature_current
);
input signed [17:0] sin_coefficient; // sfix18_En16
input signed [17:0] cos_coefficient; // sfix18_En16
input signed [17:0] alpha_current; // sfix18_En13
input signed [17:0] beta_current; // sfix18_En13
output signed [17:0] direct_current; // sfix18_En15
output signed [17:0] quadrature_current; // sfix18_En15
wire signed [35:0] Product2_out1; // sfix36_En29
wire signed [35:0] Product3_out1; // sfix36_En29
wire signed [35:0] Add1_out1; // sfix36_En29
wire signed [17:0] D_Data_Type_out1; // sfix18_En15
wire signed [35:0] Product1_out1; // sfix36_En29
wire signed [35:0] Product_out1; // sfix36_En29
wire signed [35:0] Add_out1; // sfix36_En29
wire signed [17:0] Q_Data_Type_out1; // sfix18_En15
// Converts balanced two-phase orthogonal stationary system to an orthogonal rotating reference frame.
//
// Park Transform
// <S42>/Product2
assign Product2_out1 = alpha_current * cos_coefficient;
// <S42>/Product3
assign Product3_out1 = beta_current * sin_coefficient;
// <S42>/Add1
assign Add1_out1 = Product2_out1 + Product3_out1;
// <S42>/D_Data_Type
assign D_Data_Type_out1 = ((Add1_out1[35] == 1'b0) && (Add1_out1[34:31] != 4'b0000) ? 18'sb011111111111111111 :
((Add1_out1[35] == 1'b1) && (Add1_out1[34:31] != 4'b1111) ? 18'sb100000000000000000 :
$signed(Add1_out1[31:14])));
assign direct_current = D_Data_Type_out1;
// <S42>/Product1
assign Product1_out1 = beta_current * cos_coefficient;
// <S42>/Product
assign Product_out1 = alpha_current * sin_coefficient;
// <S42>/Add
assign Add_out1 = Product1_out1 - Product_out1;
// <S42>/Q_Data_Type
assign Q_Data_Type_out1 = ((Add_out1[35] == 1'b0) && (Add_out1[34:31] != 4'b0000) ? 18'sb011111111111111111 :
((Add_out1[35] == 1'b1) && (Add_out1[34:31] != 4'b1111) ? 18'sb100000000000000000 :
$signed(Add_out1[31:14])));
assign quadrature_current = Q_Data_Type_out1;
endmodule // velocityControlHdl_Park_Transform

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Reset_Delay.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Reset_Delay
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Reset_Delay
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Reset_Delay
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
In,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [31:0] In; // sfix32_En26
output signed [31:0] Out; // sfix32_En26
wire signed [31:0] Constant1_out1; // sfix32_En26
wire signed [31:0] Reset_Switch1_out1; // sfix32_En26
reg signed [31:0] In_Delay_out1; // sfix32_En26
wire signed [31:0] Constant_out1; // sfix32_En26
wire signed [31:0] Reset_Switch_out1; // sfix32_En26
// <S13>/Constant1
assign Constant1_out1 = 32'sb00000000000000000000000000000000;
// <S13>/Reset_Switch1
assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In :
Constant1_out1);
// <S13>/In_Delay
always @(posedge CLK_IN)
begin : In_Delay_process
if (reset == 1'b1) begin
In_Delay_out1 <= 32'sb00000000000000000000000000000000;
end
else if (enb_1_2000_0) begin
In_Delay_out1 <= Reset_Switch1_out1;
end
end
// <S13>/Constant
assign Constant_out1 = 32'sb00000000000000000000000000000000;
// <S13>/Reset_Switch
assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 :
Constant_out1);
assign Out = Reset_Switch_out1;
endmodule // velocityControlHdl_Reset_Delay

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Reset_Delay_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Reset_Delay_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Reset_Delay
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Reset_Delay_block
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
In,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [31:0] In; // sfix32_En26
output signed [31:0] Out; // sfix32_En26
wire signed [31:0] Constant1_out1; // sfix32_En26
wire signed [31:0] Reset_Switch1_out1; // sfix32_En26
reg signed [31:0] In_Delay_out1; // sfix32_En26
wire signed [31:0] Constant_out1; // sfix32_En26
wire signed [31:0] Reset_Switch_out1; // sfix32_En26
// <S21>/Constant1
assign Constant1_out1 = 32'sb00000000000000000000000000000000;
// <S21>/Reset_Switch1
assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In :
Constant1_out1);
// <S21>/In_Delay
always @(posedge CLK_IN)
begin : In_Delay_process
if (reset == 1'b1) begin
In_Delay_out1 <= 32'sb00000000000000000000000000000000;
end
else if (enb_1_2000_0) begin
In_Delay_out1 <= Reset_Switch1_out1;
end
end
// <S21>/Constant
assign Constant_out1 = 32'sb00000000000000000000000000000000;
// <S21>/Reset_Switch
assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 :
Constant_out1);
assign Out = Reset_Switch_out1;
endmodule // velocityControlHdl_Reset_Delay_block

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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Reset_Delay_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Reset_Delay_block1
// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Reset_Delay
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Reset_Delay_block1
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
In,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [31:0] In; // sfix32_En28
output signed [31:0] Out; // sfix32_En28
wire signed [31:0] Constant1_out1; // sfix32_En28
wire signed [31:0] Reset_Switch1_out1; // sfix32_En28
reg signed [31:0] In_Delay_out1; // sfix32_En28
wire signed [31:0] Constant_out1; // sfix32_En28
wire signed [31:0] Reset_Switch_out1; // sfix32_En28
// <S30>/Constant1
assign Constant1_out1 = 32'sb00000000000000000000000000000000;
// <S30>/Reset_Switch1
assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In :
Constant1_out1);
// <S30>/In_Delay
always @(posedge CLK_IN)
begin : In_Delay_process
if (reset == 1'b1) begin
In_Delay_out1 <= 32'sb00000000000000000000000000000000;
end
else if (enb_1_2000_0) begin
In_Delay_out1 <= Reset_Switch1_out1;
end
end
// <S30>/Constant
assign Constant_out1 = 32'sb00000000000000000000000000000000;
// <S30>/Reset_Switch
assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 :
Constant_out1);
assign Out = Reset_Switch_out1;
endmodule // velocityControlHdl_Reset_Delay_block1

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