diff --git a/library/axi_mc_controller/axi_mc_controller.v b/library/axi_mc_controller/axi_mc_controller.v index e29a5f5e8..a0e05dd57 100755 --- a/library/axi_mc_controller/axi_mc_controller.v +++ b/library/axi_mc_controller/axi_mc_controller.v @@ -45,6 +45,7 @@ module axi_mc_controller ) ( input ref_clk, // 100 MHz + input ctrl_data_clk, // physical interface @@ -60,29 +61,55 @@ module axi_mc_controller // controller connections - input [31:0] err_i, - input [31:0] pwm_i, - input [31:0] speed_rpm_i, - output ctrl_rst_o, - output [31:0] ref_speed_o, - output [31:0] kp_o, - output [31:0] ki_o, - output [31:0] kd_o, + input pwm_a_i, + input pwm_b_i, + input pwm_c_i, + input ctrl_data_valid_i, + input [31:0] ctrl_data0_i, + input [31:0] ctrl_data1_i, + input [31:0] ctrl_data2_i, + input [31:0] ctrl_data3_i, + input [31:0] ctrl_data4_i, + input [31:0] ctrl_data5_i, + input [31:0] ctrl_data6_i, + input [31:0] ctrl_data7_i, // interconnection with other modules output [1:0] sensors_o, input [2:0] position_i, - input new_speed_i, - input [31:0] speed_i, // dma interface output adc_clk_o, - output adc_dwr_o, - output [31:0] adc_ddata_o, input adc_dovf_i, input adc_dunf_i, + output adc_enable_c0, + output adc_enable_c1, + output adc_enable_c2, + output adc_enable_c3, + output adc_enable_c4, + output adc_enable_c5, + output adc_enable_c6, + output adc_enable_c7, + + output adc_valid_c0, + output adc_valid_c1, + output adc_valid_c2, + output adc_valid_c3, + output adc_valid_c4, + output adc_valid_c5, + output adc_valid_c6, + output adc_valid_c7, + + output [31:0] adc_data_c0, + output [31:0] adc_data_c1, + output [31:0] adc_data_c2, + output [31:0] adc_data_c3, + output [31:0] adc_data_c4, + output [31:0] adc_data_c5, + output [31:0] adc_data_c6, + output [31:0] adc_data_c7, // axi interface @@ -104,12 +131,7 @@ module axi_mc_controller output s_axi_rvalid, output [1:0] s_axi_rresp, output [31:0] s_axi_rdata, - input s_axi_rready, - -// debug signals - - output adc_mon_valid, - output [31:0] adc_mon_data + input s_axi_rready ); //------------------------------------------------------------------------------ @@ -141,24 +163,41 @@ wire [13:0] up_addr_s; wire [31:0] up_wdata_s; wire [31:0] up_adc_common_rdata_s; wire [31:0] up_control_rdata_s; -wire [31:0] rdata_ref_speed_s; -wire [31:0] rdata_actual_speed_s; +wire [31:0] rdata_c0_s; +wire [31:0] rdata_c1_s; +wire [31:0] rdata_c2_s; +wire [31:0] rdata_c3_s; +wire [31:0] rdata_c4_s; +wire [31:0] rdata_c5_s; +wire [31:0] rdata_c6_s; +wire [31:0] rdata_c7_s; wire up_adc_common_ack_s; wire up_control_ack_s; -wire ack_ref_speed_s; -wire ack_actual_speed_s; +wire ack_c0_s; +wire ack_c1_s; +wire ack_c2_s; +wire ack_c3_s; +wire ack_c4_s; +wire ack_c5_s; +wire ack_c6_s; +wire ack_c7_s; wire run_s; wire star_delta_s; -wire oloop_matlab_s; // 0 - open loop, 1 matlab controlls pwm wire dir_s; wire [10:0] pwm_open_s; wire [10:0] pwm_s; -wire enable_ref_speed_s; -wire enable_actual_speed_s; - wire [10:0] gpo_s; +wire dpwm_ah_s; +wire dpwm_al_s; +wire dpwm_bh_s; +wire dpwm_bl_s; +wire dpwm_ch_s; +wire dpwm_cl_s; + +wire foc_ctrl_s; + //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ @@ -168,19 +207,40 @@ wire [10:0] gpo_s; assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; -assign adc_clk_o = ref_clk; -assign adc_dwr_o = adc_valid; -assign adc_ddata_o = adc_data; +assign adc_clk_o = ctrl_data_clk; + +assign adc_valid_c0 = ctrl_data_valid_i; +assign adc_valid_c1 = ctrl_data_valid_i; +assign adc_valid_c2 = ctrl_data_valid_i; +assign adc_valid_c3 = ctrl_data_valid_i; +assign adc_valid_c4 = ctrl_data_valid_i; +assign adc_valid_c5 = ctrl_data_valid_i; +assign adc_valid_c6 = ctrl_data_valid_i; +assign adc_valid_c7 = ctrl_data_valid_i; + +assign adc_data_c0 = ctrl_data0_i; +assign adc_data_c1 = ctrl_data1_i; +assign adc_data_c2 = ctrl_data2_i; +assign adc_data_c3 = ctrl_data3_i; +assign adc_data_c4 = ctrl_data4_i; +assign adc_data_c5 = ctrl_data5_i; +assign adc_data_c6 = ctrl_data6_i; +assign adc_data_c7 = ctrl_data7_i; + assign ctrl_rst_o = !run_s; // monitor signals -assign adc_mon_valid = adc_valid; -assign adc_mon_data = {25'h0 ,fmc_m1_en_o, pwm_ah_o, pwm_al_o, pwm_bh_o, pwm_bl_o, pwm_ch_o, pwm_cl_o}; - assign fmc_m1_en_o = run_s; -assign pwm_s = oloop_matlab_s ? pwm_i[10:0] : pwm_open_s ; +assign pwm_s = pwm_open_s ; + +assign pwm_ah_o = foc_ctrl_s ? !pwm_a_i : dpwm_ah_s; +assign pwm_al_o = foc_ctrl_s ? pwm_a_i : dpwm_al_s; +assign pwm_bh_o = foc_ctrl_s ? !pwm_b_i : dpwm_bh_s; +assign pwm_bl_o = foc_ctrl_s ? pwm_b_i : dpwm_bl_s; +assign pwm_ch_o = foc_ctrl_s ? !pwm_c_i : dpwm_ch_s; +assign pwm_cl_o = foc_ctrl_s ? pwm_c_i : dpwm_cl_s; // assign gpo @@ -194,57 +254,6 @@ begin pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk end -// adc channels - dma interface - -always @(posedge ref_clk) -begin - if(new_speed_i == 1) - begin - case({enable_actual_speed_s , enable_ref_speed_s}) - 2'b11: - begin - adc_data <= {speed_rpm_i[31:16], ref_speed_o[15:0]}; - adc_valid <= 1'b1; - end - 2'b01: - begin - adc_data <= { adc_data[15:0], ref_speed_o[15:0]}; - one_chan_reg <= ~one_chan_reg; - if(one_chan_reg == 1'b1) - begin - adc_valid <= 1'b1; - end - else - begin - adc_valid <= 1'b0; - end - end - 2'b10: - begin - adc_data <= { adc_data[15:0], speed_rpm_i[31:16]}; - one_chan_reg <= ~one_chan_reg; - if(one_chan_reg == 1'b1) - begin - adc_valid <= 1'b1; - end - else - begin - adc_valid <= 1'b0; - end - end - 2'b00: - begin - adc_data <= 32'hdeadbeef; - adc_valid <= 1'b1; - end - endcase - end - else - begin - adc_data <= adc_data; - adc_valid <= 1'b0; - end -end // processor read interface @@ -253,8 +262,8 @@ always @(negedge up_rstn or posedge up_clk) begin up_rdata <= 'd0; up_ack <= 'd0; end else begin - up_rdata <= up_control_rdata_s | up_adc_common_rdata_s | rdata_ref_speed_s | rdata_actual_speed_s ; - up_ack <= up_control_ack_s | up_adc_common_ack_s | ack_ref_speed_s | ack_actual_speed_s; + up_rdata <= up_control_rdata_s | up_adc_common_rdata_s | rdata_c0_s | rdata_c1_s | rdata_c2_s | rdata_c3_s | rdata_c4_s | rdata_c5_s | rdata_c6_s | rdata_c7_s; + up_ack <= up_control_ack_s | up_adc_common_ack_s | ack_c0_s | ack_c1_s | ack_c2_s | ack_c3_s | ack_c4_s | ack_c5_s | ack_c6_s | ack_c7_s; end end @@ -271,12 +280,12 @@ motor_driver_inst( .dir_i(dir_s), .position_i(position_i), .pwm_duty_i(pwm_s), - .AH_o(pwm_ah_o), - .BH_o(pwm_bh_o), - .CH_o(pwm_ch_o), - .AL_o(pwm_al_o), - .BL_o(pwm_bl_o), - .CL_o(pwm_cl_o)); + .AH_o(dpwm_ah_s), + .BH_o(dpwm_bh_s), + .CH_o(dpwm_ch_s), + .AL_o(dpwm_al_s), + .BL_o(dpwm_bl_s), + .CL_o(dpwm_cl_s)); control_registers control_reg_inst( .up_rstn(up_rstn), @@ -301,15 +310,15 @@ control_registers control_reg_inst( .kd1_o(), .gpo_o(gpo_s), .reference_speed_o(ref_speed_o), - .oloop_matlab_o(oloop_matlab_s), + .oloop_matlab_o(foc_ctrl_s), .err_i(err_i), .calibrate_adcs_o(), .pwm_open_o( pwm_open_s)); -up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel_ref_speed( +up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0( .adc_clk(ref_clk), .adc_rst(adc_rst), - .adc_enable(enable_ref_speed_s), + .adc_enable(adc_enable_c0), .adc_iqcor_enb(), .adc_dcfilt_enb(), .adc_dfmt_se(), @@ -345,13 +354,13 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel_ref_speed( .up_wr(up_wr_s), .up_addr(up_addr_s), .up_wdata(up_wdata_s), - .up_rdata(rdata_ref_speed_s), - .up_ack(ack_ref_speed_s)); + .up_rdata(rdata_c0_s), + .up_ack(ack_c0_s)); -up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel_actual_speed( +up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1( .adc_clk(ref_clk), .adc_rst(adc_rst), - .adc_enable(enable_actual_speed_s), + .adc_enable(adc_enable_c1), .adc_iqcor_enb(), .adc_dcfilt_enb(), .adc_dfmt_se(), @@ -387,9 +396,261 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel_actual_speed( .up_wr(up_wr_s), .up_addr(up_addr_s), .up_wdata(up_wdata_s), - .up_rdata(rdata_actual_speed_s), - .up_ack(ack_actual_speed_s)); + .up_rdata(rdata_c1_s), + .up_ack(ack_c1_s)); + +up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2( + .adc_clk(ref_clk), + .adc_rst(adc_rst), + .adc_enable(adc_enable_c2), + .adc_iqcor_enb(), + .adc_dcfilt_enb(), + .adc_dfmt_se(), + .adc_dfmt_type(), + .adc_dfmt_enable(), + .adc_dcfilt_offset(), + .adc_dcfilt_coeff(), + .adc_iqcor_coeff_1(), + .adc_iqcor_coeff_2(), + .adc_pn_err(1'b0), + .adc_pn_oos(1'b0), + .adc_or(1'b0), + .up_adc_pn_err(), + .up_adc_pn_oos(), + .up_adc_or(), + .up_usr_datatype_be(), + .up_usr_datatype_signed(), + .up_usr_datatype_shift(), + .up_usr_datatype_total_bits(), + .up_usr_datatype_bits(), + .up_usr_decimation_m(), + .up_usr_decimation_n(), + .adc_usr_datatype_be(1'b0), + .adc_usr_datatype_signed(1'b1), + .adc_usr_datatype_shift(8'd0), + .adc_usr_datatype_total_bits(8'd16), + .adc_usr_datatype_bits(8'd16), + .adc_usr_decimation_m(16'd1), + .adc_usr_decimation_n(16'd1), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_sel(up_sel_s), + .up_wr(up_wr_s), + .up_addr(up_addr_s), + .up_wdata(up_wdata_s), + .up_rdata(rdata_c2_s), + .up_ack(ack_c2_s)); +up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3( + .adc_clk(ref_clk), + .adc_rst(adc_rst), + .adc_enable(adc_enable_c3), + .adc_iqcor_enb(), + .adc_dcfilt_enb(), + .adc_dfmt_se(), + .adc_dfmt_type(), + .adc_dfmt_enable(), + .adc_dcfilt_offset(), + .adc_dcfilt_coeff(), + .adc_iqcor_coeff_1(), + .adc_iqcor_coeff_2(), + .adc_pn_err(1'b0), + .adc_pn_oos(1'b0), + .adc_or(1'b0), + .up_adc_pn_err(), + .up_adc_pn_oos(), + .up_adc_or(), + .up_usr_datatype_be(), + .up_usr_datatype_signed(), + .up_usr_datatype_shift(), + .up_usr_datatype_total_bits(), + .up_usr_datatype_bits(), + .up_usr_decimation_m(), + .up_usr_decimation_n(), + .adc_usr_datatype_be(1'b0), + .adc_usr_datatype_signed(1'b1), + .adc_usr_datatype_shift(8'd0), + .adc_usr_datatype_total_bits(8'd16), + .adc_usr_datatype_bits(8'd16), + .adc_usr_decimation_m(16'd1), + .adc_usr_decimation_n(16'd1), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_sel(up_sel_s), + .up_wr(up_wr_s), + .up_addr(up_addr_s), + .up_wdata(up_wdata_s), + .up_rdata(rdata_c3_s), + .up_ack(ack_c3_s)); + +up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4( + .adc_clk(ref_clk), + .adc_rst(adc_rst), + .adc_enable(adc_enable_c4), + .adc_iqcor_enb(), + .adc_dcfilt_enb(), + .adc_dfmt_se(), + .adc_dfmt_type(), + .adc_dfmt_enable(), + .adc_dcfilt_offset(), + .adc_dcfilt_coeff(), + .adc_iqcor_coeff_1(), + .adc_iqcor_coeff_2(), + .adc_pn_err(1'b0), + .adc_pn_oos(1'b0), + .adc_or(1'b0), + .up_adc_pn_err(), + .up_adc_pn_oos(), + .up_adc_or(), + .up_usr_datatype_be(), + .up_usr_datatype_signed(), + .up_usr_datatype_shift(), + .up_usr_datatype_total_bits(), + .up_usr_datatype_bits(), + .up_usr_decimation_m(), + .up_usr_decimation_n(), + .adc_usr_datatype_be(1'b0), + .adc_usr_datatype_signed(1'b1), + .adc_usr_datatype_shift(8'd0), + .adc_usr_datatype_total_bits(8'd16), + .adc_usr_datatype_bits(8'd16), + .adc_usr_decimation_m(16'd1), + .adc_usr_decimation_n(16'd1), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_sel(up_sel_s), + .up_wr(up_wr_s), + .up_addr(up_addr_s), + .up_wdata(up_wdata_s), + .up_rdata(rdata_c4_s), + .up_ack(ack_c4_s)); + +up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5( + .adc_clk(ref_clk), + .adc_rst(adc_rst), + .adc_enable(adc_enable_c5), + .adc_iqcor_enb(), + .adc_dcfilt_enb(), + .adc_dfmt_se(), + .adc_dfmt_type(), + .adc_dfmt_enable(), + .adc_dcfilt_offset(), + .adc_dcfilt_coeff(), + .adc_iqcor_coeff_1(), + .adc_iqcor_coeff_2(), + .adc_pn_err(1'b0), + .adc_pn_oos(1'b0), + .adc_or(1'b0), + .up_adc_pn_err(), + .up_adc_pn_oos(), + .up_adc_or(), + .up_usr_datatype_be(), + .up_usr_datatype_signed(), + .up_usr_datatype_shift(), + .up_usr_datatype_total_bits(), + .up_usr_datatype_bits(), + .up_usr_decimation_m(), + .up_usr_decimation_n(), + .adc_usr_datatype_be(1'b0), + .adc_usr_datatype_signed(1'b1), + .adc_usr_datatype_shift(8'd0), + .adc_usr_datatype_total_bits(8'd16), + .adc_usr_datatype_bits(8'd16), + .adc_usr_decimation_m(16'd1), + .adc_usr_decimation_n(16'd1), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_sel(up_sel_s), + .up_wr(up_wr_s), + .up_addr(up_addr_s), + .up_wdata(up_wdata_s), + .up_rdata(rdata_c5_s), + .up_ack(ack_c5_s)); + +up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6( + .adc_clk(ref_clk), + .adc_rst(adc_rst), + .adc_enable(adc_enable_c6), + .adc_iqcor_enb(), + .adc_dcfilt_enb(), + .adc_dfmt_se(), + .adc_dfmt_type(), + .adc_dfmt_enable(), + .adc_dcfilt_offset(), + .adc_dcfilt_coeff(), + .adc_iqcor_coeff_1(), + .adc_iqcor_coeff_2(), + .adc_pn_err(1'b0), + .adc_pn_oos(1'b0), + .adc_or(1'b0), + .up_adc_pn_err(), + .up_adc_pn_oos(), + .up_adc_or(), + .up_usr_datatype_be(), + .up_usr_datatype_signed(), + .up_usr_datatype_shift(), + .up_usr_datatype_total_bits(), + .up_usr_datatype_bits(), + .up_usr_decimation_m(), + .up_usr_decimation_n(), + .adc_usr_datatype_be(1'b0), + .adc_usr_datatype_signed(1'b1), + .adc_usr_datatype_shift(8'd0), + .adc_usr_datatype_total_bits(8'd16), + .adc_usr_datatype_bits(8'd16), + .adc_usr_decimation_m(16'd1), + .adc_usr_decimation_n(16'd1), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_sel(up_sel_s), + .up_wr(up_wr_s), + .up_addr(up_addr_s), + .up_wdata(up_wdata_s), + .up_rdata(rdata_c6_s), + .up_ack(ack_c6_s)); + +up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7( + .adc_clk(ref_clk), + .adc_rst(adc_rst), + .adc_enable(adc_enable_c7), + .adc_iqcor_enb(), + .adc_dcfilt_enb(), + .adc_dfmt_se(), + .adc_dfmt_type(), + .adc_dfmt_enable(), + .adc_dcfilt_offset(), + .adc_dcfilt_coeff(), + .adc_iqcor_coeff_1(), + .adc_iqcor_coeff_2(), + .adc_pn_err(1'b0), + .adc_pn_oos(1'b0), + .adc_or(1'b0), + .up_adc_pn_err(), + .up_adc_pn_oos(), + .up_adc_or(), + .up_usr_datatype_be(), + .up_usr_datatype_signed(), + .up_usr_datatype_shift(), + .up_usr_datatype_total_bits(), + .up_usr_datatype_bits(), + .up_usr_decimation_m(), + .up_usr_decimation_n(), + .adc_usr_datatype_be(1'b0), + .adc_usr_datatype_signed(1'b1), + .adc_usr_datatype_shift(8'd0), + .adc_usr_datatype_total_bits(8'd16), + .adc_usr_datatype_bits(8'd16), + .adc_usr_decimation_m(16'd1), + .adc_usr_decimation_n(16'd1), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_sel(up_sel_s), + .up_wr(up_wr_s), + .up_addr(up_addr_s), + .up_wdata(up_wdata_s), + .up_rdata(rdata_c7_s), + .up_ack(ack_c7_s)); + // common processor control up_adc_common i_up_adc_common( diff --git a/library/axi_mc_current_monitor/axi_mc_current_monitor.v b/library/axi_mc_current_monitor/axi_mc_current_monitor.v index 5e57bfc4f..dc8fd7794 100755 --- a/library/axi_mc_current_monitor/axi_mc_current_monitor.v +++ b/library/axi_mc_current_monitor/axi_mc_current_monitor.v @@ -58,9 +58,9 @@ module axi_mc_current_monitor input ref_clk, - output [15:0] ia_o, - output [15:0] ib_o, - output [15:0] it_o, + output [17:0] ia_o, + output [17:0] ib_o, + output [17:0] it_o, output i_ready_o, // dma interface @@ -193,9 +193,9 @@ assign adc_mon_data[31:16] = {adc_enable_vbus, adc_enable_it, adc_enable_ib, ad // current outputs assign i_ready_o = data_rd_ready_ia_s; -assign ia_o = adc_data_ia_s; -assign ib_o = adc_data_ib_s; -assign it_o = adc_data_it_n_s; +assign ia_o = {adc_data_ia_s - 16'h7FFF, 2'b00}; +assign ib_o = {adc_data_ib_s - 16'h7FFF, 2'b00}; +assign it_o = {adc_data_it_s, 2'b00}; assign adc_data_it_n_s = 65535 - adc_data_it_s; // adc clock diff --git a/library/controllerperipheralhdladi_pcore/Chart.v b/library/controllerperipheralhdladi_pcore/Chart.v new file mode 100644 index 000000000..2ee360061 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/Chart.v @@ -0,0 +1,112 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Chart.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: Chart +// Source Path: controllerPeripheralHdlAdi/PWM/Chart +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module Chart + ( + CLK_IN, + reset, + enb, + CounterMax, + count + ); + + + input CLK_IN; + input reset; + input enb; + input [15:0] CounterMax; // uint16 + output [15:0] count; // uint16 + + parameter IN_COUNT_Down = 0, IN_COUNT_UP = 1; + + reg [1:0] is_libPwmCompareToPinsHdl_c1_Chart; // uint8 + reg [15:0] count_reg; // uint16 + reg [1:0] is_libPwmCompareToPinsHdl_c1_Chart_next; // enumerated type (2 enums) + reg [15:0] count_reg_next; // uint16 + reg [16:0] add_temp_1; // ufix17 + reg signed [16:0] sub_temp_1; // sfix17 + + + always @(posedge CLK_IN) + begin : libPwmCompareToPinsHdl_c1_Chart_process + if (reset == 1'b1) begin + //Entry: PWM_HDL/Chart + //Entry Internal: PWM_HDL/Chart + //Transition: ':5' + count_reg <= 16'd0; + is_libPwmCompareToPinsHdl_c1_Chart <= IN_COUNT_UP; + end + else if (enb) begin + is_libPwmCompareToPinsHdl_c1_Chart <= is_libPwmCompareToPinsHdl_c1_Chart_next; + count_reg <= count_reg_next; + end + end + + always @(is_libPwmCompareToPinsHdl_c1_Chart, CounterMax, count_reg) begin + is_libPwmCompareToPinsHdl_c1_Chart_next = is_libPwmCompareToPinsHdl_c1_Chart; + count_reg_next = count_reg; + //Gateway: PWM_HDL/Chart + //During: PWM_HDL/Chart + + case ( is_libPwmCompareToPinsHdl_c1_Chart) + IN_COUNT_Down : + begin + //During 'COUNT_Down': ':2' + if (count_reg <= 16'b0000000000000000) begin + //Transition: ':4' + is_libPwmCompareToPinsHdl_c1_Chart_next = IN_COUNT_UP; + end + else begin + sub_temp_1 = $signed({1'b0, count_reg}) - 1; + if (sub_temp_1[16] == 1'b1) begin + count_reg_next = 16'b0000000000000000; + end + else begin + count_reg_next = sub_temp_1[15:0]; + end + end + end + default : + begin + //During 'COUNT_UP': ':1' + if (count_reg >= CounterMax) begin + //Transition: ':3' + is_libPwmCompareToPinsHdl_c1_Chart_next = IN_COUNT_Down; + end + else begin + add_temp_1 = count_reg + 1; + if (add_temp_1[16] != 1'b0) begin + count_reg_next = 16'b1111111111111111; + end + else begin + count_reg_next = add_temp_1[15:0]; + end + end + end + endcase + + end + + assign count = count_reg_next; + + + +endmodule // Chart + diff --git a/library/controllerperipheralhdladi_pcore/Count_Up_Down.v b/library/controllerperipheralhdladi_pcore/Count_Up_Down.v new file mode 100644 index 000000000..f75de4478 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/Count_Up_Down.v @@ -0,0 +1,104 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Count_Up_Down.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: Count_Up_Down +// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_A/Count_Up_Down +// Hierarchy Level: 3 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module Count_Up_Down + ( + CLK_IN, + reset, + enb, + u, + count_debounce, + y + ); + + + input CLK_IN; + input reset; + input enb; + input u; + input [7:0] count_debounce; // uint8 + output y; + + + reg u_n1; + reg [7:0] count; // uint8 + reg y_reg; + reg u_n1_next; + reg [7:0] count_next; // uint8 + reg y_reg_next; + reg [8:0] add_temp_1; // ufix9 + + + always @(posedge CLK_IN) + begin : libDebounce_c2_Count_Up_Down_process + if (reset == 1'b1) begin + u_n1 <= 1'b0; + count <= 8'd0; + y_reg <= 1'b0; + end + else if (enb) begin + u_n1 <= u_n1_next; + count <= count_next; + y_reg <= y_reg_next; + end + end + + always @(u, u_n1, count, count_debounce, y_reg) begin + count_next = count; + y_reg_next = y_reg; + //Gateway: Debounce/Count_Up_Down + //During: Debounce/Count_Up_Down + //Entry Internal: Debounce/Count_Up_Down + //Transition: ':27' + if (u == u_n1) begin + //Transition: ':4' + //Transition: ':6' + if (count >= count_debounce) begin + //Transition: ':8' + //Transition: ':10' + y_reg_next = u; + //Transition: ':16' + end + else begin + //Transition: ':12' + add_temp_1 = count + 1; + if (add_temp_1[8] != 1'b0) begin + count_next = 8'b11111111; + end + else begin + count_next = add_temp_1[7:0]; + end + end + //Transition: ':15' + end + else begin + //Transition: ':14' + count_next = 8'd0; + end + //Transition: ':18' + u_n1_next = u; + end + + assign y = y_reg_next; + + + +endmodule // Count_Up_Down + diff --git a/library/controllerperipheralhdladi_pcore/Debounce_A.v b/library/controllerperipheralhdladi_pcore/Debounce_A.v new file mode 100644 index 000000000..ca3d1f364 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/Debounce_A.v @@ -0,0 +1,59 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Debounce_A.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: Debounce_A +// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_A +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module Debounce_A + ( + CLK_IN, + reset, + enb, + In, + Out + ); + + + input CLK_IN; + input reset; + input enb; + input In; + output Out; + + + wire [7:0] Debouce_Count_out1; // uint8 + wire Count_Up_Down_out1; + + + // /Debouce_Count + assign Debouce_Count_out1 = 8'd20; + + + + // /Count_Up_Down + Count_Up_Down u_Count_Up_Down (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .u(In), + .count_debounce(Debouce_Count_out1), // uint8 + .y(Count_Up_Down_out1) + ); + + assign Out = Count_Up_Down_out1; + +endmodule // Debounce_A + diff --git a/library/controllerperipheralhdladi_pcore/Debounce_B.v b/library/controllerperipheralhdladi_pcore/Debounce_B.v new file mode 100644 index 000000000..78da069c7 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/Debounce_B.v @@ -0,0 +1,59 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Debounce_B.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: Debounce_B +// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_B +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module Debounce_B + ( + CLK_IN, + reset, + enb, + In, + Out + ); + + + input CLK_IN; + input reset; + input enb; + input In; + output Out; + + + wire [7:0] Debouce_Count_out1; // uint8 + wire Count_Up_Down_out1; + + + // /Debouce_Count + assign Debouce_Count_out1 = 8'd20; + + + + // /Count_Up_Down + Count_Up_Down u_Count_Up_Down (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .u(In), + .count_debounce(Debouce_Count_out1), // uint8 + .y(Count_Up_Down_out1) + ); + + assign Out = Count_Up_Down_out1; + +endmodule // Debounce_B + diff --git a/library/controllerperipheralhdladi_pcore/Debounce_Index.v b/library/controllerperipheralhdladi_pcore/Debounce_Index.v new file mode 100644 index 000000000..d20c7eb83 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/Debounce_Index.v @@ -0,0 +1,59 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Debounce_Index.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: Debounce_Index +// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_Index +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module Debounce_Index + ( + CLK_IN, + reset, + enb, + In, + Out + ); + + + input CLK_IN; + input reset; + input enb; + input In; + output Out; + + + wire [7:0] Debouce_Count_out1; // uint8 + wire Count_Up_Down_out1; + + + // /Debouce_Count + assign Debouce_Count_out1 = 8'd20; + + + + // /Count_Up_Down + Count_Up_Down u_Count_Up_Down (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .u(In), + .count_debounce(Debouce_Count_out1), // uint8 + .y(Count_Up_Down_out1) + ); + + assign Out = Count_Up_Down_out1; + +endmodule // Debounce_Index + diff --git a/library/controllerperipheralhdladi_pcore/Detect_Change_To_One.v b/library/controllerperipheralhdladi_pcore/Detect_Change_To_One.v new file mode 100644 index 000000000..e83a819e1 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/Detect_Change_To_One.v @@ -0,0 +1,69 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Detect_Change_To_One.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: Detect_Change_To_One +// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Detect Change To One +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module Detect_Change_To_One + ( + CLK_IN, + reset, + enb, + In1, + Out1 + ); + + + input CLK_IN; + input reset; + input enb; + input In1; + output Out1; + + + reg Unit_Delay_out1; + wire Unit_Delay_out1_1; + wire In1_1; + + + // /Unit Delay + always @(posedge CLK_IN) + begin : Unit_Delay_process + if (reset == 1'b1) begin + Unit_Delay_out1 <= 1'b0; + end + else if (enb) begin + Unit_Delay_out1 <= In1; + end + end + + + + // /Logical Operator + assign Unit_Delay_out1_1 = ~ Unit_Delay_out1; + + + + // /Logical Operator1 + assign In1_1 = In1 & Unit_Delay_out1_1; + + + + assign Out1 = In1_1; + +endmodule // Detect_Change_To_One + diff --git a/library/controllerperipheralhdladi_pcore/Encoder_Peripheral_Hardware_Specification.v b/library/controllerperipheralhdladi_pcore/Encoder_Peripheral_Hardware_Specification.v new file mode 100644 index 000000000..1b884add1 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/Encoder_Peripheral_Hardware_Specification.v @@ -0,0 +1,136 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Encoder_Peripheral_Hardware_Specification.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: Encoder_Peripheral_Hardware_Specification +// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification +// Hierarchy Level: 1 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module Encoder_Peripheral_Hardware_Specification + ( + CLK_IN, + reset, + enb, + a, + b, + index, + valid, + count + ); + + + input CLK_IN; + input reset; + input enb; + input a; + input b; + input index; + output valid; + output [15:0] count; // uint16 + + + wire y; + wire Latch_Index_Pulse_out1; + wire Select_AB_Inputs_out1; + wire y_1; + wire y_2; + wire Select_AB_out1; + wire Select_AB_out2; + wire Detect_Change_To_One_out1; + wire signed [15:0] Counter_Max_out1; // int16 + wire signed [15:0] Update_Count_From_AB_out1; // int16 + wire [15:0] Data_Type_Conversion_out1; // uint16 + + + // /Debounce_Index + Debounce_Index u_Debounce_Index (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .In(index), + .Out(y) + ); + + // /Latch_Index_Pulse + Latch_Index_Pulse u_Latch_Index_Pulse (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .In1(y), + .Out1(Latch_Index_Pulse_out1) + ); + + assign valid = Latch_Index_Pulse_out1; + + // /Select_AB_Inputs + assign Select_AB_Inputs_out1 = 1'b0; + + + + // /Debounce_A + Debounce_A u_Debounce_A (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .In(a), + .Out(y_1) + ); + + // /Debounce_B + Debounce_B u_Debounce_B (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .In(b), + .Out(y_2) + ); + + // /Select AB + Select_AB u_Select_AB (.in_select(Select_AB_Inputs_out1), + .in1(y_1), + .in2(y_2), + .A(Select_AB_out1), + .B(Select_AB_out2) + ); + + // /Detect Change To One + Detect_Change_To_One u_Detect_Change_To_One (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .In1(y), + .Out1(Detect_Change_To_One_out1) + ); + + // /Counter_Max + assign Counter_Max_out1 = 16'sd4999; + + + + // /Update_Count_From_AB + Update_Count_From_AB u_Update_Count_From_AB (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .A(Select_AB_out1), + .B(Select_AB_out2), + .index(Detect_Change_To_One_out1), + .count_max(Counter_Max_out1), // int16 + .count(Update_Count_From_AB_out1) // int16 + ); + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = Update_Count_From_AB_out1; + + + + assign count = Data_Type_Conversion_out1; + +endmodule // Encoder_Peripheral_Hardware_Specification + diff --git a/library/controllerperipheralhdladi_pcore/Latch_Index_Pulse.v b/library/controllerperipheralhdladi_pcore/Latch_Index_Pulse.v new file mode 100644 index 000000000..657c5c122 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/Latch_Index_Pulse.v @@ -0,0 +1,70 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Latch_Index_Pulse.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: Latch_Index_Pulse +// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Latch_Index_Pulse +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module Latch_Index_Pulse + ( + CLK_IN, + reset, + enb, + In1, + Out1 + ); + + + input CLK_IN; + input reset; + input enb; + input In1; + output Out1; + + + wire Constant1_out1; + wire Switch_out1; + reg Delay_out1; + + + // /Constant1 + assign Constant1_out1 = 1'b1; + + + + // /Delay + always @(posedge CLK_IN) + begin : Delay_process + if (reset == 1'b1) begin + Delay_out1 <= 1'b0; + end + else if (enb) begin + Delay_out1 <= Switch_out1; + end + end + + + + // /Switch + assign Switch_out1 = (Delay_out1 == 1'b0 ? In1 : + Constant1_out1); + + + + assign Out1 = Switch_out1; + +endmodule // Latch_Index_Pulse + diff --git a/library/controllerperipheralhdladi_pcore/PWM.v b/library/controllerperipheralhdladi_pcore/PWM.v new file mode 100644 index 000000000..3f21ca232 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/PWM.v @@ -0,0 +1,163 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\PWM.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: PWM +// Source Path: controllerPeripheralHdlAdi/PWM +// Hierarchy Level: 1 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module PWM + ( + CLK_IN, + reset, + enb, + c_0, + c_1, + c_2, + pwm_0, + pwm_1, + pwm_2 + ); + + + input CLK_IN; + input reset; + input enb; + input [15:0] c_0; // uint16 + input [15:0] c_1; // uint16 + input [15:0] c_2; // uint16 + output pwm_0; // boolean + output pwm_1; // boolean + output pwm_2; // boolean + + + wire [15:0] Timer_Period_Clock_Cycles_out1; // uint16 + wire [15:0] Chart_out1; // uint16 + wire [15:0] c [0:2]; // uint16 [3] + wire [15:0] Add_out1 [0:2]; // uint16 [3] + wire [15:0] Add_out1_0; // uint16 + wire Relational_Operator_relop1; + wire [15:0] Add_out1_1; // uint16 + wire Relational_Operator_relop2; + wire [15:0] Add_out1_2; // uint16 + wire Relational_Operator_relop3; + wire [0:2] Relational_Operator_out1; // boolean [3] + wire Relational_Operator_out1_0; + wire [0:2] Compare_To_Zero_out1; // boolean [3] + wire Compare_To_Zero_out1_0; + wire Relational_Operator_out1_0_1; + wire Relational_Operator_out1_1; + wire Compare_To_Zero_out1_1; + wire Relational_Operator_out1_1_1; + wire Relational_Operator_out1_2; + wire Compare_To_Zero_out1_2; + wire Relational_Operator_out1_2_1; + + + // /Timer Period Clock Cycles + assign Timer_Period_Clock_Cycles_out1 = 16'd1000; + + + + // /Chart + Chart u_Chart (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .CounterMax(Timer_Period_Clock_Cycles_out1), // uint16 + .count(Chart_out1) // uint16 + ); + + assign c[0] = c_0; + assign c[1] = c_1; + assign c[2] = c_2; + + // /Add + assign Add_out1[0] = Timer_Period_Clock_Cycles_out1 - c[0]; + assign Add_out1[1] = Timer_Period_Clock_Cycles_out1 - c[1]; + assign Add_out1[2] = Timer_Period_Clock_Cycles_out1 - c[2]; + + + + assign Add_out1_0 = Add_out1[0]; + + assign Relational_Operator_relop1 = (Chart_out1 >= Add_out1_0 ? 1'b1 : + 1'b0); + + + + assign Add_out1_1 = Add_out1[1]; + + assign Relational_Operator_relop2 = (Chart_out1 >= Add_out1_1 ? 1'b1 : + 1'b0); + + + + assign Add_out1_2 = Add_out1[2]; + + // /Relational Operator + assign Relational_Operator_relop3 = (Chart_out1 >= Add_out1_2 ? 1'b1 : + 1'b0); + + + + assign Relational_Operator_out1[0] = Relational_Operator_relop1; + assign Relational_Operator_out1[1] = Relational_Operator_relop2; + assign Relational_Operator_out1[2] = Relational_Operator_relop3; + + + + assign Relational_Operator_out1_0 = Relational_Operator_out1[0]; + + // /Compare To Zero + assign Compare_To_Zero_out1[0] = (c[0] != 16'b0000000000000000 ? 1'b1 : + 1'b0); + assign Compare_To_Zero_out1[1] = (c[1] != 16'b0000000000000000 ? 1'b1 : + 1'b0); + assign Compare_To_Zero_out1[2] = (c[2] != 16'b0000000000000000 ? 1'b1 : + 1'b0); + + + + assign Compare_To_Zero_out1_0 = Compare_To_Zero_out1[0]; + + assign Relational_Operator_out1_0_1 = Relational_Operator_out1_0 & Compare_To_Zero_out1_0; + + + + assign pwm_0 = Relational_Operator_out1_0_1; + + assign Relational_Operator_out1_1 = Relational_Operator_out1[1]; + + assign Compare_To_Zero_out1_1 = Compare_To_Zero_out1[1]; + + assign Relational_Operator_out1_1_1 = Relational_Operator_out1_1 & Compare_To_Zero_out1_1; + + + + assign pwm_1 = Relational_Operator_out1_1_1; + + assign Relational_Operator_out1_2 = Relational_Operator_out1[2]; + + assign Compare_To_Zero_out1_2 = Compare_To_Zero_out1[2]; + + // /Logical Operator + assign Relational_Operator_out1_2_1 = Relational_Operator_out1_2 & Compare_To_Zero_out1_2; + + + + assign pwm_2 = Relational_Operator_out1_2_1; + +endmodule // PWM + diff --git a/library/controllerperipheralhdladi_pcore/Select_AB.v b/library/controllerperipheralhdladi_pcore/Select_AB.v new file mode 100644 index 000000000..3d6f9f890 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/Select_AB.v @@ -0,0 +1,59 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Select_AB.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: Select_AB +// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Select AB +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module Select_AB + ( + in_select, + in1, + in2, + A, + B + ); + + + input in_select; + input in1; + input in2; + output A; + output B; + + + wire Switch_out1; + wire Switch1_out1; + + + // /Switch + assign Switch_out1 = (in_select == 1'b0 ? in2 : + in1); + + + + assign A = Switch_out1; + + // /Switch1 + assign Switch1_out1 = (in_select == 1'b0 ? in1 : + in2); + + + + assign B = Switch1_out1; + +endmodule // Select_AB + diff --git a/library/controllerperipheralhdladi_pcore/Update_Count_From_AB.v b/library/controllerperipheralhdladi_pcore/Update_Count_From_AB.v new file mode 100644 index 000000000..bf343ed0b --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/Update_Count_From_AB.v @@ -0,0 +1,270 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Update_Count_From_AB.v +// Created: 2014-08-28 10:13:58 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: Update_Count_From_AB +// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module Update_Count_From_AB + ( + CLK_IN, + reset, + enb, + A, + B, + index, + count_max, + count + ); + + + input CLK_IN; + input reset; + input enb; + input A; + input B; + input index; + input signed [15:0] count_max; // int16 + output signed [15:0] count; // int16 + + parameter IN_NO_ACTIVE_CHILD = 0, IN_A0_B0 = 1, IN_A0_B1 = 2, IN_A1_B0 = 3, IN_A1_B1 = 4; + parameter IN_INDEX = 0, IN_INIT = 1; + + reg [1:0] is_libEncoderPeripheralHdl_c7_Update_Count_From_AB; // uint8 + reg [2:0] is_INDEX; // uint8 + reg signed [15:0] count_reg; // int16 + reg [1:0] is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next; // enumerated type (2 enums) + reg [2:0] is_INDEX_next; // enumerated type (5 enums) + reg signed [15:0] count_reg_next; // int16 + + + always @(posedge CLK_IN) + begin : libEncoderPeripheralHdl_c7_Update_Count_From_AB_process + if (reset == 1'b1) begin + is_INDEX <= IN_NO_ACTIVE_CHILD; + count_reg <= 16'sd0; + //Entry: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB + //Entry Internal: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB + //Transition: ':30' + is_libEncoderPeripheralHdl_c7_Update_Count_From_AB <= IN_INIT; + end + else if (enb) begin + is_libEncoderPeripheralHdl_c7_Update_Count_From_AB <= is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next; + is_INDEX <= is_INDEX_next; + count_reg <= count_reg_next; + end + end + + always @(is_libEncoderPeripheralHdl_c7_Update_Count_From_AB, is_INDEX, A, B, index, + count_max, count_reg) begin + count_reg_next = count_reg; + is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next = is_libEncoderPeripheralHdl_c7_Update_Count_From_AB; + is_INDEX_next = is_INDEX; + //Gateway: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB + //During: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB + + case ( is_libEncoderPeripheralHdl_c7_Update_Count_From_AB) + IN_INDEX : + begin + //During 'INDEX': ':29' + if (index == 1'b1) begin + //Transition: ':34' + //Transition: ':35' + count_reg_next = 16'sd0; + //Transition: ':37' + //Exit Internal 'INDEX': ':29' + is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next = IN_INDEX; + is_INDEX_next = IN_A0_B0; + end + else begin + + case ( is_INDEX) + IN_A0_B0 : + begin + //During 'A0_B0': ':1' + if (A && ( ~ B)) begin + //Transition: ':14' + //Graphical Function 'incrementCount': ':42' + //Transition: ':44' + count_reg_next = count_reg + 1; + if ((count_reg + 16'sd1) > count_max) begin + //Transition: ':46' + //Transition: ':48' + count_reg_next = 16'sd0; + //Transition: ':51' + end + else begin + //Transition: ':50' + end + //Transition: ':13' + is_INDEX_next = IN_A1_B0; + end + else if (( ~ A) && B) begin + //Transition: ':8' + //Graphical Function 'decrementCount': ':55' + //Transition: ':60' + count_reg_next = count_reg - 1; + if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin + //Transition: ':61' + //Transition: ':63' + count_reg_next = count_max; + //Transition: ':64' + end + else begin + //Transition: ':62' + end + is_INDEX_next = IN_A0_B1; + end + end + IN_A0_B1 : + begin + //During 'A0_B1': ':5' + if (A && B) begin + //Transition: ':10' + //Graphical Function 'decrementCount': ':55' + //Transition: ':60' + count_reg_next = count_reg - 1; + if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin + //Transition: ':61' + //Transition: ':63' + count_reg_next = count_max; + //Transition: ':64' + end + else begin + //Transition: ':62' + end + is_INDEX_next = IN_A1_B1; + end + else begin + //Transition: ':16' + if (( ~ A) && ( ~ B)) begin + //Transition: ':17' + //Graphical Function 'incrementCount': ':42' + //Transition: ':44' + count_reg_next = count_reg + 1; + if ((count_reg + 16'sd1) > count_max) begin + //Transition: ':46' + //Transition: ':48' + count_reg_next = 16'sd0; + //Transition: ':51' + end + else begin + //Transition: ':50' + end + is_INDEX_next = IN_A0_B0; + end + end + end + IN_A1_B0 : + begin + //During 'A1_B0': ':2' + if (( ~ A) && ( ~ B)) begin + //Transition: ':7' + //Graphical Function 'decrementCount': ':55' + //Transition: ':60' + count_reg_next = count_reg - 1; + if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin + //Transition: ':61' + //Transition: ':63' + count_reg_next = count_max; + //Transition: ':64' + end + else begin + //Transition: ':62' + end + is_INDEX_next = IN_A0_B0; + end + else begin + //Transition: ':24' + if (A && B) begin + //Transition: ':25' + //Graphical Function 'incrementCount': ':42' + //Transition: ':44' + count_reg_next = count_reg + 1; + if ((count_reg + 16'sd1) > count_max) begin + //Transition: ':46' + //Transition: ':48' + count_reg_next = 16'sd0; + //Transition: ':51' + end + else begin + //Transition: ':50' + end + is_INDEX_next = IN_A1_B1; + end + end + end + default : + begin + //During 'A1_B1': ':4' + if (( ~ A) && B) begin + //Transition: ':19' + //Graphical Function 'incrementCount': ':42' + //Transition: ':44' + count_reg_next = count_reg + 1; + if ((count_reg + 16'sd1) > count_max) begin + //Transition: ':46' + //Transition: ':48' + count_reg_next = 16'sd0; + //Transition: ':51' + end + else begin + //Transition: ':50' + end + //Transition: ':21' + is_INDEX_next = IN_A0_B1; + end + else if (A && ( ~ B)) begin + //Transition: ':22' + //Graphical Function 'decrementCount': ':55' + //Transition: ':60' + count_reg_next = count_reg - 1; + if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin + //Transition: ':61' + //Transition: ':63' + count_reg_next = count_max; + //Transition: ':64' + end + else begin + //Transition: ':62' + end + is_INDEX_next = IN_A1_B0; + end + end + endcase + + end + end + default : + begin + //During 'INIT': ':68' + //Transition: ':70' + //Transition: ':35' + count_reg_next = 16'sd0; + //Transition: ':37' + is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next = IN_INDEX; + is_INDEX_next = IN_A0_B0; + end + endcase + + end + + assign count = count_reg_next; + + + +endmodule // Update_Count_From_AB + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_ADC_Peripheral_To_Phase_Current.v b/library/controllerperipheralhdladi_pcore/controllerHdl_ADC_Peripheral_To_Phase_Current.v new file mode 100644 index 000000000..bc540e600 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_ADC_Peripheral_To_Phase_Current.v @@ -0,0 +1,87 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_ADC_Peripheral_To_Phase_Current.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_ADC_Peripheral_To_Phase_Current +// Source Path: controllerHdl/ADC_Peripheral_To_Phase_Current +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_ADC_Peripheral_To_Phase_Current + ( + adc_0, + adc_1, + phase_currents_0, + phase_currents_1 + ); + + + input signed [17:0] adc_0; // sfix18_En17 + input signed [17:0] adc_1; // sfix18_En17 + output signed [17:0] phase_currents_0; // sfix18_En15 + output signed [17:0] phase_currents_1; // sfix18_En15 + + + wire signed [17:0] adc [0:1]; // sfix18_En17 [2] + wire signed [17:0] ADC_Zero_Offset_out1; // sfix18_En16 + wire signed [19:0] Add_v; // sfix20_En17 + wire signed [19:0] Add_sub_cast; // sfix20_En17 + wire signed [19:0] Add_sub_cast_1; // sfix20_En17 + wire signed [19:0] Add_out1 [0:1]; // sfix20_En17 [2] + wire signed [17:0] ADC_Amps_Per_Driver_Unit_out1; // sfix18_En15 + wire signed [37:0] Product_mul_temp; // sfix38_En32 + wire signed [37:0] Product_mul_temp_1; // sfix38_En32 + wire signed [17:0] phase_currents [0:1]; // sfix18_En15 [2] + + + assign adc[0] = adc_0; + assign adc[1] = adc_1; + + // /ADC_Zero_Offset + assign ADC_Zero_Offset_out1 = 18'sb000000000000000000; + + + + // /Add + assign Add_v = {ADC_Zero_Offset_out1[17], {ADC_Zero_Offset_out1, 1'b0}}; + assign Add_sub_cast = adc[0]; + assign Add_out1[0] = Add_sub_cast - Add_v; + assign Add_sub_cast_1 = adc[1]; + assign Add_out1[1] = Add_sub_cast_1 - Add_v; + + + + // /ADC_Amps_Per_Driver_Unit + assign ADC_Amps_Per_Driver_Unit_out1 = 18'sb010100000000000000; + + + + // /Product + assign Product_mul_temp = Add_out1[0] * ADC_Amps_Per_Driver_Unit_out1; + assign phase_currents[0] = ((Product_mul_temp[37] == 1'b0) && (Product_mul_temp[36:34] != 3'b000) ? 18'sb011111111111111111 : + ((Product_mul_temp[37] == 1'b1) && (Product_mul_temp[36:34] != 3'b111) ? 18'sb100000000000000000 : + $signed(Product_mul_temp[34:17]))); + assign Product_mul_temp_1 = Add_out1[1] * ADC_Amps_Per_Driver_Unit_out1; + assign phase_currents[1] = ((Product_mul_temp_1[37] == 1'b0) && (Product_mul_temp_1[36:34] != 3'b000) ? 18'sb011111111111111111 : + ((Product_mul_temp_1[37] == 1'b1) && (Product_mul_temp_1[36:34] != 3'b111) ? 18'sb100000000000000000 : + $signed(Product_mul_temp_1[34:17]))); + + + + assign phase_currents_0 = phase_currents[0]; + + assign phase_currents_1 = phase_currents[1]; + +endmodule // controllerHdl_ADC_Peripheral_To_Phase_Current + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Calculate_Rotor_Velocity.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Calculate_Rotor_Velocity.v new file mode 100644 index 000000000..14152a80b --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Calculate_Rotor_Velocity.v @@ -0,0 +1,189 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Calculate_Rotor_Velocity.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Calculate_Rotor_Velocity +// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Calculate_Rotor_Velocity +// Hierarchy Level: 3 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Calculate_Rotor_Velocity + ( + CLK_IN, + reset, + enb_1_2000_0, + valid, + position, + rotor_velocity + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input valid; + input signed [17:0] position; // sfix18_En14 + output signed [17:0] rotor_velocity; // sfix18_En8 + + + wire Constant_out1; + reg Delay3_out1; + reg [0:1] Delay2_reg; // ufix1 [2] + wire [0:1] Delay2_reg_next; // ufix1 [2] + wire Delay2_out1; + wire Detect_Rise_relop1; + wire Detect_Rise_out1; + wire Delay2_out1_1; + wire update_velocity; + reg signed [17:0] Delay1_out1; // sfix18_En14 + wire signed [18:0] Add_sub_cast; // sfix19_En14 + wire signed [18:0] Add_sub_cast_1; // sfix19_En14 + wire signed [18:0] Add_out1; // sfix19_En14 + wire signed [17:0] position_delta; // sfix18_En15 + wire [17:0] time_delta_1; // ufix18_En3 + wire signed [18:0] Product_cast; // sfix19_En3 + wire signed [36:0] Product_mul_temp; // sfix37_En18 + wire signed [35:0] velocity; // sfix36_En18 + wire signed [35:0] Switch_out1; // sfix36_En18 + reg signed [35:0] Delay_out1; // sfix36_En18 + wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En8 + + // First two velocity calculations are not valid + // + // If detect positive rise in valid, this is a bad sample + // since encoder index just reset. In this case hold the last value + // + // Calculate Velocity + + + // /Constant + assign Constant_out1 = 1'b1; + + + + // /Delay3 + always @(posedge CLK_IN) + begin : Delay3_process + if (reset == 1'b1) begin + Delay3_out1 <= 1'b0; + end + else if (enb_1_2000_0) begin + Delay3_out1 <= valid; + end + end + + + + // /Delay2 + always @(posedge CLK_IN) + begin : Delay2_process + if (reset == 1'b1) begin + Delay2_reg[0] <= 1'b0; + Delay2_reg[1] <= 1'b0; + end + else if (enb_1_2000_0) begin + Delay2_reg[0] <= Delay2_reg_next[0]; + Delay2_reg[1] <= Delay2_reg_next[1]; + end + end + + assign Delay2_out1 = Delay2_reg[1]; + assign Delay2_reg_next[0] = Constant_out1; + assign Delay2_reg_next[1] = Delay2_reg[0]; + + + + // /Detect_Rise + assign Detect_Rise_relop1 = (valid > Delay3_out1 ? 1'b1 : + 1'b0); + + + + // /No_Rise_Detected + assign Detect_Rise_out1 = ~ Detect_Rise_relop1; + + + + // /Logical Operator + assign Delay2_out1_1 = Delay2_out1 & Detect_Rise_out1; + + + + assign update_velocity = Delay2_out1_1; + + // /Delay1 + always @(posedge CLK_IN) + begin : Delay1_process + if (reset == 1'b1) begin + Delay1_out1 <= 18'sb000000000000000000; + end + else if (enb_1_2000_0) begin + Delay1_out1 <= position; + end + end + + + + // /Add + assign Add_sub_cast = position; + assign Add_sub_cast_1 = Delay1_out1; + assign Add_out1 = Add_sub_cast - Add_sub_cast_1; + + + + // /Wrap_NegPi_To_Pi + controllerHdl_Wrap_NegPi_To_Pi u_Wrap_NegPi_To_Pi (.position(Add_out1), // sfix19_En14 + .wrap(position_delta) // sfix18_En15 + ); + + // /Time_Delta + assign time_delta_1 = 18'b110000110101000000; + + + + // /Product + assign Product_cast = time_delta_1; + assign Product_mul_temp = position_delta * Product_cast; + assign velocity = Product_mul_temp[35:0]; + + + + // /Delay + always @(posedge CLK_IN) + begin : Delay_process + if (reset == 1'b1) begin + Delay_out1 <= 36'sh000000000; + end + else if (enb_1_2000_0) begin + Delay_out1 <= Switch_out1; + end + end + + + + // /Switch + assign Switch_out1 = (update_velocity == 1'b0 ? Delay_out1 : + velocity); + + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = Switch_out1[27:10]; + + + + assign rotor_velocity = Data_Type_Conversion_out1; + +endmodule // controllerHdl_Calculate_Rotor_Velocity + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Complex_Multiply.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Complex_Multiply.v new file mode 100644 index 000000000..dbc93c5bc --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Complex_Multiply.v @@ -0,0 +1,87 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Complex_Multiply.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Complex_Multiply +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Complex_Multiply +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Complex_Multiply + ( + In1_re, + In1_im, + In2_re, + In2_im, + Re, + Im + ); + + + input signed [17:0] In1_re; // sfix18_En16 + input signed [17:0] In1_im; // sfix18_En16 + input signed [17:0] In2_re; // sfix18_En16 + input signed [17:0] In2_im; // sfix18_En16 + output signed [35:0] Re; // sfix36_En32 + output signed [35:0] Im; // sfix36_En32 + + + wire signed [35:0] Product_out1; // sfix36_En32 + wire signed [35:0] Product1_out1; // sfix36_En32 + wire signed [35:0] Add1_out1; // sfix36_En32 + wire signed [35:0] Product2_out1; // sfix36_En32 + wire signed [35:0] Product3_out1; // sfix36_En32 + wire signed [35:0] Add2_out1; // sfix36_En32 + + + // /Product + // + // /Complex to Real-Imag1 + // + // /Complex to Real-Imag2 + assign Product_out1 = In1_re * In2_re; + + + + // /Product1 + assign Product1_out1 = In1_im * In2_im; + + + + // /Add1 + assign Add1_out1 = Product_out1 - Product1_out1; + + + + assign Re = Add1_out1; + + // /Product2 + assign Product2_out1 = In1_re * In2_im; + + + + // /Product3 + assign Product3_out1 = In1_im * In2_re; + + + + // /Add2 + assign Add2_out1 = Product2_out1 + Product3_out1; + + + + assign Im = Add2_out1; + +endmodule // controllerHdl_Complex_Multiply + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type.v new file mode 100644 index 000000000..ca67baecf --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Convert_Data_Type.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Convert_Data_Type +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Frequency_To_Volts/Convert_Data_Type +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Convert_Data_Type + ( + In1, + Out1 + ); + + + input signed [31:0] In1; // sfix32_En21 + output signed [17:0] Out1; // sfix18_En7 + + + wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En7 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = In1[31:14]; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // controllerHdl_Convert_Data_Type + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type1.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type1.v new file mode 100644 index 000000000..fafbf5608 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type1.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Convert_Data_Type1.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Convert_Data_Type1 +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Park_Transform/Convert_Data_Type1 +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Convert_Data_Type1 + ( + In1, + Out1 + ); + + + input signed [35:0] In1; // sfix36_En28 + output signed [17:0] Out1; // sfix18_En10 + + + wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En10 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = In1[35:18]; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // controllerHdl_Convert_Data_Type1 + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type_block.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type_block.v new file mode 100644 index 000000000..6d82659b5 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type_block.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Convert_Data_Type_block.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Convert_Data_Type_block +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_To_Electical_Velocity/Convert_Data_Type +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Convert_Data_Type_block + ( + In1, + Out1 + ); + + + input signed [31:0] In1; // sfix32_En22 + output signed [17:0] Out1; // sfix18_En8 + + + wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En8 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = In1[31:14]; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // controllerHdl_Convert_Data_Type_block + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type_block1.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type_block1.v new file mode 100644 index 000000000..e9cc100c6 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type_block1.v @@ -0,0 +1,38 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Convert_Data_Type_block1.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Convert_Data_Type_block1 +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Convert_Data_Type +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Convert_Data_Type_block1 + ( + In1, + Out1 + ); + + + input signed [17:0] In1; // sfix18_En14 + output signed [17:0] Out1; // sfix18_En14 + + + + + // /Data Type Conversion + assign Out1 = In1; + +endmodule // controllerHdl_Convert_Data_Type_block1 + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type_block2.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type_block2.v new file mode 100644 index 000000000..fd134415a --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type_block2.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Convert_Data_Type_block2.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Convert_Data_Type_block2 +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Park_Transform/Convert_Data_Type +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Convert_Data_Type_block2 + ( + In1, + Out1 + ); + + + input signed [35:0] In1; // sfix36_En28 + output signed [17:0] Out1; // sfix18_En10 + + + wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En10 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = In1[35:18]; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // controllerHdl_Convert_Data_Type_block2 + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Detect_Change.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Detect_Change.v new file mode 100644 index 000000000..c6402bf5a --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Detect_Change.v @@ -0,0 +1,74 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Detect_Change.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Detect_Change +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity/Set_Acceleration/Detect_Change +// Hierarchy Level: 7 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Detect_Change + ( + CLK_IN, + reset, + enb_1_2000_0, + x, + y + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input signed [17:0] x; // sfix18_En8 + output y; + + + reg signed [17:0] Delay_out1; // sfix18_En8 + wire signed [18:0] Add_sub_cast; // sfix19_En8 + wire signed [18:0] Add_sub_cast_1; // sfix19_En8 + wire signed [18:0] Add_out1; // sfix19_En8 + wire Compare_To_Zero2_out1; + + + // /Delay + always @(posedge CLK_IN) + begin : Delay_process + if (reset == 1'b1) begin + Delay_out1 <= 18'sb000000000000000000; + end + else if (enb_1_2000_0) begin + Delay_out1 <= x; + end + end + + + + // /Add + assign Add_sub_cast = x; + assign Add_sub_cast_1 = Delay_out1; + assign Add_out1 = Add_sub_cast - Add_sub_cast_1; + + + + // /Compare To Zero2 + assign Compare_To_Zero2_out1 = (Add_out1 != 19'sb0000000000000000000 ? 1'b1 : + 1'b0); + + + + assign y = Compare_To_Zero2_out1; + +endmodule // controllerHdl_Detect_Change + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Double_Range.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Double_Range.v new file mode 100644 index 000000000..15f24a457 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Double_Range.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Double_Range.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Double_Range +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Frequency_To_Volts/Double_Range +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Double_Range + ( + In1, + Out1 + ); + + + input signed [31:0] In1; // sfix32_En22 + output signed [31:0] Out1; // sfix32_En21 + + + wire signed [31:0] Data_Type_Conversion_out1; // sfix32_En21 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = {In1[31], In1[31:1]}; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // controllerHdl_Double_Range + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Electrical_Velocity_To_Position.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Electrical_Velocity_To_Position.v new file mode 100644 index 000000000..e4e538423 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Electrical_Velocity_To_Position.v @@ -0,0 +1,87 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Electrical_Velocity_To_Position.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Electrical_Velocity_To_Position +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Electrical_Velocity_To_Position +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Electrical_Velocity_To_Position + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + EV, + EP + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [17:0] EV; // sfix18_En6 + output signed [17:0] EP; // sfix18_En14 + + + wire signed [35:0] Gain_out1; // sfix36_En37 + wire signed [31:0] Data_Type_Conversion2_out1; // sfix32_En27 + wire signed [31:0] Reset_Delay_out1; // sfix32_En27 + wire signed [31:0] Add3_out1; // sfix32_En27 + wire signed [31:0] Wrap_2pi_Once_out1; // sfix32_En27 + wire signed [17:0] Data_Type_Conversion1_out1; // sfix18_En14 + + // Electrical Velocity To Position + + + // /Gain + assign Gain_out1 = 85899 * EV; + + + + // /Data Type Conversion2 + assign Data_Type_Conversion2_out1 = {{6{Gain_out1[35]}}, Gain_out1[35:10]}; + + + + // /Add3 + assign Add3_out1 = Data_Type_Conversion2_out1 + Reset_Delay_out1; + + + + // /Wrap_2pi_Once + controllerHdl_Wrap_2pi_Once u_Wrap_2pi_Once (.x(Add3_out1), // sfix32_En27 + .wrap(Wrap_2pi_Once_out1) // sfix32_En27 + ); + + // /Reset_Delay + controllerHdl_Reset_Delay u_Reset_Delay (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(Reset_1), + .In(Wrap_2pi_Once_out1), // sfix32_En27 + .Out(Reset_Delay_out1) // sfix32_En27 + ); + + // /Data Type Conversion1 + assign Data_Type_Conversion1_out1 = Reset_Delay_out1[30:13]; + + + + assign EP = Data_Type_Conversion1_out1; + +endmodule // controllerHdl_Electrical_Velocity_To_Position + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Encoder_To_Position_And_Velocity.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Encoder_To_Position_And_Velocity.v new file mode 100644 index 000000000..e29d995c7 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Encoder_To_Position_And_Velocity.v @@ -0,0 +1,79 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Encoder_To_Position_And_Velocity.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Encoder_To_Position_And_Velocity +// Source Path: controllerHdl/Encoder_To_Position_And_Velocity +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Encoder_To_Position_And_Velocity + ( + CLK_IN, + reset, + enb_1_2000_0, + encoder_valid, + encoder_counter, + param_zero_offset, + position_valid, + rotor_position, + electrical_position, + rotor_velocity + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input encoder_valid; + input [15:0] encoder_counter; // uint16 + input signed [17:0] param_zero_offset; // sfix18_En14 + output position_valid; + output signed [17:0] rotor_position; // sfix18_En14 + output signed [17:0] electrical_position; // sfix18_En14 + output signed [17:0] rotor_velocity; // sfix18_En8 + + + wire signed [17:0] Rotor_To_Electrical_Position_out1; // sfix18_En14 + wire signed [17:0] Calculate_Rotor_Velocity_out1; // sfix18_En8 + + + assign position_valid = encoder_valid; + + // /Encoder_To_Rotor_Position + controllerHdl_Encoder_To_Rotor_Position u_Encoder_To_Rotor_Position (.counter(encoder_counter), // uint16 + .param_zero_offset(param_zero_offset), // sfix18_En14 + .position(rotor_position) // sfix18_En14 + ); + + // /Rotor_To_Electrical_Position + controllerHdl_Rotor_To_Electrical_Position u_Rotor_To_Electrical_Position (.R(rotor_position), // sfix18_En14 + .E(Rotor_To_Electrical_Position_out1) // sfix18_En14 + ); + + assign electrical_position = Rotor_To_Electrical_Position_out1; + + // /Calculate_Rotor_Velocity + controllerHdl_Calculate_Rotor_Velocity u_Calculate_Rotor_Velocity (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .valid(encoder_valid), + .position(rotor_position), // sfix18_En14 + .rotor_velocity(Calculate_Rotor_Velocity_out1) // sfix18_En8 + ); + + assign rotor_velocity = Calculate_Rotor_Velocity_out1; + +endmodule // controllerHdl_Encoder_To_Position_And_Velocity + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Encoder_To_Rotor_Position.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Encoder_To_Rotor_Position.v new file mode 100644 index 000000000..dffade101 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Encoder_To_Rotor_Position.v @@ -0,0 +1,67 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Encoder_To_Rotor_Position.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Encoder_To_Rotor_Position +// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Encoder_To_Rotor_Position +// Hierarchy Level: 3 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Encoder_To_Rotor_Position + ( + counter, + param_zero_offset, + position + ); + + + input [15:0] counter; // uint16 + input signed [17:0] param_zero_offset; // sfix18_En14 + output signed [17:0] position; // sfix18_En14 + + + wire [31:0] radians_per_counts_mul_temp; // ufix32_En25 + wire signed [17:0] encoder_angle; // sfix18_En14 + wire signed [18:0] Add_sub_cast; // sfix19_En14 + wire signed [18:0] Add_sub_cast_1; // sfix19_En14 + wire signed [18:0] Add_out1; // sfix19_En14 + wire signed [17:0] rotor_position; // sfix18_En14 + + // Encoder to Rotor Position + // + // The encoder counts increase with positive rotation of the rotor. + + + // /radians_per_counts + assign radians_per_counts_mul_temp = 42166 * counter; + assign encoder_angle = $signed(radians_per_counts_mul_temp[28:11]); + + + + // /Add + assign Add_sub_cast = encoder_angle; + assign Add_sub_cast_1 = param_zero_offset; + assign Add_out1 = Add_sub_cast - Add_sub_cast_1; + + + + // /Wrap_2pi + controllerHdl_Wrap_2pi u_Wrap_2pi (.x(Add_out1), // sfix19_En14 + .wrap(rotor_position) // sfix18_En14 + ); + + assign position = rotor_position; + +endmodule // controllerHdl_Encoder_To_Rotor_Position + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Field_Oriented_Control.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Field_Oriented_Control.v new file mode 100644 index 000000000..232954653 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Field_Oriented_Control.v @@ -0,0 +1,189 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Field_Oriented_Control.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Field_Oriented_Control +// Source Path: controllerHdl/Field_Oriented_Control +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Field_Oriented_Control + ( + CLK_IN, + reset, + enb_1_2000_0, + controller_mode, + command, + electrical_postion, + rotor_velocity, + phase_currents_0, + phase_currents_1, + param_velocity_p_gain, + param_velocity_i_gain, + param_current_p_gain, + param_current_i_gain, + param_open_loop_bias, + param_open_loop_scalar, + phase_voltages_0, + phase_voltages_1, + phase_voltages_2, + dq_current_0, + dq_current_1, + electrical_position_ol + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input [1:0] controller_mode; // ufix2 + input signed [17:0] command; // sfix18_En8 + input signed [17:0] electrical_postion; // sfix18_En14 + input signed [17:0] rotor_velocity; // sfix18_En8 + input signed [17:0] phase_currents_0; // sfix18_En15 + input signed [17:0] phase_currents_1; // sfix18_En15 + input signed [17:0] param_velocity_p_gain; // sfix18_En16 + input signed [17:0] param_velocity_i_gain; // sfix18_En15 + input signed [17:0] param_current_p_gain; // sfix18_En10 + input signed [17:0] param_current_i_gain; // sfix18_En2 + input signed [17:0] param_open_loop_bias; // sfix18_En14 + input signed [17:0] param_open_loop_scalar; // sfix18_En16 + output signed [19:0] phase_voltages_0; // sfix20_En12 + output signed [19:0] phase_voltages_1; // sfix20_En12 + output signed [19:0] phase_voltages_2; // sfix20_En12 + output signed [17:0] dq_current_0; // sfix18_En15 + output signed [17:0] dq_current_1; // sfix18_En15 + output signed [17:0] electrical_position_ol; // sfix18_En14 + + + wire MATLAB_Function_out2; + wire signed [19:0] Velocity_Control_out1_0; // sfix20_En12 + wire signed [19:0] Velocity_Control_out1_1; // sfix20_En12 + wire signed [19:0] Velocity_Control_out1_2; // sfix20_En12 + wire signed [17:0] Velocity_Control_out2_0; // sfix18_En15 + wire signed [17:0] Velocity_Control_out2_1; // sfix18_En15 + wire [1:0] MATLAB_Function_out1; // ufix2 + wire signed [17:0] Open_Loop_Control_out1_0; // sfix18_En13 + wire signed [17:0] Open_Loop_Control_out1_1; // sfix18_En13 + wire signed [17:0] Open_Loop_Control_out1_2; // sfix18_En13 + wire signed [17:0] Open_Loop_Control_out2; // sfix18_En14 + wire signed [17:0] Open_Loop_Control_out1 [0:2]; // sfix18_En13 [3] + wire signed [19:0] Open_Loop_Control_out1_dtc [0:2]; // sfix20_En12 [3] + wire signed [19:0] Velocity_Control_out1 [0:2]; // sfix20_En12 [3] + wire signed [19:0] StandBy_out1_0; // sfix20_En12 + wire signed [19:0] StandBy_out1_1; // sfix20_En12 + wire signed [19:0] StandBy_out1_2; // sfix20_En12 + wire signed [19:0] StandBy_out1 [0:2]; // sfix20_En12 [3] + wire signed [19:0] Multiport_Switch_out1 [0:2]; // sfix20_En12 [3] + + // Field Oriented Control + + + // /MATLAB Function + controllerHdl_MATLAB_Function_block2 u_MATLAB_Function (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .cMode(controller_mode), // ufix2 + .index(MATLAB_Function_out1), // ufix2 + .reset_1(MATLAB_Function_out2) + ); + + // /Open_Loop_Control + controllerHdl_Open_Loop_Control u_Open_Loop_Control (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .reset_1(MATLAB_Function_out2), + .command_value(command), // sfix18_En8 + .param_open_loop_bias(param_open_loop_bias), // sfix18_En14 + .param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16 + .phase_voltages_0(Open_Loop_Control_out1_0), // sfix18_En13 + .phase_voltages_1(Open_Loop_Control_out1_1), // sfix18_En13 + .phase_voltages_2(Open_Loop_Control_out1_2), // sfix18_En13 + .electrical_position(Open_Loop_Control_out2) // sfix18_En14 + ); + + assign Open_Loop_Control_out1[0] = Open_Loop_Control_out1_0; + assign Open_Loop_Control_out1[1] = Open_Loop_Control_out1_1; + assign Open_Loop_Control_out1[2] = Open_Loop_Control_out1_2; + + assign Open_Loop_Control_out1_dtc[0] = {{3{Open_Loop_Control_out1[0][17]}}, Open_Loop_Control_out1[0][17:1]}; + assign Open_Loop_Control_out1_dtc[1] = {{3{Open_Loop_Control_out1[1][17]}}, Open_Loop_Control_out1[1][17:1]}; + assign Open_Loop_Control_out1_dtc[2] = {{3{Open_Loop_Control_out1[2][17]}}, Open_Loop_Control_out1[2][17:1]}; + + + + // /Velocity_Control + velocityControlHdl_velocityControlHdl u_Velocity_Control (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .reset_1(MATLAB_Function_out2), + .command(command), // sfix18_En8 + .measured(rotor_velocity), // sfix18_En8 + .phase_currents_0(phase_currents_0), // sfix18_En15 + .phase_currents_1(phase_currents_1), // sfix18_En15 + .electrical_position(electrical_postion), // sfix18_En14 + .param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16 + .param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15 + .param_current_p_gain(param_current_p_gain), // sfix18_En10 + .param_current_i_gain(param_current_i_gain), // sfix18_En2 + .phase_voltages_0(Velocity_Control_out1_0), // sfix20_En12 + .phase_voltages_1(Velocity_Control_out1_1), // sfix20_En12 + .phase_voltages_2(Velocity_Control_out1_2), // sfix20_En12 + .dq_currents_0(Velocity_Control_out2_0), // sfix18_En15 + .dq_currents_1(Velocity_Control_out2_1) // sfix18_En15 + ); + + assign Velocity_Control_out1[0] = Velocity_Control_out1_0; + assign Velocity_Control_out1[1] = Velocity_Control_out1_1; + assign Velocity_Control_out1[2] = Velocity_Control_out1_2; + + // Stand By mode for controller outputs constant phase voltages. + // + // /StandBy + controllerHdl_StandBy u_StandBy (.Phase_Voltages_0(StandBy_out1_0), // sfix20_En12 + .Phase_Voltages_1(StandBy_out1_1), // sfix20_En12 + .Phase_Voltages_2(StandBy_out1_2) // sfix20_En12 + ); + + assign StandBy_out1[0] = StandBy_out1_0; + assign StandBy_out1[1] = StandBy_out1_1; + assign StandBy_out1[2] = StandBy_out1_2; + + // /Multiport Switch + assign Multiport_Switch_out1[0] = (MATLAB_Function_out1 == 2'b00 ? Open_Loop_Control_out1_dtc[0] : + (MATLAB_Function_out1 == 2'b01 ? Velocity_Control_out1[0] : + StandBy_out1[0])); + assign Multiport_Switch_out1[1] = (MATLAB_Function_out1 == 2'b00 ? Open_Loop_Control_out1_dtc[1] : + (MATLAB_Function_out1 == 2'b01 ? Velocity_Control_out1[1] : + StandBy_out1[1])); + assign Multiport_Switch_out1[2] = (MATLAB_Function_out1 == 2'b00 ? Open_Loop_Control_out1_dtc[2] : + (MATLAB_Function_out1 == 2'b01 ? Velocity_Control_out1[2] : + StandBy_out1[2])); + + + + assign phase_voltages_0 = Multiport_Switch_out1[0]; + + assign phase_voltages_1 = Multiport_Switch_out1[1]; + + assign phase_voltages_2 = Multiport_Switch_out1[2]; + + assign dq_current_0 = Velocity_Control_out2_0; + + assign dq_current_1 = Velocity_Control_out2_1; + + assign electrical_position_ol = Open_Loop_Control_out2; + +endmodule // controllerHdl_Field_Oriented_Control + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Frequency_To_Volts.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Frequency_To_Volts.v new file mode 100644 index 000000000..089f4dd5c --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Frequency_To_Volts.v @@ -0,0 +1,88 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Frequency_To_Volts.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Frequency_To_Volts +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Frequency_To_Volts +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Frequency_To_Volts + ( + F, + param_open_loop_bias, + param_open_loop_scalar, + V + ); + + + input signed [31:0] F; // sfix32_En22 + input signed [17:0] param_open_loop_bias; // sfix18_En14 + input signed [17:0] param_open_loop_scalar; // sfix18_En16 + output signed [17:0] V; // sfix18_En12 + + + wire signed [31:0] Double_Range_out1; // sfix32_En21 + wire signed [17:0] Convert_Data_Type_out1; // sfix18_En7 + wire signed [18:0] Abs1_cast; // sfix19_En7 + wire signed [18:0] Abs1_cast_1; // sfix19_En7 + wire signed [17:0] Abs1_out1; // sfix18_En7 + wire signed [35:0] freq_to_volts; // sfix36_En23 + wire signed [36:0] Add_add_cast; // sfix37_En23 + wire signed [36:0] Add_add_cast_1; // sfix37_En23 + wire signed [36:0] volts; // sfix37_En23 + wire signed [17:0] volts_dt; // sfix18_En12 + + // Frequency To Volts + + + // /Double_Range + controllerHdl_Double_Range u_Double_Range (.In1(F), // sfix32_En22 + .Out1(Double_Range_out1) // sfix32_En21 + ); + + // /Convert_Data_Type + controllerHdl_Convert_Data_Type u_Convert_Data_Type (.In1(Double_Range_out1), // sfix32_En21 + .Out1(Convert_Data_Type_out1) // sfix18_En7 + ); + + // /Abs1 + assign Abs1_cast = Convert_Data_Type_out1; + assign Abs1_cast_1 = - (Abs1_cast); + assign Abs1_out1 = (Convert_Data_Type_out1 < 18'sb000000000000000000 ? $signed(Abs1_cast_1[17:0]) : + Convert_Data_Type_out1); + + + + // /Product + assign freq_to_volts = Abs1_out1 * param_open_loop_scalar; + + + + // /Add + assign Add_add_cast = freq_to_volts; + assign Add_add_cast_1 = {{10{param_open_loop_bias[17]}}, {param_open_loop_bias, 9'b000000000}}; + assign volts = Add_add_cast + Add_add_cast_1; + + + + // /Voltage_Data_Type + assign volts_dt = volts[28:11]; + + + + assign V = volts_dt; + +endmodule // controllerHdl_Frequency_To_Volts + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Generate_Position_And_Voltage_Ramp.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Generate_Position_And_Voltage_Ramp.v new file mode 100644 index 000000000..6fa9ea2c4 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Generate_Position_And_Voltage_Ramp.v @@ -0,0 +1,89 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Generate_Position_And_Voltage_Ramp.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Generate_Position_And_Voltage_Ramp +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Generate_Position_And_Voltage_Ramp + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + target_velocity, + param_open_loop_bias, + param_open_loop_scalar, + Q_Voltage, + Position + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [17:0] target_velocity; // sfix18_En8 + input signed [17:0] param_open_loop_bias; // sfix18_En14 + input signed [17:0] param_open_loop_scalar; // sfix18_En16 + output signed [17:0] Q_Voltage; // sfix18_En12 + output signed [17:0] Position; // sfix18_En14 + + + wire signed [31:0] rotor_velocity; // sfix32_En22 + wire signed [17:0] volts_dt; // sfix18_En12 + wire signed [17:0] electrical_velocity; // sfix18_En6 + wire signed [17:0] electrical_position; // sfix18_En14 + + // Generate Position And Voltage + + + // /Rotor_Acceleration_To_Velocity + controllerHdl_Rotor_Acceleration_To_Velocity u_Rotor_Acceleration_To_Velocity (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(Reset_1), + .Vel_Target(target_velocity), // sfix18_En8 + .RV(rotor_velocity) // sfix32_En22 + ); + + // /Frequency_To_Volts + controllerHdl_Frequency_To_Volts u_Frequency_To_Volts (.F(rotor_velocity), // sfix32_En22 + .param_open_loop_bias(param_open_loop_bias), // sfix18_En14 + .param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16 + .V(volts_dt) // sfix18_En12 + ); + + assign Q_Voltage = volts_dt; + + // /Rotor_To_Electical_Velocity + controllerHdl_Rotor_To_Electical_Velocity u_Rotor_To_Electical_Velocity (.RV(rotor_velocity), // sfix32_En22 + .EV(electrical_velocity) // sfix18_En6 + ); + + // /Electrical_Velocity_To_Position + controllerHdl_Electrical_Velocity_To_Position u_Electrical_Velocity_To_Position (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(Reset_1), + .EV(electrical_velocity), // sfix18_En6 + .EP(electrical_position) // sfix18_En14 + ); + + assign Position = electrical_position; + +endmodule // controllerHdl_Generate_Position_And_Voltage_Ramp + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Inverse_Clarke_Transform.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Inverse_Clarke_Transform.v new file mode 100644 index 000000000..c81b7db9c --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Inverse_Clarke_Transform.v @@ -0,0 +1,110 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Inverse_Clarke_Transform.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Inverse_Clarke_Transform +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Clarke_Transform +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Inverse_Clarke_Transform + ( + alpha_voltage, + beta_voltage, + phase_voltages_0, + phase_voltages_1, + phase_voltages_2 + ); + + + input signed [17:0] alpha_voltage; // sfix18_En10 + input signed [17:0] beta_voltage; // sfix18_En10 + output signed [17:0] phase_voltages_0; // sfix18_En13 + output signed [17:0] phase_voltages_1; // sfix18_En13 + output signed [17:0] phase_voltages_2; // sfix18_En13 + + + wire signed [35:0] voltage_phase_a; // sfix36_En26 + wire signed [35:0] Gain1_out1; // sfix36_En26 + wire signed [35:0] Gain_out1; // sfix36_En26 + wire signed [35:0] voltage_phase_b; // sfix36_En26 + wire signed [37:0] Add1_cast; // sfix38_En26 + wire signed [37:0] Add1_cast_1; // sfix38_En26 + wire signed [37:0] Add1_sub_cast; // sfix38_En26 + wire signed [37:0] Add1_sub_temp; // sfix38_En26 + wire signed [35:0] voltage_phase_c; // sfix36_En26 + wire signed [35:0] Mux_out1 [0:2]; // sfix36_En26 [3] + wire signed [17:0] Current_Data_Type_out1 [0:2]; // sfix18_En13 [3] + + // Inverse Clarke Transform + // + // Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities + // The alpha and beta components are dependent on time and speed. + + + // /Data Type Conversion + assign voltage_phase_a = {{2{alpha_voltage[17]}}, {alpha_voltage, 16'b0000000000000000}}; + + + + // /Gain1 + assign Gain1_out1 = 56756 * beta_voltage; + + + + // /Gain + assign Gain_out1 = {{3{alpha_voltage[17]}}, {alpha_voltage, 15'b000000000000000}}; + + + + // /Add + assign voltage_phase_b = Gain1_out1 - Gain_out1; + + + + // /Add1 + assign Add1_cast = Gain_out1; + assign Add1_cast_1 = - (Add1_cast); + assign Add1_sub_cast = Gain1_out1; + assign Add1_sub_temp = Add1_cast_1 - Add1_sub_cast; + assign voltage_phase_c = Add1_sub_temp[35:0]; + + + + // /Mux + assign Mux_out1[0] = voltage_phase_a; + assign Mux_out1[1] = voltage_phase_b; + assign Mux_out1[2] = voltage_phase_c; + + // /Current_Data_Type + assign Current_Data_Type_out1[0] = ((Mux_out1[0][35] == 1'b0) && (Mux_out1[0][34:30] != 5'b00000) ? 18'sb011111111111111111 : + ((Mux_out1[0][35] == 1'b1) && (Mux_out1[0][34:30] != 5'b11111) ? 18'sb100000000000000000 : + $signed(Mux_out1[0][30:13]))); + assign Current_Data_Type_out1[1] = ((Mux_out1[1][35] == 1'b0) && (Mux_out1[1][34:30] != 5'b00000) ? 18'sb011111111111111111 : + ((Mux_out1[1][35] == 1'b1) && (Mux_out1[1][34:30] != 5'b11111) ? 18'sb100000000000000000 : + $signed(Mux_out1[1][30:13]))); + assign Current_Data_Type_out1[2] = ((Mux_out1[2][35] == 1'b0) && (Mux_out1[2][34:30] != 5'b00000) ? 18'sb011111111111111111 : + ((Mux_out1[2][35] == 1'b1) && (Mux_out1[2][34:30] != 5'b11111) ? 18'sb100000000000000000 : + $signed(Mux_out1[2][30:13]))); + + + + assign phase_voltages_0 = Current_Data_Type_out1[0]; + + assign phase_voltages_1 = Current_Data_Type_out1[1]; + + assign phase_voltages_2 = Current_Data_Type_out1[2]; + +endmodule // controllerHdl_Inverse_Clarke_Transform + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Inverse_Park_Transform.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Inverse_Park_Transform.v new file mode 100644 index 000000000..cc1794c2d --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Inverse_Park_Transform.v @@ -0,0 +1,99 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Inverse_Park_Transform.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Inverse_Park_Transform +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Park_Transform +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Inverse_Park_Transform + ( + direct_voltage, + quadrature_voltage, + sin_coefficient, + cos_coefficient, + alpha_voltage, + beta_voltage + ); + + + input signed [17:0] direct_voltage; // sfix18_En12 + input signed [17:0] quadrature_voltage; // sfix18_En12 + input signed [17:0] sin_coefficient; // sfix18_En16 + input signed [17:0] cos_coefficient; // sfix18_En16 + output signed [17:0] alpha_voltage; // sfix18_En10 + output signed [17:0] beta_voltage; // sfix18_En10 + + + wire signed [35:0] Product2_out1; // sfix36_En28 + wire signed [35:0] Product3_out1; // sfix36_En28 + wire signed [35:0] alpha_voltage_1; // sfix36_En28 + wire signed [17:0] Convert_Data_Type_out1; // sfix18_En10 + wire signed [35:0] Product_out1; // sfix36_En28 + wire signed [35:0] Product1_out1; // sfix36_En28 + wire signed [35:0] beta_voltage_1; // sfix36_En28 + wire signed [17:0] Convert_Data_Type1_out1; // sfix18_En10 + + // Inverse Park Transform + // + // Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) + + + // /Product2 + assign Product2_out1 = direct_voltage * cos_coefficient; + + + + // /Product3 + assign Product3_out1 = quadrature_voltage * sin_coefficient; + + + + // /Add1 + assign alpha_voltage_1 = Product2_out1 - Product3_out1; + + + + // /Convert_Data_Type + controllerHdl_Convert_Data_Type_block2 u_Convert_Data_Type (.In1(alpha_voltage_1), // sfix36_En28 + .Out1(Convert_Data_Type_out1) // sfix18_En10 + ); + + assign alpha_voltage = Convert_Data_Type_out1; + + // /Product + assign Product_out1 = direct_voltage * sin_coefficient; + + + + // /Product1 + assign Product1_out1 = quadrature_voltage * cos_coefficient; + + + + // /Add + assign beta_voltage_1 = Product_out1 + Product1_out1; + + + + // /Convert_Data_Type1 + controllerHdl_Convert_Data_Type1 u_Convert_Data_Type1 (.In1(beta_voltage_1), // sfix36_En28 + .Out1(Convert_Data_Type1_out1) // sfix18_En10 + ); + + assign beta_voltage = Convert_Data_Type1_out1; + +endmodule // controllerHdl_Inverse_Park_Transform + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function.v b/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function.v new file mode 100644 index 000000000..e5e3352c2 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function.v @@ -0,0 +1,44 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_MATLAB_Function +// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits/MATLAB Function +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_MATLAB_Function + ( + u, + y + ); + + + input [35:0] u; // ufix36 + output [17:0] y; // ufix18 + + + + + //MATLAB Function 'Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits/MATLAB Function': ':1' + // Non-tunable mask parameter + //':1:8' + //':1:10' + assign y = u[17:0]; + //':1:14' + + + +endmodule // controllerHdl_MATLAB_Function + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block.v b/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block.v new file mode 100644 index 000000000..9033d7777 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block.v @@ -0,0 +1,46 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_MATLAB_Function_block +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits/MATLAB Function +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_MATLAB_Function_block + ( + u, + y + ); + + + input [17:0] u; // ufix18 + output [8:0] y; // ufix9 + + + wire [8:0] y1; // ufix9_E9 + + + //MATLAB Function 'Open_Loop_Control/Sin_Cos/Mark_Extract_Bits/MATLAB Function': ':1' + // Non-tunable mask parameter + //':1:8' + //':1:10' + assign y1 = u[17:9]; + //':1:14' + assign y = y1; + + + +endmodule // controllerHdl_MATLAB_Function_block + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block1.v b/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block1.v new file mode 100644 index 000000000..78a725fd6 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block1.v @@ -0,0 +1,44 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block1.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_MATLAB_Function_block1 +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits1/MATLAB Function +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_MATLAB_Function_block1 + ( + u, + y + ); + + + input [17:0] u; // ufix18 + output [8:0] y; // ufix9 + + + + + //MATLAB Function 'Open_Loop_Control/Sin_Cos/Mark_Extract_Bits1/MATLAB Function': ':1' + // Non-tunable mask parameter + //':1:8' + //':1:10' + assign y = u[8:0]; + //':1:14' + + + +endmodule // controllerHdl_MATLAB_Function_block1 + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block2.v b/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block2.v new file mode 100644 index 000000000..e882737b1 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block2.v @@ -0,0 +1,94 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block2.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_MATLAB_Function_block2 +// Source Path: controllerHdl/Field_Oriented_Control/MATLAB Function +// Hierarchy Level: 3 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_MATLAB_Function_block2 + ( + CLK_IN, + reset, + enb_1_2000_0, + cMode, + index, + reset_1 + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input [1:0] cMode; // ufix2 + output [1:0] index; // ufix2 + output reset_1; + + parameter [1:0] controllerModeEnum_VelocityControl = 2; // ufix2 + parameter [1:0] controllerModeEnum_OpenLoopVelocityControl = 3; // ufix2 + + reg [1:0] index_1; // ufix2 + reg reset_2; + reg [1:0] index_n1; // ufix2 + reg [1:0] index_n1_next; // ufix2 + reg [1:0] index_2; // ufix2 + + + always @(posedge CLK_IN) + begin : MATLAB_Function_process + if (reset == 1'b1) begin + index_n1 <= 2'b10; + end + else if (enb_1_2000_0) begin + index_n1 <= index_n1_next; + end + end + + always @(cMode, index_n1) begin + //MATLAB Function 'Field_Oriented_Control/MATLAB Function': ':1' + //. + if (cMode == controllerModeEnum_OpenLoopVelocityControl) begin + //':1:17' + index_2 = 2'b00; + end + else if (cMode == controllerModeEnum_VelocityControl) begin + //':1:19' + index_2 = 2'b01; + end + else begin + //':1:21' + index_2 = 2'b10; + end + if (index_2 != index_n1) begin + //':1:25' + reset_2 = 1'b1; + end + else begin + //':1:27' + reset_2 = 1'b0; + end + //':1:29' + index_n1_next = index_2; + index_1 = index_2; + end + + + + assign index = index_1; + + assign reset_1 = reset_2; + +endmodule // controllerHdl_MATLAB_Function_block2 + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block3.v b/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block3.v new file mode 100644 index 000000000..c8f66d564 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block3.v @@ -0,0 +1,152 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block3.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_MATLAB_Function_block3 +// Source Path: controllerHdl/MATLAB Function +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_MATLAB_Function_block3 + ( + CLK_IN, + reset, + enb_1_2000_0, + u, + y + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input signed [18:0] u; // sfix19_En14 + output signed [18:0] y; // sfix19_En14 + + + reg signed [18:0] y_1; // sfix19_En14 + reg sel; + reg [15:0] count_n; // ufix16 + reg [15:0] count_p; // ufix16 + reg signed [18:0] u_n1; // sfix19 + reg signed [18:0] u_filter_p; // sfix19 + reg signed [18:0] u_filter_n; // sfix19 + reg sel_next; + reg [15:0] count_n_next; // ufix16 + reg [15:0] count_p_next; // ufix16 + reg signed [18:0] u_n1_next; // sfix19_En14 + reg signed [18:0] u_filter_p_next; // sfix19_En14 + reg signed [18:0] u_filter_n_next; // sfix19_En14 + reg signed [37:0] a1_1; // sfix38_En28 + reg signed [37:0] b1_1; // sfix38_En28 + reg signed [37:0] c1_1; // sfix38_En28 + reg signed [37:0] a1_0_1; // sfix38_En28 + reg signed [37:0] b1_0_1; // sfix38_En28 + reg signed [37:0] c1_0_1; // sfix38_En28 + reg sel_temp_1; + reg signed [18:0] u_filter_p_temp_1; // sfix19_En14 + reg signed [18:0] u_filter_n_temp_1; // sfix19_En14 + + + always @(posedge CLK_IN) + begin : MATLAB_Function_process + if (reset == 1'b1) begin + sel <= 1'b0; + u_n1 <= 19'sb0000000000000000000; + u_filter_p <= 19'sb0000000000000000000; + u_filter_n <= 19'sb0000000000000000000; + count_n <= 16'b0000000000000000; + count_p <= 16'b0000000000000000; + end + else if (enb_1_2000_0) begin + sel <= sel_next; + count_n <= count_n_next; + count_p <= count_p_next; + u_n1 <= u_n1_next; + u_filter_p <= u_filter_p_next; + u_filter_n <= u_filter_n_next; + end + end + + always @(u, sel, count_n, count_p, u_n1, u_filter_p, u_filter_n) begin + sel_temp_1 = sel; + u_filter_p_temp_1 = u_filter_p; + u_filter_n_temp_1 = u_filter_n; + count_n_next = count_n; + count_p_next = count_p; + //MATLAB Function 'MATLAB Function': ':1' + if ((u < 19'sb0000000000000000000) && (u_n1 > 19'sb0000000000000000000)) begin + //':1:25' + sel_temp_1 = count_p > count_n; + //':1:26' + count_n_next = 16'b0000000000000000; + //':1:27' + count_p_next = 16'b0000000000000000; + end + else if (u > 19'sb0000000000000000000) begin + //':1:31' + a1_0_1 = 14336 * u_filter_p; + b1_0_1 = {{8{u[18]}}, {u, 11'b00000000000}}; + c1_0_1 = a1_0_1 + b1_0_1; + if (((c1_0_1[37] == 1'b0) && (c1_0_1[36:32] != 5'b00000)) || ((c1_0_1[37] == 1'b0) && (c1_0_1[32:14] == 19'sb0111111111111111111))) begin + u_filter_p_temp_1 = 19'sb0111111111111111111; + end + else if ((c1_0_1[37] == 1'b1) && (c1_0_1[36:32] != 5'b11111)) begin + u_filter_p_temp_1 = 19'sb1000000000000000000; + end + else begin + u_filter_p_temp_1 = c1_0_1[32:14] + $signed({1'b0, c1_0_1[13]}); + end + //':1:32' + count_p_next = count_p + 1; + end + else begin + //':1:34' + a1_1 = 14336 * u_filter_n; + b1_1 = {{8{u[18]}}, {u, 11'b00000000000}}; + c1_1 = a1_1 + b1_1; + if (((c1_1[37] == 1'b0) && (c1_1[36:32] != 5'b00000)) || ((c1_1[37] == 1'b0) && (c1_1[32:14] == 19'sb0111111111111111111))) begin + u_filter_n_temp_1 = 19'sb0111111111111111111; + end + else if ((c1_1[37] == 1'b1) && (c1_1[36:32] != 5'b11111)) begin + u_filter_n_temp_1 = 19'sb1000000000000000000; + end + else begin + u_filter_n_temp_1 = c1_1[32:14] + $signed({1'b0, c1_1[13]}); + end + //':1:35' + count_n_next = count_n + 1; + end + //':1:39' + u_n1_next = u; + if (sel_temp_1) begin + //':1:40' + //':1:41' + y_1 = u_filter_p_temp_1; + end + else begin + //':1:43' + y_1 = u_filter_n_temp_1; + end + sel_next = sel_temp_1; + u_filter_p_next = u_filter_p_temp_1; + u_filter_n_next = u_filter_n_temp_1; + end + + + + assign y = y_1; + +endmodule // controllerHdl_MATLAB_Function_block3 + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits.v new file mode 100644 index 000000000..5a7c9f191 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mark_Extract_Bits.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Mark_Extract_Bits +// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Mark_Extract_Bits + ( + In1, + Out1 + ); + + + input [35:0] In1; // ufix36 + output [17:0] Out1; // ufix18 + + + wire [17:0] MATLAB_Function_out1; // ufix18 + + + // /MATLAB Function + controllerHdl_MATLAB_Function u_MATLAB_Function (.u(In1), // ufix36 + .y(MATLAB_Function_out1) // ufix18 + ); + + assign Out1 = MATLAB_Function_out1; + +endmodule // controllerHdl_Mark_Extract_Bits + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits1.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits1.v new file mode 100644 index 000000000..6ef693eb4 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits1.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mark_Extract_Bits1.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Mark_Extract_Bits1 +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits1 +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Mark_Extract_Bits1 + ( + In1, + Out1 + ); + + + input [17:0] In1; // ufix18 + output [8:0] Out1; // ufix9 + + + wire [8:0] MATLAB_Function_out1; // ufix9 + + + // /MATLAB Function + controllerHdl_MATLAB_Function_block1 u_MATLAB_Function (.u(In1), // ufix18 + .y(MATLAB_Function_out1) // ufix9 + ); + + assign Out1 = MATLAB_Function_out1; + +endmodule // controllerHdl_Mark_Extract_Bits1 + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits_block.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits_block.v new file mode 100644 index 000000000..294a904df --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits_block.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mark_Extract_Bits_block.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Mark_Extract_Bits_block +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Mark_Extract_Bits_block + ( + In1, + Out1 + ); + + + input [17:0] In1; // ufix18 + output [8:0] Out1; // ufix9 + + + wire [8:0] MATLAB_Function_out1; // ufix9 + + + // /MATLAB Function + controllerHdl_MATLAB_Function_block u_MATLAB_Function (.u(In1), // ufix18 + .y(MATLAB_Function_out1) // ufix9 + ); + + assign Out1 = MATLAB_Function_out1; + +endmodule // controllerHdl_Mark_Extract_Bits_block + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Mod_2pi_Scale_And_Bit_Slice.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Mod_2pi_Scale_And_Bit_Slice.v new file mode 100644 index 000000000..7d82518da --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Mod_2pi_Scale_And_Bit_Slice.v @@ -0,0 +1,61 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mod_2pi_Scale_And_Bit_Slice.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Mod_2pi_Scale_And_Bit_Slice +// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Mod_2pi_Scale_And_Bit_Slice + ( + u, + y + ); + + + input signed [17:0] u; // sfix18_En12 + output signed [17:0] y; // sfix18_En14 + + + wire signed [35:0] Pre_Scale_mul_temp; // sfix36_En13 + wire [35:0] Pre_Scale_out1; // ufix36 + wire [17:0] y_1; // ufix18 + wire [35:0] Post_Scale_mul_temp; // ufix36_En33 + wire signed [17:0] Post_Scale_out1; // sfix18_En14 + + + // /Pre_Scale + // + // /Remove Scaling + assign Pre_Scale_mul_temp = 83443 * u; + assign Pre_Scale_out1 = {{13{Pre_Scale_mul_temp[35]}}, Pre_Scale_mul_temp[35:13]}; + + + + // /Mark_Extract_Bits + controllerHdl_Mark_Extract_Bits u_Mark_Extract_Bits (.In1(Pre_Scale_out1), // ufix36 + .Out1(y_1) // ufix18 + ); + + // /Post_Scale + assign Post_Scale_mul_temp = 205888 * y_1; + assign Post_Scale_out1 = Post_Scale_mul_temp[35:19]; + + + + assign y = Post_Scale_out1; + +endmodule // controllerHdl_Mod_2pi_Scale_And_Bit_Slice + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Open_Loop_Control.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Open_Loop_Control.v new file mode 100644 index 000000000..fb7c9fd07 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Open_Loop_Control.v @@ -0,0 +1,102 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Open_Loop_Control.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Open_Loop_Control +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control +// Hierarchy Level: 3 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Open_Loop_Control + ( + CLK_IN, + reset, + enb_1_2000_0, + reset_1, + command_value, + param_open_loop_bias, + param_open_loop_scalar, + phase_voltages_0, + phase_voltages_1, + phase_voltages_2, + electrical_position + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input reset_1; + input signed [17:0] command_value; // sfix18_En8 + input signed [17:0] param_open_loop_bias; // sfix18_En14 + input signed [17:0] param_open_loop_scalar; // sfix18_En16 + output signed [17:0] phase_voltages_0; // sfix18_En13 + output signed [17:0] phase_voltages_1; // sfix18_En13 + output signed [17:0] phase_voltages_2; // sfix18_En13 + output signed [17:0] electrical_position; // sfix18_En14 + + + wire signed [17:0] direct_voltage; // sfix18_En12 + wire signed [17:0] volts_dt; // sfix18_En12 + wire signed [17:0] Generate_Position_And_Voltage_Ramp_out2; // sfix18_En14 + wire signed [17:0] sin_coefficient; // sfix18_En16 + wire signed [17:0] cos_coefficient; // sfix18_En16 + wire signed [17:0] Transform_dq_to_ABC_out1_0; // sfix18_En13 + wire signed [17:0] Transform_dq_to_ABC_out1_1; // sfix18_En13 + wire signed [17:0] Transform_dq_to_ABC_out1_2; // sfix18_En13 + + + // /Zero + assign direct_voltage = 18'sb000000000000000000; + + + + // /Generate_Position_And_Voltage_Ramp + controllerHdl_Generate_Position_And_Voltage_Ramp u_Generate_Position_And_Voltage_Ramp (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(reset_1), + .target_velocity(command_value), // sfix18_En8 + .param_open_loop_bias(param_open_loop_bias), // sfix18_En14 + .param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16 + .Q_Voltage(volts_dt), // sfix18_En12 + .Position(Generate_Position_And_Voltage_Ramp_out2) // sfix18_En14 + ); + + // /Sin_Cos + controllerHdl_Sin_Cos u_Sin_Cos (.x(Generate_Position_And_Voltage_Ramp_out2), // sfix18_En14 + .sin(sin_coefficient), // sfix18_En16 + .cos(cos_coefficient) // sfix18_En16 + ); + + // /Transform_dq_to_ABC + controllerHdl_Transform_dq_to_ABC u_Transform_dq_to_ABC (.d(direct_voltage), // sfix18_En12 + .q(volts_dt), // sfix18_En12 + .sin(sin_coefficient), // sfix18_En16 + .cos(cos_coefficient), // sfix18_En16 + .ABC_0(Transform_dq_to_ABC_out1_0), // sfix18_En13 + .ABC_1(Transform_dq_to_ABC_out1_1), // sfix18_En13 + .ABC_2(Transform_dq_to_ABC_out1_2) // sfix18_En13 + ); + + assign phase_voltages_0 = Transform_dq_to_ABC_out1_0; + + assign phase_voltages_1 = Transform_dq_to_ABC_out1_1; + + assign phase_voltages_2 = Transform_dq_to_ABC_out1_2; + + assign electrical_position = Generate_Position_And_Voltage_Ramp_out2; + +endmodule // controllerHdl_Open_Loop_Control + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Phase_Voltages_To_Compare_Values.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Phase_Voltages_To_Compare_Values.v new file mode 100644 index 000000000..428d22e40 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Phase_Voltages_To_Compare_Values.v @@ -0,0 +1,112 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Phase_Voltages_To_Compare_Values.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Phase_Voltages_To_Compare_Values +// Source Path: controllerHdl/Phase_Voltages_To_Compare_Values +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Phase_Voltages_To_Compare_Values + ( + V_0, + V_1, + V_2, + C_0, + C_1, + C_2 + ); + + + input signed [19:0] V_0; // sfix20_En12 + input signed [19:0] V_1; // sfix20_En12 + input signed [19:0] V_2; // sfix20_En12 + output [15:0] C_0; // uint16 + output [15:0] C_1; // uint16 + output [15:0] C_2; // uint16 + + + wire signed [19:0] V [0:2]; // sfix20_En12 [3] + wire signed [19:0] Half_Bus_Voltage_out1; // sfix20_En12 + wire signed [20:0] Add2_v; // sfix21_En12 + wire signed [20:0] Add2_add_cast; // sfix21_En12 + wire signed [20:0] Add2_add_temp; // sfix21_En12 + wire signed [20:0] Add2_add_cast_1; // sfix21_En12 + wire signed [20:0] Add2_add_temp_1; // sfix21_En12 + wire signed [20:0] Add2_add_cast_2; // sfix21_En12 + wire signed [20:0] Add2_add_temp_2; // sfix21_En12 + wire signed [19:0] Add2_out1 [0:2]; // sfix20_En12 [3] + wire signed [39:0] Voltage_To_PWM_Compare_Units_out1 [0:2]; // sfix40_En24 [3] + wire signed [39:0] Saturation1_out1 [0:2]; // sfix40_En24 [3] + wire [15:0] pwm_compare [0:2]; // uint16 [3] + + + assign V[0] = V_0; + assign V[1] = V_1; + assign V[2] = V_2; + + // /Half_Bus_Voltage + assign Half_Bus_Voltage_out1 = 20'sb00000110000000000000; + + + + // /Add2 + assign Add2_v = Half_Bus_Voltage_out1; + assign Add2_add_cast = V[0]; + assign Add2_add_temp = Add2_add_cast + Add2_v; + assign Add2_out1[0] = Add2_add_temp[19:0]; + assign Add2_add_cast_1 = V[1]; + assign Add2_add_temp_1 = Add2_add_cast_1 + Add2_v; + assign Add2_out1[1] = Add2_add_temp_1[19:0]; + assign Add2_add_cast_2 = V[2]; + assign Add2_add_temp_2 = Add2_add_cast_2 + Add2_v; + assign Add2_out1[2] = Add2_add_temp_2[19:0]; + + + + // /Voltage_To_PWM_Compare_Units + assign Voltage_To_PWM_Compare_Units_out1[0] = 341333 * Add2_out1[0]; + assign Voltage_To_PWM_Compare_Units_out1[1] = 341333 * Add2_out1[1]; + assign Voltage_To_PWM_Compare_Units_out1[2] = 341333 * Add2_out1[2]; + + + + // /Saturation1 + assign Saturation1_out1[0] = (Voltage_To_PWM_Compare_Units_out1[0] > 40'sh03E8000000 ? 40'sh03E8000000 : + (Voltage_To_PWM_Compare_Units_out1[0] < 40'sh0000000000 ? 40'sh0000000000 : + Voltage_To_PWM_Compare_Units_out1[0])); + assign Saturation1_out1[1] = (Voltage_To_PWM_Compare_Units_out1[1] > 40'sh03E8000000 ? 40'sh03E8000000 : + (Voltage_To_PWM_Compare_Units_out1[1] < 40'sh0000000000 ? 40'sh0000000000 : + Voltage_To_PWM_Compare_Units_out1[1])); + assign Saturation1_out1[2] = (Voltage_To_PWM_Compare_Units_out1[2] > 40'sh03E8000000 ? 40'sh03E8000000 : + (Voltage_To_PWM_Compare_Units_out1[2] < 40'sh0000000000 ? 40'sh0000000000 : + Voltage_To_PWM_Compare_Units_out1[2])); + + + + // /Data Type Conversion1 + assign pwm_compare[0] = Saturation1_out1[0][39:24]; + assign pwm_compare[1] = Saturation1_out1[1][39:24]; + assign pwm_compare[2] = Saturation1_out1[2][39:24]; + + + + assign C_0 = pwm_compare[0]; + + assign C_1 = pwm_compare[1]; + + assign C_2 = pwm_compare[2]; + +endmodule // controllerHdl_Phase_Voltages_To_Compare_Values + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Reset_Delay.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Reset_Delay.v new file mode 100644 index 000000000..23f6c5ab0 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Reset_Delay.v @@ -0,0 +1,85 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Reset_Delay.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Reset_Delay +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Electrical_Velocity_To_Position/Reset_Delay +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Reset_Delay + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + In, + Out + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [31:0] In; // sfix32_En27 + output signed [31:0] Out; // sfix32_En27 + + + wire signed [31:0] Constant1_out1; // sfix32_En27 + wire signed [31:0] Reset_Switch1_out1; // sfix32_En27 + reg signed [31:0] In_Delay_out1; // sfix32_En27 + wire signed [31:0] Constant_out1; // sfix32_En27 + wire signed [31:0] Reset_Switch_out1; // sfix32_En27 + + + // /Constant1 + assign Constant1_out1 = 32'sb00000000000000000000000000000000; + + + + // /Reset_Switch1 + assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In : + Constant1_out1); + + + + // /In_Delay + always @(posedge CLK_IN) + begin : In_Delay_process + if (reset == 1'b1) begin + In_Delay_out1 <= 32'sb00000000000000000000000000000000; + end + else if (enb_1_2000_0) begin + In_Delay_out1 <= Reset_Switch1_out1; + end + end + + + + // /Constant + assign Constant_out1 = 32'sb00000000000000000000000000000000; + + + + // /Reset_Switch + assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 : + Constant_out1); + + + + assign Out = Reset_Switch_out1; + +endmodule // controllerHdl_Reset_Delay + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Reset_Delay_block.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Reset_Delay_block.v new file mode 100644 index 000000000..88f7109a0 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Reset_Delay_block.v @@ -0,0 +1,85 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Reset_Delay_block.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Reset_Delay_block +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity/Reset_Delay +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Reset_Delay_block + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + In, + Out + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [31:0] In; // sfix32_En22 + output signed [31:0] Out; // sfix32_En22 + + + wire signed [31:0] Constant1_out1; // sfix32_En22 + wire signed [31:0] Reset_Switch1_out1; // sfix32_En22 + reg signed [31:0] In_Delay_out1; // sfix32_En22 + wire signed [31:0] Constant_out1; // sfix32_En22 + wire signed [31:0] Reset_Switch_out1; // sfix32_En22 + + + // /Constant1 + assign Constant1_out1 = 32'sb00000000000000000000000000000000; + + + + // /Reset_Switch1 + assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In : + Constant1_out1); + + + + // /In_Delay + always @(posedge CLK_IN) + begin : In_Delay_process + if (reset == 1'b1) begin + In_Delay_out1 <= 32'sb00000000000000000000000000000000; + end + else if (enb_1_2000_0) begin + In_Delay_out1 <= Reset_Switch1_out1; + end + end + + + + // /Constant + assign Constant_out1 = 32'sb00000000000000000000000000000000; + + + + // /Reset_Switch + assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 : + Constant_out1); + + + + assign Out = Reset_Switch_out1; + +endmodule // controllerHdl_Reset_Delay_block + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_Acceleration_To_Velocity.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_Acceleration_To_Velocity.v new file mode 100644 index 000000000..e348dc467 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_Acceleration_To_Velocity.v @@ -0,0 +1,93 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Rotor_Acceleration_To_Velocity.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Rotor_Acceleration_To_Velocity +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Rotor_Acceleration_To_Velocity + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + Vel_Target, + RV + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [17:0] Vel_Target; // sfix18_En8 + output signed [31:0] RV; // sfix32_En22 + + + wire signed [31:0] Reset_Delay_out1; // sfix32_En22 + wire signed [17:0] Set_Acceleration_out1; // sfix18_En10 + wire signed [35:0] Gain_out1; // sfix36_En41 + wire signed [31:0] Convert_out1; // sfix32_En22 + wire signed [32:0] Sum_add_cast; // sfix33_En22 + wire signed [32:0] Sum_add_cast_1; // sfix33_En22 + wire signed [32:0] Sum_add_temp; // sfix33_En22 + wire signed [31:0] Sum_out1; // sfix32_En22 + + // Rotor Acceleration To Velocity + + + // /Set_Acceleration + controllerHdl_Set_Acceleration u_Set_Acceleration (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .v_target(Vel_Target), // sfix18_En8 + .v_current(Reset_Delay_out1), // sfix32_En22 + .a(Set_Acceleration_out1) // sfix18_En10 + ); + + // /Gain + assign Gain_out1 = 85899 * Set_Acceleration_out1; + + + + // /Convert + assign Convert_out1 = {{15{Gain_out1[35]}}, Gain_out1[35:19]}; + + + + // /Sum + assign Sum_add_cast = Convert_out1; + assign Sum_add_cast_1 = Reset_Delay_out1; + assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1; + assign Sum_out1 = ((Sum_add_temp[32] == 1'b0) && (Sum_add_temp[31] != 1'b0) ? 32'sb01111111111111111111111111111111 : + ((Sum_add_temp[32] == 1'b1) && (Sum_add_temp[31] != 1'b1) ? 32'sb10000000000000000000000000000000 : + $signed(Sum_add_temp[31:0]))); + + + + // /Reset_Delay + controllerHdl_Reset_Delay_block u_Reset_Delay (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(Reset_1), + .In(Sum_out1), // sfix32_En22 + .Out(Reset_Delay_out1) // sfix32_En22 + ); + + assign RV = Reset_Delay_out1; + +endmodule // controllerHdl_Rotor_Acceleration_To_Velocity + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_To_Electical_Velocity.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_To_Electical_Velocity.v new file mode 100644 index 000000000..3daed9536 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_To_Electical_Velocity.v @@ -0,0 +1,57 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Rotor_To_Electical_Velocity.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Rotor_To_Electical_Velocity +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_To_Electical_Velocity +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Rotor_To_Electical_Velocity + ( + RV, + EV + ); + + + input signed [31:0] RV; // sfix32_En22 + output signed [17:0] EV; // sfix18_En6 + + + wire signed [17:0] Convert_Data_Type_out1; // sfix18_En8 + wire signed [35:0] number_of_pole_pairs_out1; // sfix36_En22 + wire signed [17:0] Electrical_Velocity_Data_Type_out1; // sfix18_En6 + + // Rotor To Electrical Velocity + + + // /Convert_Data_Type + controllerHdl_Convert_Data_Type_block u_Convert_Data_Type (.In1(RV), // sfix32_En22 + .Out1(Convert_Data_Type_out1) // sfix18_En8 + ); + + // /number_of_pole_pairs + assign number_of_pole_pairs_out1 = {{2{Convert_Data_Type_out1[17]}}, {Convert_Data_Type_out1, 16'b0000000000000000}}; + + + + // /Electrical_Velocity_Data_Type + assign Electrical_Velocity_Data_Type_out1 = number_of_pole_pairs_out1[33:16]; + + + + assign EV = Electrical_Velocity_Data_Type_out1; + +endmodule // controllerHdl_Rotor_To_Electical_Velocity + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_To_Electrical_Position.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_To_Electrical_Position.v new file mode 100644 index 000000000..b5e25fb78 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_To_Electrical_Position.v @@ -0,0 +1,53 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Rotor_To_Electrical_Position.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Rotor_To_Electrical_Position +// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position +// Hierarchy Level: 3 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Rotor_To_Electrical_Position + ( + R, + E + ); + + + input signed [17:0] R; // sfix18_En14 + output signed [17:0] E; // sfix18_En14 + + + wire signed [35:0] number_of_pole_pairs_cast; // sfix36_En28 + wire signed [17:0] number_of_pole_pairs_out1; // sfix18_En12 + wire signed [17:0] Mod_2pi_Scale_And_Bit_Slice_out1; // sfix18_En14 + + // Rotor To Electrical Position + + + // /number_of_pole_pairs + assign number_of_pole_pairs_cast = {{2{R[17]}}, {R, 16'b0000000000000000}}; + assign number_of_pole_pairs_out1 = number_of_pole_pairs_cast[33:16]; + + + + // /Mod_2pi_Scale_And_Bit_Slice + controllerHdl_Mod_2pi_Scale_And_Bit_Slice u_Mod_2pi_Scale_And_Bit_Slice (.u(number_of_pole_pairs_out1), // sfix18_En12 + .y(Mod_2pi_Scale_And_Bit_Slice_out1) // sfix18_En14 + ); + + assign E = Mod_2pi_Scale_And_Bit_Slice_out1; + +endmodule // controllerHdl_Rotor_To_Electrical_Position + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Set_Acceleration.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Set_Acceleration.v new file mode 100644 index 000000000..2cfa20bf7 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Set_Acceleration.v @@ -0,0 +1,186 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Set_Acceleration.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Set_Acceleration +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity/Set_Acceleration +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Set_Acceleration + ( + CLK_IN, + reset, + enb_1_2000_0, + v_target, + v_current, + a + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input signed [17:0] v_target; // sfix18_En8 + input signed [31:0] v_current; // sfix32_En22 + output signed [17:0] a; // sfix18_En10 + + + wire signed [31:0] Relational_Operator_1_cast; // sfix32_En22 + wire Relational_Operator_relop1; + wire current_less_than_target; + wire current_less_than_target_1; + wire current_greater_than_target; + wire target_has_changed; + wire Latch_out1; + reg Delay1_out1; + wire Latch_out1_1; + wire negative_direction; + wire switch_compare_1; + wire signed [17:0] Acceleration1_out1; // sfix18_En10 + wire signed [18:0] Neg_cast; // sfix19_En10 + wire signed [18:0] Neg_cast_1; // sfix19_En10 + wire signed [35:0] Neg_cast_2; // sfix36_En27 + wire signed [17:0] Neg_out1; // sfix18_En10 + wire current_greater_than_target_1; + wire stop_positive_acceleration; + wire current_less_than_target_2; + wire stop_negative_acceleration; + wire stop_positive_acceleration_1; + wire stop_accelerating; + wire signed [17:0] positive_accleration; // sfix18_En10 + wire signed [17:0] accleration; // sfix18_En10 + wire signed [17:0] Constant_out1; // sfix18_En10 + wire signed [17:0] Switch_Stop_out1; // sfix18_En10 + + // Set Acceleration + + + // /Relational Operator + assign Relational_Operator_1_cast = {v_target, 14'b00000000000000}; + assign Relational_Operator_relop1 = (Relational_Operator_1_cast > v_current ? 1'b1 : + 1'b0); + + + + assign current_less_than_target = Relational_Operator_relop1; + + // /NOT2 + assign current_less_than_target_1 = ~ current_less_than_target; + + + + assign current_greater_than_target = current_less_than_target_1; + + // /Detect_Change + controllerHdl_Detect_Change u_Detect_Change (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .x(v_target), // sfix18_En8 + .y(target_has_changed) + ); + + // /Delay1 + always @(posedge CLK_IN) + begin : Delay1_process + if (reset == 1'b1) begin + Delay1_out1 <= 1'b0; + end + else if (enb_1_2000_0) begin + Delay1_out1 <= Latch_out1; + end + end + + + + // /Latch + // + // /Signal Specification + assign Latch_out1 = (target_has_changed == 1'b0 ? Delay1_out1 : + current_less_than_target); + + + + // /NOT3 + assign Latch_out1_1 = ~ Latch_out1; + + + + assign negative_direction = Latch_out1_1; + + assign switch_compare_1 = (Latch_out1 > 1'b0 ? 1'b1 : + 1'b0); + + + + // /Acceleration1 + assign Acceleration1_out1 = 18'sb001010000000000000; + + + + // /Neg + assign Neg_cast = Acceleration1_out1; + assign Neg_cast_1 = - (Neg_cast); + assign Neg_cast_2 = {Neg_cast_1, 17'b00000000000000000}; + assign Neg_out1 = Neg_cast_2[34:17]; + + + + // /AND_Pos + assign current_greater_than_target_1 = current_greater_than_target & Latch_out1; + + + + assign stop_positive_acceleration = current_greater_than_target_1; + + // /AND_Neg + assign current_less_than_target_2 = current_less_than_target & negative_direction; + + + + assign stop_negative_acceleration = current_less_than_target_2; + + // /OR_SAT1 + assign stop_positive_acceleration_1 = stop_positive_acceleration | stop_negative_acceleration; + + + + assign stop_accelerating = stop_positive_acceleration_1; + + // /Acceleration + assign positive_accleration = 18'sb001010000000000000; + + + + // /Switch_Dir + assign accleration = (switch_compare_1 == 1'b0 ? Neg_out1 : + positive_accleration); + + + + // /Constant + assign Constant_out1 = 18'sb000000000000000000; + + + + // /Switch_Stop + assign Switch_Stop_out1 = (stop_accelerating == 1'b0 ? accleration : + Constant_out1); + + + + assign a = Switch_Stop_out1; + +endmodule // controllerHdl_Set_Acceleration + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Sin_Cos.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Sin_Cos.v new file mode 100644 index 000000000..5b5325ab9 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Sin_Cos.v @@ -0,0 +1,4230 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Sin_Cos.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Sin_Cos +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Sin_Cos + ( + x, + sin, + cos + ); + + + input signed [17:0] x; // sfix18_En14 + output signed [17:0] sin; // sfix18_En16 + output signed [17:0] cos; // sfix18_En16 + + parameter signed [17:0] t1_re_0 = 65536; // sfix18 + parameter signed [17:0] t1_re_1 = 65531; // sfix18 + parameter signed [17:0] t1_re_2 = 65516; // sfix18 + parameter signed [17:0] t1_re_3 = 65492; // sfix18 + parameter signed [17:0] t1_re_4 = 65457; // sfix18 + parameter signed [17:0] t1_re_5 = 65413; // sfix18 + parameter signed [17:0] t1_re_6 = 65358; // sfix18 + parameter signed [17:0] t1_re_7 = 65294; // sfix18 + parameter signed [17:0] t1_re_8 = 65220; // sfix18 + parameter signed [17:0] t1_re_9 = 65137; // sfix18 + parameter signed [17:0] t1_re_10 = 65043; // sfix18 + parameter signed [17:0] t1_re_11 = 64940; // sfix18 + parameter signed [17:0] t1_re_12 = 64827; // sfix18 + parameter signed [17:0] t1_re_13 = 64704; // sfix18 + parameter signed [17:0] t1_re_14 = 64571; // sfix18 + parameter signed [17:0] t1_re_15 = 64429; // sfix18 + parameter signed [17:0] t1_re_16 = 64277; // sfix18 + parameter signed [17:0] t1_re_17 = 64115; // sfix18 + parameter signed [17:0] t1_re_18 = 63944; // sfix18 + parameter signed [17:0] t1_re_19 = 63763; // sfix18 + parameter signed [17:0] t1_re_20 = 63572; // sfix18 + parameter signed [17:0] t1_re_21 = 63372; // sfix18 + parameter signed [17:0] t1_re_22 = 63162; // sfix18 + parameter signed [17:0] t1_re_23 = 62943; // sfix18 + parameter signed [17:0] t1_re_24 = 62714; // sfix18 + parameter signed [17:0] t1_re_25 = 62476; // sfix18 + parameter signed [17:0] t1_re_26 = 62228; // sfix18 + parameter signed [17:0] t1_re_27 = 61971; // sfix18 + parameter signed [17:0] t1_re_28 = 61705; // sfix18 + parameter signed [17:0] t1_re_29 = 61429; // sfix18 + parameter signed [17:0] t1_re_30 = 61145; // sfix18 + parameter signed [17:0] t1_re_31 = 60851; // sfix18 + parameter signed [17:0] t1_re_32 = 60547; // sfix18 + parameter signed [17:0] t1_re_33 = 60235; // sfix18 + parameter signed [17:0] t1_re_34 = 59914; // sfix18 + parameter signed [17:0] t1_re_35 = 59583; // sfix18 + parameter signed [17:0] t1_re_36 = 59244; // sfix18 + parameter signed [17:0] t1_re_37 = 58896; // sfix18 + parameter signed [17:0] t1_re_38 = 58538; // sfix18 + parameter signed [17:0] t1_re_39 = 58172; // sfix18 + parameter signed [17:0] t1_re_40 = 57798; // sfix18 + parameter signed [17:0] t1_re_41 = 57414; // sfix18 + parameter signed [17:0] t1_re_42 = 57022; // sfix18 + parameter signed [17:0] t1_re_43 = 56621; // sfix18 + parameter signed [17:0] t1_re_44 = 56212; // sfix18 + parameter signed [17:0] t1_re_45 = 55794; // sfix18 + parameter signed [17:0] t1_re_46 = 55368; // sfix18 + parameter signed [17:0] t1_re_47 = 54934; // sfix18 + parameter signed [17:0] t1_re_48 = 54491; // sfix18 + parameter signed [17:0] t1_re_49 = 54040; // sfix18 + parameter signed [17:0] t1_re_50 = 53581; // sfix18 + parameter signed [17:0] t1_re_51 = 53114; // sfix18 + parameter signed [17:0] t1_re_52 = 52639; // sfix18 + parameter signed [17:0] t1_re_53 = 52156; // sfix18 + parameter signed [17:0] t1_re_54 = 51665; // sfix18 + parameter signed [17:0] t1_re_55 = 51166; // sfix18 + parameter signed [17:0] t1_re_56 = 50660; // sfix18 + parameter signed [17:0] t1_re_57 = 50146; // sfix18 + parameter signed [17:0] t1_re_58 = 49624; // sfix18 + parameter signed [17:0] t1_re_59 = 49095; // sfix18 + parameter signed [17:0] t1_re_60 = 48559; // sfix18 + parameter signed [17:0] t1_re_61 = 48015; // sfix18 + parameter signed [17:0] t1_re_62 = 47464; // sfix18 + parameter signed [17:0] t1_re_63 = 46906; // sfix18 + parameter signed [17:0] t1_re_64 = 46341; // sfix18 + parameter signed [17:0] t1_re_65 = 45769; // sfix18 + parameter signed [17:0] t1_re_66 = 45190; // sfix18 + parameter signed [17:0] t1_re_67 = 44604; // sfix18 + parameter signed [17:0] t1_re_68 = 44011; // sfix18 + parameter signed [17:0] t1_re_69 = 43412; // sfix18 + parameter signed [17:0] t1_re_70 = 42806; // sfix18 + parameter signed [17:0] t1_re_71 = 42194; // sfix18 + parameter signed [17:0] t1_re_72 = 41576; // sfix18 + parameter signed [17:0] t1_re_73 = 40951; // sfix18 + parameter signed [17:0] t1_re_74 = 40320; // sfix18 + parameter signed [17:0] t1_re_75 = 39683; // sfix18 + parameter signed [17:0] t1_re_76 = 39040; // sfix18 + parameter signed [17:0] t1_re_77 = 38391; // sfix18 + parameter signed [17:0] t1_re_78 = 37736; // sfix18 + parameter signed [17:0] t1_re_79 = 37076; // sfix18 + parameter signed [17:0] t1_re_80 = 36410; // sfix18 + parameter signed [17:0] t1_re_81 = 35738; // sfix18 + parameter signed [17:0] t1_re_82 = 35062; // sfix18 + parameter signed [17:0] t1_re_83 = 34380; // sfix18 + parameter signed [17:0] t1_re_84 = 33692; // sfix18 + parameter signed [17:0] t1_re_85 = 33000; // sfix18 + parameter signed [17:0] t1_re_86 = 32303; // sfix18 + parameter signed [17:0] t1_re_87 = 31600; // sfix18 + parameter signed [17:0] t1_re_88 = 30893; // sfix18 + parameter signed [17:0] t1_re_89 = 30182; // sfix18 + parameter signed [17:0] t1_re_90 = 29466; // sfix18 + parameter signed [17:0] t1_re_91 = 28745; // sfix18 + parameter signed [17:0] t1_re_92 = 28020; // sfix18 + parameter signed [17:0] t1_re_93 = 27291; // sfix18 + parameter signed [17:0] t1_re_94 = 26558; // sfix18 + parameter signed [17:0] t1_re_95 = 25821; // sfix18 + parameter signed [17:0] t1_re_96 = 25080; // sfix18 + parameter signed [17:0] t1_re_97 = 24335; // sfix18 + parameter signed [17:0] t1_re_98 = 23586; // sfix18 + parameter signed [17:0] t1_re_99 = 22834; // sfix18 + parameter signed [17:0] t1_re_100 = 22078; // sfix18 + parameter signed [17:0] t1_re_101 = 21320; // sfix18 + parameter signed [17:0] t1_re_102 = 20557; // sfix18 + parameter signed [17:0] t1_re_103 = 19792; // sfix18 + parameter signed [17:0] t1_re_104 = 19024; // sfix18 + parameter signed [17:0] t1_re_105 = 18253; // sfix18 + parameter signed [17:0] t1_re_106 = 17479; // sfix18 + parameter signed [17:0] t1_re_107 = 16703; // sfix18 + parameter signed [17:0] t1_re_108 = 15924; // sfix18 + parameter signed [17:0] t1_re_109 = 15143; // sfix18 + parameter signed [17:0] t1_re_110 = 14359; // sfix18 + parameter signed [17:0] t1_re_111 = 13573; // sfix18 + parameter signed [17:0] t1_re_112 = 12785; // sfix18 + parameter signed [17:0] t1_re_113 = 11996; // sfix18 + parameter signed [17:0] t1_re_114 = 11204; // sfix18 + parameter signed [17:0] t1_re_115 = 10411; // sfix18 + parameter signed [17:0] t1_re_116 = 9616; // sfix18 + parameter signed [17:0] t1_re_117 = 8820; // sfix18 + parameter signed [17:0] t1_re_118 = 8022; // sfix18 + parameter signed [17:0] t1_re_119 = 7224; // sfix18 + parameter signed [17:0] t1_re_120 = 6424; // sfix18 + parameter signed [17:0] t1_re_121 = 5623; // sfix18 + parameter signed [17:0] t1_re_122 = 4821; // sfix18 + parameter signed [17:0] t1_re_123 = 4019; // sfix18 + parameter signed [17:0] t1_re_124 = 3216; // sfix18 + parameter signed [17:0] t1_re_125 = 2412; // sfix18 + parameter signed [17:0] t1_re_126 = 1608; // sfix18 + parameter signed [17:0] t1_re_127 = 804; // sfix18 + parameter signed [17:0] t1_re_128 = 0; // sfix18 + parameter signed [17:0] t1_re_129 = -804; // sfix18 + parameter signed [17:0] t1_re_130 = -1608; // sfix18 + parameter signed [17:0] t1_re_131 = -2412; // sfix18 + parameter signed [17:0] t1_re_132 = -3216; // sfix18 + parameter signed [17:0] t1_re_133 = -4019; // sfix18 + parameter signed [17:0] t1_re_134 = -4821; // sfix18 + parameter signed [17:0] t1_re_135 = -5623; // sfix18 + parameter signed [17:0] t1_re_136 = -6424; // sfix18 + parameter signed [17:0] t1_re_137 = -7224; // sfix18 + parameter signed [17:0] t1_re_138 = -8022; // sfix18 + parameter signed [17:0] t1_re_139 = -8820; // sfix18 + parameter signed [17:0] t1_re_140 = -9616; // sfix18 + parameter signed [17:0] t1_re_141 = -10411; // sfix18 + parameter signed [17:0] t1_re_142 = -11204; // sfix18 + parameter signed [17:0] t1_re_143 = -11996; // sfix18 + parameter signed [17:0] t1_re_144 = -12785; // sfix18 + parameter signed [17:0] t1_re_145 = -13573; // sfix18 + parameter signed [17:0] t1_re_146 = -14359; // sfix18 + parameter signed [17:0] t1_re_147 = -15143; // sfix18 + parameter signed [17:0] t1_re_148 = -15924; // sfix18 + parameter signed [17:0] t1_re_149 = -16703; // sfix18 + parameter signed [17:0] t1_re_150 = -17479; // sfix18 + parameter signed [17:0] t1_re_151 = -18253; // sfix18 + parameter signed [17:0] t1_re_152 = -19024; // sfix18 + parameter signed [17:0] t1_re_153 = -19792; // sfix18 + parameter signed [17:0] t1_re_154 = -20557; // sfix18 + parameter signed [17:0] t1_re_155 = -21320; // sfix18 + parameter signed [17:0] t1_re_156 = -22078; // sfix18 + parameter signed [17:0] t1_re_157 = -22834; // sfix18 + parameter signed [17:0] t1_re_158 = -23586; // sfix18 + parameter signed [17:0] t1_re_159 = -24335; // sfix18 + parameter signed [17:0] t1_re_160 = -25080; // sfix18 + parameter signed [17:0] t1_re_161 = -25821; // sfix18 + parameter signed [17:0] t1_re_162 = -26558; // sfix18 + parameter signed [17:0] t1_re_163 = -27291; // sfix18 + parameter signed [17:0] t1_re_164 = -28020; // sfix18 + parameter signed [17:0] t1_re_165 = -28745; // sfix18 + parameter signed [17:0] t1_re_166 = -29466; // sfix18 + parameter signed [17:0] t1_re_167 = -30182; // sfix18 + parameter signed [17:0] t1_re_168 = -30893; // sfix18 + parameter signed [17:0] t1_re_169 = -31600; // sfix18 + parameter signed [17:0] t1_re_170 = -32303; // sfix18 + parameter signed [17:0] t1_re_171 = -33000; // sfix18 + parameter signed [17:0] t1_re_172 = -33692; // sfix18 + parameter signed [17:0] t1_re_173 = -34380; // sfix18 + parameter signed [17:0] t1_re_174 = -35062; // sfix18 + parameter signed [17:0] t1_re_175 = -35738; // sfix18 + parameter signed [17:0] t1_re_176 = -36410; // sfix18 + parameter signed [17:0] t1_re_177 = -37076; // sfix18 + parameter signed [17:0] t1_re_178 = -37736; // sfix18 + parameter signed [17:0] t1_re_179 = -38391; // sfix18 + parameter signed [17:0] t1_re_180 = -39040; // sfix18 + parameter signed [17:0] t1_re_181 = -39683; // sfix18 + parameter signed [17:0] t1_re_182 = -40320; // sfix18 + parameter signed [17:0] t1_re_183 = -40951; // sfix18 + parameter signed [17:0] t1_re_184 = -41576; // sfix18 + parameter signed [17:0] t1_re_185 = -42194; // sfix18 + parameter signed [17:0] t1_re_186 = -42806; // sfix18 + parameter signed [17:0] t1_re_187 = -43412; // sfix18 + parameter signed [17:0] t1_re_188 = -44011; // sfix18 + parameter signed [17:0] t1_re_189 = -44604; // sfix18 + parameter signed [17:0] t1_re_190 = -45190; // sfix18 + parameter signed [17:0] t1_re_191 = -45769; // sfix18 + parameter signed [17:0] t1_re_192 = -46341; // sfix18 + parameter signed [17:0] t1_re_193 = -46906; // sfix18 + parameter signed [17:0] t1_re_194 = -47464; // sfix18 + parameter signed [17:0] t1_re_195 = -48015; // sfix18 + parameter signed [17:0] t1_re_196 = -48559; // sfix18 + parameter signed [17:0] t1_re_197 = -49095; // sfix18 + parameter signed [17:0] t1_re_198 = -49624; // sfix18 + parameter signed [17:0] t1_re_199 = -50146; // sfix18 + parameter signed [17:0] t1_re_200 = -50660; // sfix18 + parameter signed [17:0] t1_re_201 = -51166; // sfix18 + parameter signed [17:0] t1_re_202 = -51665; // sfix18 + parameter signed [17:0] t1_re_203 = -52156; // sfix18 + parameter signed [17:0] t1_re_204 = -52639; // sfix18 + parameter signed [17:0] t1_re_205 = -53114; // sfix18 + parameter signed [17:0] t1_re_206 = -53581; // sfix18 + parameter signed [17:0] t1_re_207 = -54040; // sfix18 + parameter signed [17:0] t1_re_208 = -54491; // sfix18 + parameter signed [17:0] t1_re_209 = -54934; // sfix18 + parameter signed [17:0] t1_re_210 = -55368; // sfix18 + parameter signed [17:0] t1_re_211 = -55794; // sfix18 + parameter signed [17:0] t1_re_212 = -56212; // sfix18 + parameter signed [17:0] t1_re_213 = -56621; // sfix18 + parameter signed [17:0] t1_re_214 = -57022; // sfix18 + parameter signed [17:0] t1_re_215 = -57414; // sfix18 + parameter signed [17:0] t1_re_216 = -57798; // sfix18 + parameter signed [17:0] t1_re_217 = -58172; // sfix18 + parameter signed [17:0] t1_re_218 = -58538; // sfix18 + parameter signed [17:0] t1_re_219 = -58896; // sfix18 + parameter signed [17:0] t1_re_220 = -59244; // sfix18 + parameter signed [17:0] t1_re_221 = -59583; // sfix18 + parameter signed [17:0] t1_re_222 = -59914; // sfix18 + parameter signed [17:0] t1_re_223 = -60235; // sfix18 + parameter signed [17:0] t1_re_224 = -60547; // sfix18 + parameter signed [17:0] t1_re_225 = -60851; // sfix18 + parameter signed [17:0] t1_re_226 = -61145; // sfix18 + parameter signed [17:0] t1_re_227 = -61429; // sfix18 + parameter signed [17:0] t1_re_228 = -61705; // sfix18 + parameter signed [17:0] t1_re_229 = -61971; // sfix18 + parameter signed [17:0] t1_re_230 = -62228; // sfix18 + parameter signed [17:0] t1_re_231 = -62476; // sfix18 + parameter signed [17:0] t1_re_232 = -62714; // sfix18 + parameter signed [17:0] t1_re_233 = -62943; // sfix18 + parameter signed [17:0] t1_re_234 = -63162; // sfix18 + parameter signed [17:0] t1_re_235 = -63372; // sfix18 + parameter signed [17:0] t1_re_236 = -63572; // sfix18 + parameter signed [17:0] t1_re_237 = -63763; // sfix18 + parameter signed [17:0] t1_re_238 = -63944; // sfix18 + parameter signed [17:0] t1_re_239 = -64115; // sfix18 + parameter signed [17:0] t1_re_240 = -64277; // sfix18 + parameter signed [17:0] t1_re_241 = -64429; // sfix18 + parameter signed [17:0] t1_re_242 = -64571; // sfix18 + parameter signed [17:0] t1_re_243 = -64704; // sfix18 + parameter signed [17:0] t1_re_244 = -64827; // sfix18 + parameter signed [17:0] t1_re_245 = -64940; // sfix18 + parameter signed [17:0] t1_re_246 = -65043; // sfix18 + parameter signed [17:0] t1_re_247 = -65137; // sfix18 + parameter signed [17:0] t1_re_248 = -65220; // sfix18 + parameter signed [17:0] t1_re_249 = -65294; // sfix18 + parameter signed [17:0] t1_re_250 = -65358; // sfix18 + parameter signed [17:0] t1_re_251 = -65413; // sfix18 + parameter signed [17:0] t1_re_252 = -65457; // sfix18 + parameter signed [17:0] t1_re_253 = -65492; // sfix18 + parameter signed [17:0] t1_re_254 = -65516; // sfix18 + parameter signed [17:0] t1_re_255 = -65531; // sfix18 + parameter signed [17:0] t1_re_256 = -65536; // sfix18 + parameter signed [17:0] t1_re_257 = -65531; // sfix18 + parameter signed [17:0] t1_re_258 = -65516; // sfix18 + parameter signed [17:0] t1_re_259 = -65492; // sfix18 + parameter signed [17:0] t1_re_260 = -65457; // sfix18 + parameter signed [17:0] t1_re_261 = -65413; // sfix18 + parameter signed [17:0] t1_re_262 = -65358; // sfix18 + parameter signed [17:0] t1_re_263 = -65294; // sfix18 + parameter signed [17:0] t1_re_264 = -65220; // sfix18 + parameter signed [17:0] t1_re_265 = -65137; // sfix18 + parameter signed [17:0] t1_re_266 = -65043; // sfix18 + parameter signed [17:0] t1_re_267 = -64940; // sfix18 + parameter signed [17:0] t1_re_268 = -64827; // sfix18 + parameter signed [17:0] t1_re_269 = -64704; // sfix18 + parameter signed [17:0] t1_re_270 = -64571; // sfix18 + parameter signed [17:0] t1_re_271 = -64429; // sfix18 + parameter signed [17:0] t1_re_272 = -64277; // sfix18 + parameter signed [17:0] t1_re_273 = -64115; // sfix18 + parameter signed [17:0] t1_re_274 = -63944; // sfix18 + parameter signed [17:0] t1_re_275 = -63763; // sfix18 + parameter signed [17:0] t1_re_276 = -63572; // sfix18 + parameter signed [17:0] t1_re_277 = -63372; // sfix18 + parameter signed [17:0] t1_re_278 = -63162; // sfix18 + parameter signed [17:0] t1_re_279 = -62943; // sfix18 + parameter signed [17:0] t1_re_280 = -62714; // sfix18 + parameter signed [17:0] t1_re_281 = -62476; // sfix18 + parameter signed [17:0] t1_re_282 = -62228; // sfix18 + parameter signed [17:0] t1_re_283 = -61971; // sfix18 + parameter signed [17:0] t1_re_284 = -61705; // sfix18 + parameter signed [17:0] t1_re_285 = -61429; // sfix18 + parameter signed [17:0] t1_re_286 = -61145; // sfix18 + parameter signed [17:0] t1_re_287 = -60851; // sfix18 + parameter signed [17:0] t1_re_288 = -60547; // sfix18 + parameter signed [17:0] t1_re_289 = -60235; // sfix18 + parameter signed [17:0] t1_re_290 = -59914; // sfix18 + parameter signed [17:0] t1_re_291 = -59583; // sfix18 + parameter signed [17:0] t1_re_292 = -59244; // sfix18 + parameter signed [17:0] t1_re_293 = -58896; // sfix18 + parameter signed [17:0] t1_re_294 = -58538; // sfix18 + parameter signed [17:0] t1_re_295 = -58172; // sfix18 + parameter signed [17:0] t1_re_296 = -57798; // sfix18 + parameter signed [17:0] t1_re_297 = -57414; // sfix18 + parameter signed [17:0] t1_re_298 = -57022; // sfix18 + parameter signed [17:0] t1_re_299 = -56621; // sfix18 + parameter signed [17:0] t1_re_300 = -56212; // sfix18 + parameter signed [17:0] t1_re_301 = -55794; // sfix18 + parameter signed [17:0] t1_re_302 = -55368; // sfix18 + parameter signed [17:0] t1_re_303 = -54934; // sfix18 + parameter signed [17:0] t1_re_304 = -54491; // sfix18 + parameter signed [17:0] t1_re_305 = -54040; // sfix18 + parameter signed [17:0] t1_re_306 = -53581; // sfix18 + parameter signed [17:0] t1_re_307 = -53114; // sfix18 + parameter signed [17:0] t1_re_308 = -52639; // sfix18 + parameter signed [17:0] t1_re_309 = -52156; // sfix18 + parameter signed [17:0] t1_re_310 = -51665; // sfix18 + parameter signed [17:0] t1_re_311 = -51166; // sfix18 + parameter signed [17:0] t1_re_312 = -50660; // sfix18 + parameter signed [17:0] t1_re_313 = -50146; // sfix18 + parameter signed [17:0] t1_re_314 = -49624; // sfix18 + parameter signed [17:0] t1_re_315 = -49095; // sfix18 + parameter signed [17:0] t1_re_316 = -48559; // sfix18 + parameter signed [17:0] t1_re_317 = -48015; // sfix18 + parameter signed [17:0] t1_re_318 = -47464; // sfix18 + parameter signed [17:0] t1_re_319 = -46906; // sfix18 + parameter signed [17:0] t1_re_320 = -46341; // sfix18 + parameter signed [17:0] t1_re_321 = -45769; // sfix18 + parameter signed [17:0] t1_re_322 = -45190; // sfix18 + parameter signed [17:0] t1_re_323 = -44604; // sfix18 + parameter signed [17:0] t1_re_324 = -44011; // sfix18 + parameter signed [17:0] t1_re_325 = -43412; // sfix18 + parameter signed [17:0] t1_re_326 = -42806; // sfix18 + parameter signed [17:0] t1_re_327 = -42194; // sfix18 + parameter signed [17:0] t1_re_328 = -41576; // sfix18 + parameter signed [17:0] t1_re_329 = -40951; // sfix18 + parameter signed [17:0] t1_re_330 = -40320; // sfix18 + parameter signed [17:0] t1_re_331 = -39683; // sfix18 + parameter signed [17:0] t1_re_332 = -39040; // sfix18 + parameter signed [17:0] t1_re_333 = -38391; // sfix18 + parameter signed [17:0] t1_re_334 = -37736; // sfix18 + parameter signed [17:0] t1_re_335 = -37076; // sfix18 + parameter signed [17:0] t1_re_336 = -36410; // sfix18 + parameter signed [17:0] t1_re_337 = -35738; // sfix18 + parameter signed [17:0] t1_re_338 = -35062; // sfix18 + parameter signed [17:0] t1_re_339 = -34380; // sfix18 + parameter signed [17:0] t1_re_340 = -33692; // sfix18 + parameter signed [17:0] t1_re_341 = -33000; // sfix18 + parameter signed [17:0] t1_re_342 = -32303; // sfix18 + parameter signed [17:0] t1_re_343 = -31600; // sfix18 + parameter signed [17:0] t1_re_344 = -30893; // sfix18 + parameter signed [17:0] t1_re_345 = -30182; // sfix18 + parameter signed [17:0] t1_re_346 = -29466; // sfix18 + parameter signed [17:0] t1_re_347 = -28745; // sfix18 + parameter signed [17:0] t1_re_348 = -28020; // sfix18 + parameter signed [17:0] t1_re_349 = -27291; // sfix18 + parameter signed [17:0] t1_re_350 = -26558; // sfix18 + parameter signed [17:0] t1_re_351 = -25821; // sfix18 + parameter signed [17:0] t1_re_352 = -25080; // sfix18 + parameter signed [17:0] t1_re_353 = -24335; // sfix18 + parameter signed [17:0] t1_re_354 = -23586; // sfix18 + parameter signed [17:0] t1_re_355 = -22834; // sfix18 + parameter signed [17:0] t1_re_356 = -22078; // sfix18 + parameter signed [17:0] t1_re_357 = -21320; // sfix18 + parameter signed [17:0] t1_re_358 = -20557; // sfix18 + parameter signed [17:0] t1_re_359 = -19792; // sfix18 + parameter signed [17:0] t1_re_360 = -19024; // sfix18 + parameter signed [17:0] t1_re_361 = -18253; // sfix18 + parameter signed [17:0] t1_re_362 = -17479; // sfix18 + parameter signed [17:0] t1_re_363 = -16703; // sfix18 + parameter signed [17:0] t1_re_364 = -15924; // sfix18 + parameter signed [17:0] t1_re_365 = -15143; // sfix18 + parameter signed [17:0] t1_re_366 = -14359; // sfix18 + parameter signed [17:0] t1_re_367 = -13573; // sfix18 + parameter signed [17:0] t1_re_368 = -12785; // sfix18 + parameter signed [17:0] t1_re_369 = -11996; // sfix18 + parameter signed [17:0] t1_re_370 = -11204; // sfix18 + parameter signed [17:0] t1_re_371 = -10411; // sfix18 + parameter signed [17:0] t1_re_372 = -9616; // sfix18 + parameter signed [17:0] t1_re_373 = -8820; // sfix18 + parameter signed [17:0] t1_re_374 = -8022; // sfix18 + parameter signed [17:0] t1_re_375 = -7224; // sfix18 + parameter signed [17:0] t1_re_376 = -6424; // sfix18 + parameter signed [17:0] t1_re_377 = -5623; // sfix18 + parameter signed [17:0] t1_re_378 = -4821; // sfix18 + parameter signed [17:0] t1_re_379 = -4019; // sfix18 + parameter signed [17:0] t1_re_380 = -3216; // sfix18 + parameter signed [17:0] t1_re_381 = -2412; // sfix18 + parameter signed [17:0] t1_re_382 = -1608; // sfix18 + parameter signed [17:0] t1_re_383 = -804; // sfix18 + parameter signed [17:0] t1_re_384 = 0; // sfix18 + parameter signed [17:0] t1_re_385 = 804; // sfix18 + parameter signed [17:0] t1_re_386 = 1608; // sfix18 + parameter signed [17:0] t1_re_387 = 2412; // sfix18 + parameter signed [17:0] t1_re_388 = 3216; // sfix18 + parameter signed [17:0] t1_re_389 = 4019; // sfix18 + parameter signed [17:0] t1_re_390 = 4821; // sfix18 + parameter signed [17:0] t1_re_391 = 5623; // sfix18 + parameter signed [17:0] t1_re_392 = 6424; // sfix18 + parameter signed [17:0] t1_re_393 = 7224; // sfix18 + parameter signed [17:0] t1_re_394 = 8022; // sfix18 + parameter signed [17:0] t1_re_395 = 8820; // sfix18 + parameter signed [17:0] t1_re_396 = 9616; // sfix18 + parameter signed [17:0] t1_re_397 = 10411; // sfix18 + parameter signed [17:0] t1_re_398 = 11204; // sfix18 + parameter signed [17:0] t1_re_399 = 11996; // sfix18 + parameter signed [17:0] t1_re_400 = 12785; // sfix18 + parameter signed [17:0] t1_re_401 = 13573; // sfix18 + parameter signed [17:0] t1_re_402 = 14359; // sfix18 + parameter signed [17:0] t1_re_403 = 15143; // sfix18 + parameter signed [17:0] t1_re_404 = 15924; // sfix18 + parameter signed [17:0] t1_re_405 = 16703; // sfix18 + parameter signed [17:0] t1_re_406 = 17479; // sfix18 + parameter signed [17:0] t1_re_407 = 18253; // sfix18 + parameter signed [17:0] t1_re_408 = 19024; // sfix18 + parameter signed [17:0] t1_re_409 = 19792; // sfix18 + parameter signed [17:0] t1_re_410 = 20557; // sfix18 + parameter signed [17:0] t1_re_411 = 21320; // sfix18 + parameter signed [17:0] t1_re_412 = 22078; // sfix18 + parameter signed [17:0] t1_re_413 = 22834; // sfix18 + parameter signed [17:0] t1_re_414 = 23586; // sfix18 + parameter signed [17:0] t1_re_415 = 24335; // sfix18 + parameter signed [17:0] t1_re_416 = 25080; // sfix18 + parameter signed [17:0] t1_re_417 = 25821; // sfix18 + parameter signed [17:0] t1_re_418 = 26558; // sfix18 + parameter signed [17:0] t1_re_419 = 27291; // sfix18 + parameter signed [17:0] t1_re_420 = 28020; // sfix18 + parameter signed [17:0] t1_re_421 = 28745; // sfix18 + parameter signed [17:0] t1_re_422 = 29466; // sfix18 + parameter signed [17:0] t1_re_423 = 30182; // sfix18 + parameter signed [17:0] t1_re_424 = 30893; // sfix18 + parameter signed [17:0] t1_re_425 = 31600; // sfix18 + parameter signed [17:0] t1_re_426 = 32303; // sfix18 + parameter signed [17:0] t1_re_427 = 33000; // sfix18 + parameter signed [17:0] t1_re_428 = 33692; // sfix18 + parameter signed [17:0] t1_re_429 = 34380; // sfix18 + parameter signed [17:0] t1_re_430 = 35062; // sfix18 + parameter signed [17:0] t1_re_431 = 35738; // sfix18 + parameter signed [17:0] t1_re_432 = 36410; // sfix18 + parameter signed [17:0] t1_re_433 = 37076; // sfix18 + parameter signed [17:0] t1_re_434 = 37736; // sfix18 + parameter signed [17:0] t1_re_435 = 38391; // sfix18 + parameter signed [17:0] t1_re_436 = 39040; // sfix18 + parameter signed [17:0] t1_re_437 = 39683; // sfix18 + parameter signed [17:0] t1_re_438 = 40320; // sfix18 + parameter signed [17:0] t1_re_439 = 40951; // sfix18 + parameter signed [17:0] t1_re_440 = 41576; // sfix18 + parameter signed [17:0] t1_re_441 = 42194; // sfix18 + parameter signed [17:0] t1_re_442 = 42806; // sfix18 + parameter signed [17:0] t1_re_443 = 43412; // sfix18 + parameter signed [17:0] t1_re_444 = 44011; // sfix18 + parameter signed [17:0] t1_re_445 = 44604; // sfix18 + parameter signed [17:0] t1_re_446 = 45190; // sfix18 + parameter signed [17:0] t1_re_447 = 45769; // sfix18 + parameter signed [17:0] t1_re_448 = 46341; // sfix18 + parameter signed [17:0] t1_re_449 = 46906; // sfix18 + parameter signed [17:0] t1_re_450 = 47464; // sfix18 + parameter signed [17:0] t1_re_451 = 48015; // sfix18 + parameter signed [17:0] t1_re_452 = 48559; // sfix18 + parameter signed [17:0] t1_re_453 = 49095; // sfix18 + parameter signed [17:0] t1_re_454 = 49624; // sfix18 + parameter signed [17:0] t1_re_455 = 50146; // sfix18 + parameter signed [17:0] t1_re_456 = 50660; // sfix18 + parameter signed [17:0] t1_re_457 = 51166; // sfix18 + parameter signed [17:0] t1_re_458 = 51665; // sfix18 + parameter signed [17:0] t1_re_459 = 52156; // sfix18 + parameter signed [17:0] t1_re_460 = 52639; // sfix18 + parameter signed [17:0] t1_re_461 = 53114; // sfix18 + parameter signed [17:0] t1_re_462 = 53581; // sfix18 + parameter signed [17:0] t1_re_463 = 54040; // sfix18 + parameter signed [17:0] t1_re_464 = 54491; // sfix18 + parameter signed [17:0] t1_re_465 = 54934; // sfix18 + parameter signed [17:0] t1_re_466 = 55368; // sfix18 + parameter signed [17:0] t1_re_467 = 55794; // sfix18 + parameter signed [17:0] t1_re_468 = 56212; // sfix18 + parameter signed [17:0] t1_re_469 = 56621; // sfix18 + parameter signed [17:0] t1_re_470 = 57022; // sfix18 + parameter signed [17:0] t1_re_471 = 57414; // sfix18 + parameter signed [17:0] t1_re_472 = 57798; // sfix18 + parameter signed [17:0] t1_re_473 = 58172; // sfix18 + parameter signed [17:0] t1_re_474 = 58538; // sfix18 + parameter signed [17:0] t1_re_475 = 58896; // sfix18 + parameter signed [17:0] t1_re_476 = 59244; // sfix18 + parameter signed [17:0] t1_re_477 = 59583; // sfix18 + parameter signed [17:0] t1_re_478 = 59914; // sfix18 + parameter signed [17:0] t1_re_479 = 60235; // sfix18 + parameter signed [17:0] t1_re_480 = 60547; // sfix18 + parameter signed [17:0] t1_re_481 = 60851; // sfix18 + parameter signed [17:0] t1_re_482 = 61145; // sfix18 + parameter signed [17:0] t1_re_483 = 61429; // sfix18 + parameter signed [17:0] t1_re_484 = 61705; // sfix18 + parameter signed [17:0] t1_re_485 = 61971; // sfix18 + parameter signed [17:0] t1_re_486 = 62228; // sfix18 + parameter signed [17:0] t1_re_487 = 62476; // sfix18 + parameter signed [17:0] t1_re_488 = 62714; // sfix18 + parameter signed [17:0] t1_re_489 = 62943; // sfix18 + parameter signed [17:0] t1_re_490 = 63162; // sfix18 + parameter signed [17:0] t1_re_491 = 63372; // sfix18 + parameter signed [17:0] t1_re_492 = 63572; // sfix18 + parameter signed [17:0] t1_re_493 = 63763; // sfix18 + parameter signed [17:0] t1_re_494 = 63944; // sfix18 + parameter signed [17:0] t1_re_495 = 64115; // sfix18 + parameter signed [17:0] t1_re_496 = 64277; // sfix18 + parameter signed [17:0] t1_re_497 = 64429; // sfix18 + parameter signed [17:0] t1_re_498 = 64571; // sfix18 + parameter signed [17:0] t1_re_499 = 64704; // sfix18 + parameter signed [17:0] t1_re_500 = 64827; // sfix18 + parameter signed [17:0] t1_re_501 = 64940; // sfix18 + parameter signed [17:0] t1_re_502 = 65043; // sfix18 + parameter signed [17:0] t1_re_503 = 65137; // sfix18 + parameter signed [17:0] t1_re_504 = 65220; // sfix18 + parameter signed [17:0] t1_re_505 = 65294; // sfix18 + parameter signed [17:0] t1_re_506 = 65358; // sfix18 + parameter signed [17:0] t1_re_507 = 65413; // sfix18 + parameter signed [17:0] t1_re_508 = 65457; // sfix18 + parameter signed [17:0] t1_re_509 = 65492; // sfix18 + parameter signed [17:0] t1_re_510 = 65516; // sfix18 + parameter signed [17:0] t1_re_511 = 65531; // sfix18 + parameter signed [17:0] t1_im_0 = 0; // sfix18 + parameter signed [17:0] t1_im_1 = 804; // sfix18 + parameter signed [17:0] t1_im_2 = 1608; // sfix18 + parameter signed [17:0] t1_im_3 = 2412; // sfix18 + parameter signed [17:0] t1_im_4 = 3216; // sfix18 + parameter signed [17:0] t1_im_5 = 4019; // sfix18 + parameter signed [17:0] t1_im_6 = 4821; // sfix18 + parameter signed [17:0] t1_im_7 = 5623; // sfix18 + parameter signed [17:0] t1_im_8 = 6424; // sfix18 + parameter signed [17:0] t1_im_9 = 7224; // sfix18 + parameter signed [17:0] t1_im_10 = 8022; // sfix18 + parameter signed [17:0] t1_im_11 = 8820; // sfix18 + parameter signed [17:0] t1_im_12 = 9616; // sfix18 + parameter signed [17:0] t1_im_13 = 10411; // sfix18 + parameter signed [17:0] t1_im_14 = 11204; // sfix18 + parameter signed [17:0] t1_im_15 = 11996; // sfix18 + parameter signed [17:0] t1_im_16 = 12785; // sfix18 + parameter signed [17:0] t1_im_17 = 13573; // sfix18 + parameter signed [17:0] t1_im_18 = 14359; // sfix18 + parameter signed [17:0] t1_im_19 = 15143; // sfix18 + parameter signed [17:0] t1_im_20 = 15924; // sfix18 + parameter signed [17:0] t1_im_21 = 16703; // sfix18 + parameter signed [17:0] t1_im_22 = 17479; // sfix18 + parameter signed [17:0] t1_im_23 = 18253; // sfix18 + parameter signed [17:0] t1_im_24 = 19024; // sfix18 + parameter signed [17:0] t1_im_25 = 19792; // sfix18 + parameter signed [17:0] t1_im_26 = 20557; // sfix18 + parameter signed [17:0] t1_im_27 = 21320; // sfix18 + parameter signed [17:0] t1_im_28 = 22078; // sfix18 + parameter signed [17:0] t1_im_29 = 22834; // sfix18 + parameter signed [17:0] t1_im_30 = 23586; // sfix18 + parameter signed [17:0] t1_im_31 = 24335; // sfix18 + parameter signed [17:0] t1_im_32 = 25080; // sfix18 + parameter signed [17:0] t1_im_33 = 25821; // sfix18 + parameter signed [17:0] t1_im_34 = 26558; // sfix18 + parameter signed [17:0] t1_im_35 = 27291; // sfix18 + parameter signed [17:0] t1_im_36 = 28020; // sfix18 + parameter signed [17:0] t1_im_37 = 28745; // sfix18 + parameter signed [17:0] t1_im_38 = 29466; // sfix18 + parameter signed [17:0] t1_im_39 = 30182; // sfix18 + parameter signed [17:0] t1_im_40 = 30893; // sfix18 + parameter signed [17:0] t1_im_41 = 31600; // sfix18 + parameter signed [17:0] t1_im_42 = 32303; // sfix18 + parameter signed [17:0] t1_im_43 = 33000; // sfix18 + parameter signed [17:0] t1_im_44 = 33692; // sfix18 + parameter signed [17:0] t1_im_45 = 34380; // sfix18 + parameter signed [17:0] t1_im_46 = 35062; // sfix18 + parameter signed [17:0] t1_im_47 = 35738; // sfix18 + parameter signed [17:0] t1_im_48 = 36410; // sfix18 + parameter signed [17:0] t1_im_49 = 37076; // sfix18 + parameter signed [17:0] t1_im_50 = 37736; // sfix18 + parameter signed [17:0] t1_im_51 = 38391; // sfix18 + parameter signed [17:0] t1_im_52 = 39040; // sfix18 + parameter signed [17:0] t1_im_53 = 39683; // sfix18 + parameter signed [17:0] t1_im_54 = 40320; // sfix18 + parameter signed [17:0] t1_im_55 = 40951; // sfix18 + parameter signed [17:0] t1_im_56 = 41576; // sfix18 + parameter signed [17:0] t1_im_57 = 42194; // sfix18 + parameter signed [17:0] t1_im_58 = 42806; // sfix18 + parameter signed [17:0] t1_im_59 = 43412; // sfix18 + parameter signed [17:0] t1_im_60 = 44011; // sfix18 + parameter signed [17:0] t1_im_61 = 44604; // sfix18 + parameter signed [17:0] t1_im_62 = 45190; // sfix18 + parameter signed [17:0] t1_im_63 = 45769; // sfix18 + parameter signed [17:0] t1_im_64 = 46341; // sfix18 + parameter signed [17:0] t1_im_65 = 46906; // sfix18 + parameter signed [17:0] t1_im_66 = 47464; // sfix18 + parameter signed [17:0] t1_im_67 = 48015; // sfix18 + parameter signed [17:0] t1_im_68 = 48559; // sfix18 + parameter signed [17:0] t1_im_69 = 49095; // sfix18 + parameter signed [17:0] t1_im_70 = 49624; // sfix18 + parameter signed [17:0] t1_im_71 = 50146; // sfix18 + parameter signed [17:0] t1_im_72 = 50660; // sfix18 + parameter signed [17:0] t1_im_73 = 51166; // sfix18 + parameter signed [17:0] t1_im_74 = 51665; // sfix18 + parameter signed [17:0] t1_im_75 = 52156; // sfix18 + parameter signed [17:0] t1_im_76 = 52639; // sfix18 + parameter signed [17:0] t1_im_77 = 53114; // sfix18 + parameter signed [17:0] t1_im_78 = 53581; // sfix18 + parameter signed [17:0] t1_im_79 = 54040; // sfix18 + parameter signed [17:0] t1_im_80 = 54491; // sfix18 + parameter signed [17:0] t1_im_81 = 54934; // sfix18 + parameter signed [17:0] t1_im_82 = 55368; // sfix18 + parameter signed [17:0] t1_im_83 = 55794; // sfix18 + parameter signed [17:0] t1_im_84 = 56212; // sfix18 + parameter signed [17:0] t1_im_85 = 56621; // sfix18 + parameter signed [17:0] t1_im_86 = 57022; // sfix18 + parameter signed [17:0] t1_im_87 = 57414; // sfix18 + parameter signed [17:0] t1_im_88 = 57798; // sfix18 + parameter signed [17:0] t1_im_89 = 58172; // sfix18 + parameter signed [17:0] t1_im_90 = 58538; // sfix18 + parameter signed [17:0] t1_im_91 = 58896; // sfix18 + parameter signed [17:0] t1_im_92 = 59244; // sfix18 + parameter signed [17:0] t1_im_93 = 59583; // sfix18 + parameter signed [17:0] t1_im_94 = 59914; // sfix18 + parameter signed [17:0] t1_im_95 = 60235; // sfix18 + parameter signed [17:0] t1_im_96 = 60547; // sfix18 + parameter signed [17:0] t1_im_97 = 60851; // sfix18 + parameter signed [17:0] t1_im_98 = 61145; // sfix18 + parameter signed [17:0] t1_im_99 = 61429; // sfix18 + parameter signed [17:0] t1_im_100 = 61705; // sfix18 + parameter signed [17:0] t1_im_101 = 61971; // sfix18 + parameter signed [17:0] t1_im_102 = 62228; // sfix18 + parameter signed [17:0] t1_im_103 = 62476; // sfix18 + parameter signed [17:0] t1_im_104 = 62714; // sfix18 + parameter signed [17:0] t1_im_105 = 62943; // sfix18 + parameter signed [17:0] t1_im_106 = 63162; // sfix18 + parameter signed [17:0] t1_im_107 = 63372; // sfix18 + parameter signed [17:0] t1_im_108 = 63572; // sfix18 + parameter signed [17:0] t1_im_109 = 63763; // sfix18 + parameter signed [17:0] t1_im_110 = 63944; // sfix18 + parameter signed [17:0] t1_im_111 = 64115; // sfix18 + parameter signed [17:0] t1_im_112 = 64277; // sfix18 + parameter signed [17:0] t1_im_113 = 64429; // sfix18 + parameter signed [17:0] t1_im_114 = 64571; // sfix18 + parameter signed [17:0] t1_im_115 = 64704; // sfix18 + parameter signed [17:0] t1_im_116 = 64827; // sfix18 + parameter signed [17:0] t1_im_117 = 64940; // sfix18 + parameter signed [17:0] t1_im_118 = 65043; // sfix18 + parameter signed [17:0] t1_im_119 = 65137; // sfix18 + parameter signed [17:0] t1_im_120 = 65220; // sfix18 + parameter signed [17:0] t1_im_121 = 65294; // sfix18 + parameter signed [17:0] t1_im_122 = 65358; // sfix18 + parameter signed [17:0] t1_im_123 = 65413; // sfix18 + parameter signed [17:0] t1_im_124 = 65457; // sfix18 + parameter signed [17:0] t1_im_125 = 65492; // sfix18 + parameter signed [17:0] t1_im_126 = 65516; // sfix18 + parameter signed [17:0] t1_im_127 = 65531; // sfix18 + parameter signed [17:0] t1_im_128 = 65536; // sfix18 + parameter signed [17:0] t1_im_129 = 65531; // sfix18 + parameter signed [17:0] t1_im_130 = 65516; // sfix18 + parameter signed [17:0] t1_im_131 = 65492; // sfix18 + parameter signed [17:0] t1_im_132 = 65457; // sfix18 + parameter signed [17:0] t1_im_133 = 65413; // sfix18 + parameter signed [17:0] t1_im_134 = 65358; // sfix18 + parameter signed [17:0] t1_im_135 = 65294; // sfix18 + parameter signed [17:0] t1_im_136 = 65220; // sfix18 + parameter signed [17:0] t1_im_137 = 65137; // sfix18 + parameter signed [17:0] t1_im_138 = 65043; // sfix18 + parameter signed [17:0] t1_im_139 = 64940; // sfix18 + parameter signed [17:0] t1_im_140 = 64827; // sfix18 + parameter signed [17:0] t1_im_141 = 64704; // sfix18 + parameter signed [17:0] t1_im_142 = 64571; // sfix18 + parameter signed [17:0] t1_im_143 = 64429; // sfix18 + parameter signed [17:0] t1_im_144 = 64277; // sfix18 + parameter signed [17:0] t1_im_145 = 64115; // sfix18 + parameter signed [17:0] t1_im_146 = 63944; // sfix18 + parameter signed [17:0] t1_im_147 = 63763; // sfix18 + parameter signed [17:0] t1_im_148 = 63572; // sfix18 + parameter signed [17:0] t1_im_149 = 63372; // sfix18 + parameter signed [17:0] t1_im_150 = 63162; // sfix18 + parameter signed [17:0] t1_im_151 = 62943; // sfix18 + parameter signed [17:0] t1_im_152 = 62714; // sfix18 + parameter signed [17:0] t1_im_153 = 62476; // sfix18 + parameter signed [17:0] t1_im_154 = 62228; // sfix18 + parameter signed [17:0] t1_im_155 = 61971; // sfix18 + parameter signed [17:0] t1_im_156 = 61705; // sfix18 + parameter signed [17:0] t1_im_157 = 61429; // sfix18 + parameter signed [17:0] t1_im_158 = 61145; // sfix18 + parameter signed [17:0] t1_im_159 = 60851; // sfix18 + parameter signed [17:0] t1_im_160 = 60547; // sfix18 + parameter signed [17:0] t1_im_161 = 60235; // sfix18 + parameter signed [17:0] t1_im_162 = 59914; // sfix18 + parameter signed [17:0] t1_im_163 = 59583; // sfix18 + parameter signed [17:0] t1_im_164 = 59244; // sfix18 + parameter signed [17:0] t1_im_165 = 58896; // sfix18 + parameter signed [17:0] t1_im_166 = 58538; // sfix18 + parameter signed [17:0] t1_im_167 = 58172; // sfix18 + parameter signed [17:0] t1_im_168 = 57798; // sfix18 + parameter signed [17:0] t1_im_169 = 57414; // sfix18 + parameter signed [17:0] t1_im_170 = 57022; // sfix18 + parameter signed [17:0] t1_im_171 = 56621; // sfix18 + parameter signed [17:0] t1_im_172 = 56212; // sfix18 + parameter signed [17:0] t1_im_173 = 55794; // sfix18 + parameter signed [17:0] t1_im_174 = 55368; // sfix18 + parameter signed [17:0] t1_im_175 = 54934; // sfix18 + parameter signed [17:0] t1_im_176 = 54491; // sfix18 + parameter signed [17:0] t1_im_177 = 54040; // sfix18 + parameter signed [17:0] t1_im_178 = 53581; // sfix18 + parameter signed [17:0] t1_im_179 = 53114; // sfix18 + parameter signed [17:0] t1_im_180 = 52639; // sfix18 + parameter signed [17:0] t1_im_181 = 52156; // sfix18 + parameter signed [17:0] t1_im_182 = 51665; // sfix18 + parameter signed [17:0] t1_im_183 = 51166; // sfix18 + parameter signed [17:0] t1_im_184 = 50660; // sfix18 + parameter signed [17:0] t1_im_185 = 50146; // sfix18 + parameter signed [17:0] t1_im_186 = 49624; // sfix18 + parameter signed [17:0] t1_im_187 = 49095; // sfix18 + parameter signed [17:0] t1_im_188 = 48559; // sfix18 + parameter signed [17:0] t1_im_189 = 48015; // sfix18 + parameter signed [17:0] t1_im_190 = 47464; // sfix18 + parameter signed [17:0] t1_im_191 = 46906; // sfix18 + parameter signed [17:0] t1_im_192 = 46341; // sfix18 + parameter signed [17:0] t1_im_193 = 45769; // sfix18 + parameter signed [17:0] t1_im_194 = 45190; // sfix18 + parameter signed [17:0] t1_im_195 = 44604; // sfix18 + parameter signed [17:0] t1_im_196 = 44011; // sfix18 + parameter signed [17:0] t1_im_197 = 43412; // sfix18 + parameter signed [17:0] t1_im_198 = 42806; // sfix18 + parameter signed [17:0] t1_im_199 = 42194; // sfix18 + parameter signed [17:0] t1_im_200 = 41576; // sfix18 + parameter signed [17:0] t1_im_201 = 40951; // sfix18 + parameter signed [17:0] t1_im_202 = 40320; // sfix18 + parameter signed [17:0] t1_im_203 = 39683; // sfix18 + parameter signed [17:0] t1_im_204 = 39040; // sfix18 + parameter signed [17:0] t1_im_205 = 38391; // sfix18 + parameter signed [17:0] t1_im_206 = 37736; // sfix18 + parameter signed [17:0] t1_im_207 = 37076; // sfix18 + parameter signed [17:0] t1_im_208 = 36410; // sfix18 + parameter signed [17:0] t1_im_209 = 35738; // sfix18 + parameter signed [17:0] t1_im_210 = 35062; // sfix18 + parameter signed [17:0] t1_im_211 = 34380; // sfix18 + parameter signed [17:0] t1_im_212 = 33692; // sfix18 + parameter signed [17:0] t1_im_213 = 33000; // sfix18 + parameter signed [17:0] t1_im_214 = 32303; // sfix18 + parameter signed [17:0] t1_im_215 = 31600; // sfix18 + parameter signed [17:0] t1_im_216 = 30893; // sfix18 + parameter signed [17:0] t1_im_217 = 30182; // sfix18 + parameter signed [17:0] t1_im_218 = 29466; // sfix18 + parameter signed [17:0] t1_im_219 = 28745; // sfix18 + parameter signed [17:0] t1_im_220 = 28020; // sfix18 + parameter signed [17:0] t1_im_221 = 27291; // sfix18 + parameter signed [17:0] t1_im_222 = 26558; // sfix18 + parameter signed [17:0] t1_im_223 = 25821; // sfix18 + parameter signed [17:0] t1_im_224 = 25080; // sfix18 + parameter signed [17:0] t1_im_225 = 24335; // sfix18 + parameter signed [17:0] t1_im_226 = 23586; // sfix18 + parameter signed [17:0] t1_im_227 = 22834; // sfix18 + parameter signed [17:0] t1_im_228 = 22078; // sfix18 + parameter signed [17:0] t1_im_229 = 21320; // sfix18 + parameter signed [17:0] t1_im_230 = 20557; // sfix18 + parameter signed [17:0] t1_im_231 = 19792; // sfix18 + parameter signed [17:0] t1_im_232 = 19024; // sfix18 + parameter signed [17:0] t1_im_233 = 18253; // sfix18 + parameter signed [17:0] t1_im_234 = 17479; // sfix18 + parameter signed [17:0] t1_im_235 = 16703; // sfix18 + parameter signed [17:0] t1_im_236 = 15924; // sfix18 + parameter signed [17:0] t1_im_237 = 15143; // sfix18 + parameter signed [17:0] t1_im_238 = 14359; // sfix18 + parameter signed [17:0] t1_im_239 = 13573; // sfix18 + parameter signed [17:0] t1_im_240 = 12785; // sfix18 + parameter signed [17:0] t1_im_241 = 11996; // sfix18 + parameter signed [17:0] t1_im_242 = 11204; // sfix18 + parameter signed [17:0] t1_im_243 = 10411; // sfix18 + parameter signed [17:0] t1_im_244 = 9616; // sfix18 + parameter signed [17:0] t1_im_245 = 8820; // sfix18 + parameter signed [17:0] t1_im_246 = 8022; // sfix18 + parameter signed [17:0] t1_im_247 = 7224; // sfix18 + parameter signed [17:0] t1_im_248 = 6424; // sfix18 + parameter signed [17:0] t1_im_249 = 5623; // sfix18 + parameter signed [17:0] t1_im_250 = 4821; // sfix18 + parameter signed [17:0] t1_im_251 = 4019; // sfix18 + parameter signed [17:0] t1_im_252 = 3216; // sfix18 + parameter signed [17:0] t1_im_253 = 2412; // sfix18 + parameter signed [17:0] t1_im_254 = 1608; // sfix18 + parameter signed [17:0] t1_im_255 = 804; // sfix18 + parameter signed [17:0] t1_im_256 = 0; // sfix18 + parameter signed [17:0] t1_im_257 = -804; // sfix18 + parameter signed [17:0] t1_im_258 = -1608; // sfix18 + parameter signed [17:0] t1_im_259 = -2412; // sfix18 + parameter signed [17:0] t1_im_260 = -3216; // sfix18 + parameter signed [17:0] t1_im_261 = -4019; // sfix18 + parameter signed [17:0] t1_im_262 = -4821; // sfix18 + parameter signed [17:0] t1_im_263 = -5623; // sfix18 + parameter signed [17:0] t1_im_264 = -6424; // sfix18 + parameter signed [17:0] t1_im_265 = -7224; // sfix18 + parameter signed [17:0] t1_im_266 = -8022; // sfix18 + parameter signed [17:0] t1_im_267 = -8820; // sfix18 + parameter signed [17:0] t1_im_268 = -9616; // sfix18 + parameter signed [17:0] t1_im_269 = -10411; // sfix18 + parameter signed [17:0] t1_im_270 = -11204; // sfix18 + parameter signed [17:0] t1_im_271 = -11996; // sfix18 + parameter signed [17:0] t1_im_272 = -12785; // sfix18 + parameter signed [17:0] t1_im_273 = -13573; // sfix18 + parameter signed [17:0] t1_im_274 = -14359; // sfix18 + parameter signed [17:0] t1_im_275 = -15143; // sfix18 + parameter signed [17:0] t1_im_276 = -15924; // sfix18 + parameter signed [17:0] t1_im_277 = -16703; // sfix18 + parameter signed [17:0] t1_im_278 = -17479; // sfix18 + parameter signed [17:0] t1_im_279 = -18253; // sfix18 + parameter signed [17:0] t1_im_280 = -19024; // sfix18 + parameter signed [17:0] t1_im_281 = -19792; // sfix18 + parameter signed [17:0] t1_im_282 = -20557; // sfix18 + parameter signed [17:0] t1_im_283 = -21320; // sfix18 + parameter signed [17:0] t1_im_284 = -22078; // sfix18 + parameter signed [17:0] t1_im_285 = -22834; // sfix18 + parameter signed [17:0] t1_im_286 = -23586; // sfix18 + parameter signed [17:0] t1_im_287 = -24335; // sfix18 + parameter signed [17:0] t1_im_288 = -25080; // sfix18 + parameter signed [17:0] t1_im_289 = -25821; // sfix18 + parameter signed [17:0] t1_im_290 = -26558; // sfix18 + parameter signed [17:0] t1_im_291 = -27291; // sfix18 + parameter signed [17:0] t1_im_292 = -28020; // sfix18 + parameter signed [17:0] t1_im_293 = -28745; // sfix18 + parameter signed [17:0] t1_im_294 = -29466; // sfix18 + parameter signed [17:0] t1_im_295 = -30182; // sfix18 + parameter signed [17:0] t1_im_296 = -30893; // sfix18 + parameter signed [17:0] t1_im_297 = -31600; // sfix18 + parameter signed [17:0] t1_im_298 = -32303; // sfix18 + parameter signed [17:0] t1_im_299 = -33000; // sfix18 + parameter signed [17:0] t1_im_300 = -33692; // sfix18 + parameter signed [17:0] t1_im_301 = -34380; // sfix18 + parameter signed [17:0] t1_im_302 = -35062; // sfix18 + parameter signed [17:0] t1_im_303 = -35738; // sfix18 + parameter signed [17:0] t1_im_304 = -36410; // sfix18 + parameter signed [17:0] t1_im_305 = -37076; // sfix18 + parameter signed [17:0] t1_im_306 = -37736; // sfix18 + parameter signed [17:0] t1_im_307 = -38391; // sfix18 + parameter signed [17:0] t1_im_308 = -39040; // sfix18 + parameter signed [17:0] t1_im_309 = -39683; // sfix18 + parameter signed [17:0] t1_im_310 = -40320; // sfix18 + parameter signed [17:0] t1_im_311 = -40951; // sfix18 + parameter signed [17:0] t1_im_312 = -41576; // sfix18 + parameter signed [17:0] t1_im_313 = -42194; // sfix18 + parameter signed [17:0] t1_im_314 = -42806; // sfix18 + parameter signed [17:0] t1_im_315 = -43412; // sfix18 + parameter signed [17:0] t1_im_316 = -44011; // sfix18 + parameter signed [17:0] t1_im_317 = -44604; // sfix18 + parameter signed [17:0] t1_im_318 = -45190; // sfix18 + parameter signed [17:0] t1_im_319 = -45769; // sfix18 + parameter signed [17:0] t1_im_320 = -46341; // sfix18 + parameter signed [17:0] t1_im_321 = -46906; // sfix18 + parameter signed [17:0] t1_im_322 = -47464; // sfix18 + parameter signed [17:0] t1_im_323 = -48015; // sfix18 + parameter signed [17:0] t1_im_324 = -48559; // sfix18 + parameter signed [17:0] t1_im_325 = -49095; // sfix18 + parameter signed [17:0] t1_im_326 = -49624; // sfix18 + parameter signed [17:0] t1_im_327 = -50146; // sfix18 + parameter signed [17:0] t1_im_328 = -50660; // sfix18 + parameter signed [17:0] t1_im_329 = -51166; // sfix18 + parameter signed [17:0] t1_im_330 = -51665; // sfix18 + parameter signed [17:0] t1_im_331 = -52156; // sfix18 + parameter signed [17:0] t1_im_332 = -52639; // sfix18 + parameter signed [17:0] t1_im_333 = -53114; // sfix18 + parameter signed [17:0] t1_im_334 = -53581; // sfix18 + parameter signed [17:0] t1_im_335 = -54040; // sfix18 + parameter signed [17:0] t1_im_336 = -54491; // sfix18 + parameter signed [17:0] t1_im_337 = -54934; // sfix18 + parameter signed [17:0] t1_im_338 = -55368; // sfix18 + parameter signed [17:0] t1_im_339 = -55794; // sfix18 + parameter signed [17:0] t1_im_340 = -56212; // sfix18 + parameter signed [17:0] t1_im_341 = -56621; // sfix18 + parameter signed [17:0] t1_im_342 = -57022; // sfix18 + parameter signed [17:0] t1_im_343 = -57414; // sfix18 + parameter signed [17:0] t1_im_344 = -57798; // sfix18 + parameter signed [17:0] t1_im_345 = -58172; // sfix18 + parameter signed [17:0] t1_im_346 = -58538; // sfix18 + parameter signed [17:0] t1_im_347 = -58896; // sfix18 + parameter signed [17:0] t1_im_348 = -59244; // sfix18 + parameter signed [17:0] t1_im_349 = -59583; // sfix18 + parameter signed [17:0] t1_im_350 = -59914; // sfix18 + parameter signed [17:0] t1_im_351 = -60235; // sfix18 + parameter signed [17:0] t1_im_352 = -60547; // sfix18 + parameter signed [17:0] t1_im_353 = -60851; // sfix18 + parameter signed [17:0] t1_im_354 = -61145; // sfix18 + parameter signed [17:0] t1_im_355 = -61429; // sfix18 + parameter signed [17:0] t1_im_356 = -61705; // sfix18 + parameter signed [17:0] t1_im_357 = -61971; // sfix18 + parameter signed [17:0] t1_im_358 = -62228; // sfix18 + parameter signed [17:0] t1_im_359 = -62476; // sfix18 + parameter signed [17:0] t1_im_360 = -62714; // sfix18 + parameter signed [17:0] t1_im_361 = -62943; // sfix18 + parameter signed [17:0] t1_im_362 = -63162; // sfix18 + parameter signed [17:0] t1_im_363 = -63372; // sfix18 + parameter signed [17:0] t1_im_364 = -63572; // sfix18 + parameter signed [17:0] t1_im_365 = -63763; // sfix18 + parameter signed [17:0] t1_im_366 = -63944; // sfix18 + parameter signed [17:0] t1_im_367 = -64115; // sfix18 + parameter signed [17:0] t1_im_368 = -64277; // sfix18 + parameter signed [17:0] t1_im_369 = -64429; // sfix18 + parameter signed [17:0] t1_im_370 = -64571; // sfix18 + parameter signed [17:0] t1_im_371 = -64704; // sfix18 + parameter signed [17:0] t1_im_372 = -64827; // sfix18 + parameter signed [17:0] t1_im_373 = -64940; // sfix18 + parameter signed [17:0] t1_im_374 = -65043; // sfix18 + parameter signed [17:0] t1_im_375 = -65137; // sfix18 + parameter signed [17:0] t1_im_376 = -65220; // sfix18 + parameter signed [17:0] t1_im_377 = -65294; // sfix18 + parameter signed [17:0] t1_im_378 = -65358; // sfix18 + parameter signed [17:0] t1_im_379 = -65413; // sfix18 + parameter signed [17:0] t1_im_380 = -65457; // sfix18 + parameter signed [17:0] t1_im_381 = -65492; // sfix18 + parameter signed [17:0] t1_im_382 = -65516; // sfix18 + parameter signed [17:0] t1_im_383 = -65531; // sfix18 + parameter signed [17:0] t1_im_384 = -65536; // sfix18 + parameter signed [17:0] t1_im_385 = -65531; // sfix18 + parameter signed [17:0] t1_im_386 = -65516; // sfix18 + parameter signed [17:0] t1_im_387 = -65492; // sfix18 + parameter signed [17:0] t1_im_388 = -65457; // sfix18 + parameter signed [17:0] t1_im_389 = -65413; // sfix18 + parameter signed [17:0] t1_im_390 = -65358; // sfix18 + parameter signed [17:0] t1_im_391 = -65294; // sfix18 + parameter signed [17:0] t1_im_392 = -65220; // sfix18 + parameter signed [17:0] t1_im_393 = -65137; // sfix18 + parameter signed [17:0] t1_im_394 = -65043; // sfix18 + parameter signed [17:0] t1_im_395 = -64940; // sfix18 + parameter signed [17:0] t1_im_396 = -64827; // sfix18 + parameter signed [17:0] t1_im_397 = -64704; // sfix18 + parameter signed [17:0] t1_im_398 = -64571; // sfix18 + parameter signed [17:0] t1_im_399 = -64429; // sfix18 + parameter signed [17:0] t1_im_400 = -64277; // sfix18 + parameter signed [17:0] t1_im_401 = -64115; // sfix18 + parameter signed [17:0] t1_im_402 = -63944; // sfix18 + parameter signed [17:0] t1_im_403 = -63763; // sfix18 + parameter signed [17:0] t1_im_404 = -63572; // sfix18 + parameter signed [17:0] t1_im_405 = -63372; // sfix18 + parameter signed [17:0] t1_im_406 = -63162; // sfix18 + parameter signed [17:0] t1_im_407 = -62943; // sfix18 + parameter signed [17:0] t1_im_408 = -62714; // sfix18 + parameter signed [17:0] t1_im_409 = -62476; // sfix18 + parameter signed [17:0] t1_im_410 = -62228; // sfix18 + parameter signed [17:0] t1_im_411 = -61971; // sfix18 + parameter signed [17:0] t1_im_412 = -61705; // sfix18 + parameter signed [17:0] t1_im_413 = -61429; // sfix18 + parameter signed [17:0] t1_im_414 = -61145; // sfix18 + parameter signed [17:0] t1_im_415 = -60851; // sfix18 + parameter signed [17:0] t1_im_416 = -60547; // sfix18 + parameter signed [17:0] t1_im_417 = -60235; // sfix18 + parameter signed [17:0] t1_im_418 = -59914; // sfix18 + parameter signed [17:0] t1_im_419 = -59583; // sfix18 + parameter signed [17:0] t1_im_420 = -59244; // sfix18 + parameter signed [17:0] t1_im_421 = -58896; // sfix18 + parameter signed [17:0] t1_im_422 = -58538; // sfix18 + parameter signed [17:0] t1_im_423 = -58172; // sfix18 + parameter signed [17:0] t1_im_424 = -57798; // sfix18 + parameter signed [17:0] t1_im_425 = -57414; // sfix18 + parameter signed [17:0] t1_im_426 = -57022; // sfix18 + parameter signed [17:0] t1_im_427 = -56621; // sfix18 + parameter signed [17:0] t1_im_428 = -56212; // sfix18 + parameter signed [17:0] t1_im_429 = -55794; // sfix18 + parameter signed [17:0] t1_im_430 = -55368; // sfix18 + parameter signed [17:0] t1_im_431 = -54934; // sfix18 + parameter signed [17:0] t1_im_432 = -54491; // sfix18 + parameter signed [17:0] t1_im_433 = -54040; // sfix18 + parameter signed [17:0] t1_im_434 = -53581; // sfix18 + parameter signed [17:0] t1_im_435 = -53114; // sfix18 + parameter signed [17:0] t1_im_436 = -52639; // sfix18 + parameter signed [17:0] t1_im_437 = -52156; // sfix18 + parameter signed [17:0] t1_im_438 = -51665; // sfix18 + parameter signed [17:0] t1_im_439 = -51166; // sfix18 + parameter signed [17:0] t1_im_440 = -50660; // sfix18 + parameter signed [17:0] t1_im_441 = -50146; // sfix18 + parameter signed [17:0] t1_im_442 = -49624; // sfix18 + parameter signed [17:0] t1_im_443 = -49095; // sfix18 + parameter signed [17:0] t1_im_444 = -48559; // sfix18 + parameter signed [17:0] t1_im_445 = -48015; // sfix18 + parameter signed [17:0] t1_im_446 = -47464; // sfix18 + parameter signed [17:0] t1_im_447 = -46906; // sfix18 + parameter signed [17:0] t1_im_448 = -46341; // sfix18 + parameter signed [17:0] t1_im_449 = -45769; // sfix18 + parameter signed [17:0] t1_im_450 = -45190; // sfix18 + parameter signed [17:0] t1_im_451 = -44604; // sfix18 + parameter signed [17:0] t1_im_452 = -44011; // sfix18 + parameter signed [17:0] t1_im_453 = -43412; // sfix18 + parameter signed [17:0] t1_im_454 = -42806; // sfix18 + parameter signed [17:0] t1_im_455 = -42194; // sfix18 + parameter signed [17:0] t1_im_456 = -41576; // sfix18 + parameter signed [17:0] t1_im_457 = -40951; // sfix18 + parameter signed [17:0] t1_im_458 = -40320; // sfix18 + parameter signed [17:0] t1_im_459 = -39683; // sfix18 + parameter signed [17:0] t1_im_460 = -39040; // sfix18 + parameter signed [17:0] t1_im_461 = -38391; // sfix18 + parameter signed [17:0] t1_im_462 = -37736; // sfix18 + parameter signed [17:0] t1_im_463 = -37076; // sfix18 + parameter signed [17:0] t1_im_464 = -36410; // sfix18 + parameter signed [17:0] t1_im_465 = -35738; // sfix18 + parameter signed [17:0] t1_im_466 = -35062; // sfix18 + parameter signed [17:0] t1_im_467 = -34380; // sfix18 + parameter signed [17:0] t1_im_468 = -33692; // sfix18 + parameter signed [17:0] t1_im_469 = -33000; // sfix18 + parameter signed [17:0] t1_im_470 = -32303; // sfix18 + parameter signed [17:0] t1_im_471 = -31600; // sfix18 + parameter signed [17:0] t1_im_472 = -30893; // sfix18 + parameter signed [17:0] t1_im_473 = -30182; // sfix18 + parameter signed [17:0] t1_im_474 = -29466; // sfix18 + parameter signed [17:0] t1_im_475 = -28745; // sfix18 + parameter signed [17:0] t1_im_476 = -28020; // sfix18 + parameter signed [17:0] t1_im_477 = -27291; // sfix18 + parameter signed [17:0] t1_im_478 = -26558; // sfix18 + parameter signed [17:0] t1_im_479 = -25821; // sfix18 + parameter signed [17:0] t1_im_480 = -25080; // sfix18 + parameter signed [17:0] t1_im_481 = -24335; // sfix18 + parameter signed [17:0] t1_im_482 = -23586; // sfix18 + parameter signed [17:0] t1_im_483 = -22834; // sfix18 + parameter signed [17:0] t1_im_484 = -22078; // sfix18 + parameter signed [17:0] t1_im_485 = -21320; // sfix18 + parameter signed [17:0] t1_im_486 = -20557; // sfix18 + parameter signed [17:0] t1_im_487 = -19792; // sfix18 + parameter signed [17:0] t1_im_488 = -19024; // sfix18 + parameter signed [17:0] t1_im_489 = -18253; // sfix18 + parameter signed [17:0] t1_im_490 = -17479; // sfix18 + parameter signed [17:0] t1_im_491 = -16703; // sfix18 + parameter signed [17:0] t1_im_492 = -15924; // sfix18 + parameter signed [17:0] t1_im_493 = -15143; // sfix18 + parameter signed [17:0] t1_im_494 = -14359; // sfix18 + parameter signed [17:0] t1_im_495 = -13573; // sfix18 + parameter signed [17:0] t1_im_496 = -12785; // sfix18 + parameter signed [17:0] t1_im_497 = -11996; // sfix18 + parameter signed [17:0] t1_im_498 = -11204; // sfix18 + parameter signed [17:0] t1_im_499 = -10411; // sfix18 + parameter signed [17:0] t1_im_500 = -9616; // sfix18 + parameter signed [17:0] t1_im_501 = -8820; // sfix18 + parameter signed [17:0] t1_im_502 = -8022; // sfix18 + parameter signed [17:0] t1_im_503 = -7224; // sfix18 + parameter signed [17:0] t1_im_504 = -6424; // sfix18 + parameter signed [17:0] t1_im_505 = -5623; // sfix18 + parameter signed [17:0] t1_im_506 = -4821; // sfix18 + parameter signed [17:0] t1_im_507 = -4019; // sfix18 + parameter signed [17:0] t1_im_508 = -3216; // sfix18 + parameter signed [17:0] t1_im_509 = -2412; // sfix18 + parameter signed [17:0] t1_im_510 = -1608; // sfix18 + parameter signed [17:0] t1_im_511 = -804; // sfix18 + parameter signed [17:0] t1_re_0_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_1_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_2_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_3_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_4_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_5_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_6_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_7_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_8_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_9_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_10_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_11_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_12_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_13_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_14_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_15_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_16_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_17_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_18_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_19_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_20_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_21_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_22_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_23_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_24_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_25_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_26_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_27_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_28_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_29_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_30_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_31_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_32_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_33_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_34_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_35_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_36_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_37_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_38_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_39_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_40_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_41_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_42_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_43_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_44_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_45_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_46_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_47_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_48_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_49_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_50_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_51_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_52_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_53_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_54_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_55_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_56_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_57_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_58_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_59_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_60_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_61_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_62_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_63_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_64_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_65_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_66_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_67_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_68_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_69_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_70_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_71_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_72_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_73_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_74_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_75_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_76_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_77_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_78_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_79_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_80_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_81_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_82_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_83_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_84_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_85_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_86_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_87_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_88_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_89_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_90_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_91_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_92_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_93_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_94_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_95_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_96_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_97_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_98_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_99_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_100_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_101_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_102_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_103_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_104_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_105_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_106_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_107_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_108_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_109_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_110_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_111_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_112_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_113_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_114_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_115_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_116_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_117_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_118_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_119_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_120_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_121_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_122_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_123_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_124_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_125_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_126_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_127_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_128_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_129_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_130_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_131_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_132_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_133_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_134_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_135_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_136_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_137_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_138_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_139_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_140_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_141_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_142_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_143_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_144_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_145_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_146_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_147_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_148_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_149_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_150_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_151_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_152_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_153_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_154_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_155_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_156_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_157_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_158_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_159_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_160_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_161_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_162_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_163_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_164_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_165_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_166_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_167_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_168_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_169_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_170_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_171_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_172_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_173_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_174_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_175_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_176_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_177_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_178_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_179_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_180_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_181_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_182_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_183_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_184_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_185_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_186_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_187_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_188_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_189_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_190_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_191_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_192_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_193_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_194_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_195_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_196_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_197_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_198_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_199_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_200_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_201_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_202_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_203_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_204_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_205_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_206_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_207_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_208_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_209_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_210_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_211_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_212_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_213_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_214_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_215_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_216_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_217_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_218_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_219_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_220_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_221_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_222_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_223_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_224_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_225_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_226_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_227_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_228_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_229_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_230_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_231_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_232_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_233_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_234_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_235_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_236_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_237_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_238_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_239_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_240_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_241_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_242_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_243_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_244_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_245_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_246_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_247_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_248_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_249_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_250_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_251_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_252_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_253_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_254_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_255_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_256_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_257_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_258_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_259_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_260_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_261_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_262_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_263_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_264_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_265_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_266_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_267_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_268_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_269_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_270_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_271_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_272_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_273_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_274_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_275_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_276_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_277_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_278_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_279_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_280_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_281_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_282_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_283_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_284_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_285_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_286_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_287_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_288_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_289_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_290_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_291_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_292_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_293_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_294_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_295_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_296_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_297_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_298_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_299_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_300_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_301_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_302_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_303_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_304_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_305_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_306_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_307_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_308_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_309_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_310_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_311_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_312_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_313_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_314_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_315_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_316_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_317_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_318_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_319_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_320_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_321_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_322_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_323_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_324_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_325_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_326_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_327_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_328_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_329_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_330_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_331_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_332_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_333_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_334_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_335_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_336_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_337_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_338_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_339_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_340_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_341_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_342_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_343_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_344_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_345_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_346_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_347_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_348_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_349_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_350_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_351_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_352_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_353_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_354_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_355_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_356_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_357_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_358_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_359_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_360_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_361_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_362_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_363_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_364_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_365_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_366_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_367_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_368_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_369_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_370_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_371_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_372_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_373_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_374_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_375_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_376_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_377_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_378_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_379_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_380_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_381_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_382_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_383_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_384_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_385_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_386_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_387_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_388_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_389_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_390_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_391_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_392_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_393_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_394_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_395_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_396_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_397_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_398_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_399_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_400_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_401_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_402_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_403_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_404_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_405_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_406_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_407_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_408_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_409_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_410_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_411_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_412_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_413_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_414_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_415_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_416_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_417_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_418_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_419_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_420_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_421_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_422_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_423_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_424_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_425_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_426_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_427_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_428_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_429_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_430_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_431_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_432_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_433_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_434_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_435_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_436_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_437_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_438_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_439_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_440_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_441_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_442_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_443_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_444_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_445_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_446_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_447_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_448_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_449_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_450_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_451_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_452_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_453_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_454_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_455_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_456_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_457_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_458_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_459_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_460_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_461_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_462_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_463_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_464_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_465_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_466_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_467_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_468_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_469_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_470_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_471_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_472_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_473_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_474_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_475_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_476_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_477_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_478_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_479_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_480_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_481_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_482_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_483_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_484_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_485_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_486_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_487_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_488_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_489_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_490_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_491_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_492_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_493_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_494_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_495_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_496_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_497_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_498_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_499_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_500_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_501_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_502_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_503_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_504_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_505_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_506_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_507_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_508_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_509_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_510_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_511_2 = 65531; // sfix18 + parameter signed [17:0] t1_im_0_2 = 0; // sfix18 + parameter signed [17:0] t1_im_1_2 = 2; // sfix18 + parameter signed [17:0] t1_im_2_2 = 3; // sfix18 + parameter signed [17:0] t1_im_3_2 = 5; // sfix18 + parameter signed [17:0] t1_im_4_2 = 6; // sfix18 + parameter signed [17:0] t1_im_5_2 = 8; // sfix18 + parameter signed [17:0] t1_im_6_2 = 9; // sfix18 + parameter signed [17:0] t1_im_7_2 = 11; // sfix18 + parameter signed [17:0] t1_im_8_2 = 13; // sfix18 + parameter signed [17:0] t1_im_9_2 = 14; // sfix18 + parameter signed [17:0] t1_im_10_2 = 16; // sfix18 + parameter signed [17:0] t1_im_11_2 = 17; // sfix18 + parameter signed [17:0] t1_im_12_2 = 19; // sfix18 + parameter signed [17:0] t1_im_13_2 = 20; // sfix18 + parameter signed [17:0] t1_im_14_2 = 22; // sfix18 + parameter signed [17:0] t1_im_15_2 = 24; // sfix18 + parameter signed [17:0] t1_im_16_2 = 25; // sfix18 + parameter signed [17:0] t1_im_17_2 = 27; // sfix18 + parameter signed [17:0] t1_im_18_2 = 28; // sfix18 + parameter signed [17:0] t1_im_19_2 = 30; // sfix18 + parameter signed [17:0] t1_im_20_2 = 31; // sfix18 + parameter signed [17:0] t1_im_21_2 = 33; // sfix18 + parameter signed [17:0] t1_im_22_2 = 35; // sfix18 + parameter signed [17:0] t1_im_23_2 = 36; // sfix18 + parameter signed [17:0] t1_im_24_2 = 38; // sfix18 + parameter signed [17:0] t1_im_25_2 = 39; // sfix18 + parameter signed [17:0] t1_im_26_2 = 41; // sfix18 + parameter signed [17:0] t1_im_27_2 = 42; // sfix18 + parameter signed [17:0] t1_im_28_2 = 44; // sfix18 + parameter signed [17:0] t1_im_29_2 = 46; // sfix18 + parameter signed [17:0] t1_im_30_2 = 47; // sfix18 + parameter signed [17:0] t1_im_31_2 = 49; // sfix18 + parameter signed [17:0] t1_im_32_2 = 50; // sfix18 + parameter signed [17:0] t1_im_33_2 = 52; // sfix18 + parameter signed [17:0] t1_im_34_2 = 53; // sfix18 + parameter signed [17:0] t1_im_35_2 = 55; // sfix18 + parameter signed [17:0] t1_im_36_2 = 57; // sfix18 + parameter signed [17:0] t1_im_37_2 = 58; // sfix18 + parameter signed [17:0] t1_im_38_2 = 60; // sfix18 + parameter signed [17:0] t1_im_39_2 = 61; // sfix18 + parameter signed [17:0] t1_im_40_2 = 63; // sfix18 + parameter signed [17:0] t1_im_41_2 = 64; // sfix18 + parameter signed [17:0] t1_im_42_2 = 66; // sfix18 + parameter signed [17:0] t1_im_43_2 = 68; // sfix18 + parameter signed [17:0] t1_im_44_2 = 69; // sfix18 + parameter signed [17:0] t1_im_45_2 = 71; // sfix18 + parameter signed [17:0] t1_im_46_2 = 72; // sfix18 + parameter signed [17:0] t1_im_47_2 = 74; // sfix18 + parameter signed [17:0] t1_im_48_2 = 75; // sfix18 + parameter signed [17:0] t1_im_49_2 = 77; // sfix18 + parameter signed [17:0] t1_im_50_2 = 79; // sfix18 + parameter signed [17:0] t1_im_51_2 = 80; // sfix18 + parameter signed [17:0] t1_im_52_2 = 82; // sfix18 + parameter signed [17:0] t1_im_53_2 = 83; // sfix18 + parameter signed [17:0] t1_im_54_2 = 85; // sfix18 + parameter signed [17:0] t1_im_55_2 = 86; // sfix18 + parameter signed [17:0] t1_im_56_2 = 88; // sfix18 + parameter signed [17:0] t1_im_57_2 = 90; // sfix18 + parameter signed [17:0] t1_im_58_2 = 91; // sfix18 + parameter signed [17:0] t1_im_59_2 = 93; // sfix18 + parameter signed [17:0] t1_im_60_2 = 94; // sfix18 + parameter signed [17:0] t1_im_61_2 = 96; // sfix18 + parameter signed [17:0] t1_im_62_2 = 97; // sfix18 + parameter signed [17:0] t1_im_63_2 = 99; // sfix18 + parameter signed [17:0] t1_im_64_2 = 101; // sfix18 + parameter signed [17:0] t1_im_65_2 = 102; // sfix18 + parameter signed [17:0] t1_im_66_2 = 104; // sfix18 + parameter signed [17:0] t1_im_67_2 = 105; // sfix18 + parameter signed [17:0] t1_im_68_2 = 107; // sfix18 + parameter signed [17:0] t1_im_69_2 = 108; // sfix18 + parameter signed [17:0] t1_im_70_2 = 110; // sfix18 + parameter signed [17:0] t1_im_71_2 = 112; // sfix18 + parameter signed [17:0] t1_im_72_2 = 113; // sfix18 + parameter signed [17:0] t1_im_73_2 = 115; // sfix18 + parameter signed [17:0] t1_im_74_2 = 116; // sfix18 + parameter signed [17:0] t1_im_75_2 = 118; // sfix18 + parameter signed [17:0] t1_im_76_2 = 119; // sfix18 + parameter signed [17:0] t1_im_77_2 = 121; // sfix18 + parameter signed [17:0] t1_im_78_2 = 123; // sfix18 + parameter signed [17:0] t1_im_79_2 = 124; // sfix18 + parameter signed [17:0] t1_im_80_2 = 126; // sfix18 + parameter signed [17:0] t1_im_81_2 = 127; // sfix18 + parameter signed [17:0] t1_im_82_2 = 129; // sfix18 + parameter signed [17:0] t1_im_83_2 = 130; // sfix18 + parameter signed [17:0] t1_im_84_2 = 132; // sfix18 + parameter signed [17:0] t1_im_85_2 = 134; // sfix18 + parameter signed [17:0] t1_im_86_2 = 135; // sfix18 + parameter signed [17:0] t1_im_87_2 = 137; // sfix18 + parameter signed [17:0] t1_im_88_2 = 138; // sfix18 + parameter signed [17:0] t1_im_89_2 = 140; // sfix18 + parameter signed [17:0] t1_im_90_2 = 141; // sfix18 + parameter signed [17:0] t1_im_91_2 = 143; // sfix18 + parameter signed [17:0] t1_im_92_2 = 145; // sfix18 + parameter signed [17:0] t1_im_93_2 = 146; // sfix18 + parameter signed [17:0] t1_im_94_2 = 148; // sfix18 + parameter signed [17:0] t1_im_95_2 = 149; // sfix18 + parameter signed [17:0] t1_im_96_2 = 151; // sfix18 + parameter signed [17:0] t1_im_97_2 = 152; // sfix18 + parameter signed [17:0] t1_im_98_2 = 154; // sfix18 + parameter signed [17:0] t1_im_99_2 = 156; // sfix18 + parameter signed [17:0] t1_im_100_2 = 157; // sfix18 + parameter signed [17:0] t1_im_101_2 = 159; // sfix18 + parameter signed [17:0] t1_im_102_2 = 160; // sfix18 + parameter signed [17:0] t1_im_103_2 = 162; // sfix18 + parameter signed [17:0] t1_im_104_2 = 163; // sfix18 + parameter signed [17:0] t1_im_105_2 = 165; // sfix18 + parameter signed [17:0] t1_im_106_2 = 167; // sfix18 + parameter signed [17:0] t1_im_107_2 = 168; // sfix18 + parameter signed [17:0] t1_im_108_2 = 170; // sfix18 + parameter signed [17:0] t1_im_109_2 = 171; // sfix18 + parameter signed [17:0] t1_im_110_2 = 173; // sfix18 + parameter signed [17:0] t1_im_111_2 = 174; // sfix18 + parameter signed [17:0] t1_im_112_2 = 176; // sfix18 + parameter signed [17:0] t1_im_113_2 = 177; // sfix18 + parameter signed [17:0] t1_im_114_2 = 179; // sfix18 + parameter signed [17:0] t1_im_115_2 = 181; // sfix18 + parameter signed [17:0] t1_im_116_2 = 182; // sfix18 + parameter signed [17:0] t1_im_117_2 = 184; // sfix18 + parameter signed [17:0] t1_im_118_2 = 185; // sfix18 + parameter signed [17:0] t1_im_119_2 = 187; // sfix18 + parameter signed [17:0] t1_im_120_2 = 188; // sfix18 + parameter signed [17:0] t1_im_121_2 = 190; // sfix18 + parameter signed [17:0] t1_im_122_2 = 192; // sfix18 + parameter signed [17:0] t1_im_123_2 = 193; // sfix18 + parameter signed [17:0] t1_im_124_2 = 195; // sfix18 + parameter signed [17:0] t1_im_125_2 = 196; // sfix18 + parameter signed [17:0] t1_im_126_2 = 198; // sfix18 + parameter signed [17:0] t1_im_127_2 = 199; // sfix18 + parameter signed [17:0] t1_im_128_2 = 201; // sfix18 + parameter signed [17:0] t1_im_129_2 = 203; // sfix18 + parameter signed [17:0] t1_im_130_2 = 204; // sfix18 + parameter signed [17:0] t1_im_131_2 = 206; // sfix18 + parameter signed [17:0] t1_im_132_2 = 207; // sfix18 + parameter signed [17:0] t1_im_133_2 = 209; // sfix18 + parameter signed [17:0] t1_im_134_2 = 210; // sfix18 + parameter signed [17:0] t1_im_135_2 = 212; // sfix18 + parameter signed [17:0] t1_im_136_2 = 214; // sfix18 + parameter signed [17:0] t1_im_137_2 = 215; // sfix18 + parameter signed [17:0] t1_im_138_2 = 217; // sfix18 + parameter signed [17:0] t1_im_139_2 = 218; // sfix18 + parameter signed [17:0] t1_im_140_2 = 220; // sfix18 + parameter signed [17:0] t1_im_141_2 = 221; // sfix18 + parameter signed [17:0] t1_im_142_2 = 223; // sfix18 + parameter signed [17:0] t1_im_143_2 = 225; // sfix18 + parameter signed [17:0] t1_im_144_2 = 226; // sfix18 + parameter signed [17:0] t1_im_145_2 = 228; // sfix18 + parameter signed [17:0] t1_im_146_2 = 229; // sfix18 + parameter signed [17:0] t1_im_147_2 = 231; // sfix18 + parameter signed [17:0] t1_im_148_2 = 232; // sfix18 + parameter signed [17:0] t1_im_149_2 = 234; // sfix18 + parameter signed [17:0] t1_im_150_2 = 236; // sfix18 + parameter signed [17:0] t1_im_151_2 = 237; // sfix18 + parameter signed [17:0] t1_im_152_2 = 239; // sfix18 + parameter signed [17:0] t1_im_153_2 = 240; // sfix18 + parameter signed [17:0] t1_im_154_2 = 242; // sfix18 + parameter signed [17:0] t1_im_155_2 = 243; // sfix18 + parameter signed [17:0] t1_im_156_2 = 245; // sfix18 + parameter signed [17:0] t1_im_157_2 = 247; // sfix18 + parameter signed [17:0] t1_im_158_2 = 248; // sfix18 + parameter signed [17:0] t1_im_159_2 = 250; // sfix18 + parameter signed [17:0] t1_im_160_2 = 251; // sfix18 + parameter signed [17:0] t1_im_161_2 = 253; // sfix18 + parameter signed [17:0] t1_im_162_2 = 254; // sfix18 + parameter signed [17:0] t1_im_163_2 = 256; // sfix18 + parameter signed [17:0] t1_im_164_2 = 258; // sfix18 + parameter signed [17:0] t1_im_165_2 = 259; // sfix18 + parameter signed [17:0] t1_im_166_2 = 261; // sfix18 + parameter signed [17:0] t1_im_167_2 = 262; // sfix18 + parameter signed [17:0] t1_im_168_2 = 264; // sfix18 + parameter signed [17:0] t1_im_169_2 = 265; // sfix18 + parameter signed [17:0] t1_im_170_2 = 267; // sfix18 + parameter signed [17:0] t1_im_171_2 = 269; // sfix18 + parameter signed [17:0] t1_im_172_2 = 270; // sfix18 + parameter signed [17:0] t1_im_173_2 = 272; // sfix18 + parameter signed [17:0] t1_im_174_2 = 273; // sfix18 + parameter signed [17:0] t1_im_175_2 = 275; // sfix18 + parameter signed [17:0] t1_im_176_2 = 276; // sfix18 + parameter signed [17:0] t1_im_177_2 = 278; // sfix18 + parameter signed [17:0] t1_im_178_2 = 280; // sfix18 + parameter signed [17:0] t1_im_179_2 = 281; // sfix18 + parameter signed [17:0] t1_im_180_2 = 283; // sfix18 + parameter signed [17:0] t1_im_181_2 = 284; // sfix18 + parameter signed [17:0] t1_im_182_2 = 286; // sfix18 + parameter signed [17:0] t1_im_183_2 = 287; // sfix18 + parameter signed [17:0] t1_im_184_2 = 289; // sfix18 + parameter signed [17:0] t1_im_185_2 = 291; // sfix18 + parameter signed [17:0] t1_im_186_2 = 292; // sfix18 + parameter signed [17:0] t1_im_187_2 = 294; // sfix18 + parameter signed [17:0] t1_im_188_2 = 295; // sfix18 + parameter signed [17:0] t1_im_189_2 = 297; // sfix18 + parameter signed [17:0] t1_im_190_2 = 298; // sfix18 + parameter signed [17:0] t1_im_191_2 = 300; // sfix18 + parameter signed [17:0] t1_im_192_2 = 302; // sfix18 + parameter signed [17:0] t1_im_193_2 = 303; // sfix18 + parameter signed [17:0] t1_im_194_2 = 305; // sfix18 + parameter signed [17:0] t1_im_195_2 = 306; // sfix18 + parameter signed [17:0] t1_im_196_2 = 308; // sfix18 + parameter signed [17:0] t1_im_197_2 = 309; // sfix18 + parameter signed [17:0] t1_im_198_2 = 311; // sfix18 + parameter signed [17:0] t1_im_199_2 = 313; // sfix18 + parameter signed [17:0] t1_im_200_2 = 314; // sfix18 + parameter signed [17:0] t1_im_201_2 = 316; // sfix18 + parameter signed [17:0] t1_im_202_2 = 317; // sfix18 + parameter signed [17:0] t1_im_203_2 = 319; // sfix18 + parameter signed [17:0] t1_im_204_2 = 320; // sfix18 + parameter signed [17:0] t1_im_205_2 = 322; // sfix18 + parameter signed [17:0] t1_im_206_2 = 324; // sfix18 + parameter signed [17:0] t1_im_207_2 = 325; // sfix18 + parameter signed [17:0] t1_im_208_2 = 327; // sfix18 + parameter signed [17:0] t1_im_209_2 = 328; // sfix18 + parameter signed [17:0] t1_im_210_2 = 330; // sfix18 + parameter signed [17:0] t1_im_211_2 = 331; // sfix18 + parameter signed [17:0] t1_im_212_2 = 333; // sfix18 + parameter signed [17:0] t1_im_213_2 = 335; // sfix18 + parameter signed [17:0] t1_im_214_2 = 336; // sfix18 + parameter signed [17:0] t1_im_215_2 = 338; // sfix18 + parameter signed [17:0] t1_im_216_2 = 339; // sfix18 + parameter signed [17:0] t1_im_217_2 = 341; // sfix18 + parameter signed [17:0] t1_im_218_2 = 342; // sfix18 + parameter signed [17:0] t1_im_219_2 = 344; // sfix18 + parameter signed [17:0] t1_im_220_2 = 346; // sfix18 + parameter signed [17:0] t1_im_221_2 = 347; // sfix18 + parameter signed [17:0] t1_im_222_2 = 349; // sfix18 + parameter signed [17:0] t1_im_223_2 = 350; // sfix18 + parameter signed [17:0] t1_im_224_2 = 352; // sfix18 + parameter signed [17:0] t1_im_225_2 = 353; // sfix18 + parameter signed [17:0] t1_im_226_2 = 355; // sfix18 + parameter signed [17:0] t1_im_227_2 = 357; // sfix18 + parameter signed [17:0] t1_im_228_2 = 358; // sfix18 + parameter signed [17:0] t1_im_229_2 = 360; // sfix18 + parameter signed [17:0] t1_im_230_2 = 361; // sfix18 + parameter signed [17:0] t1_im_231_2 = 363; // sfix18 + parameter signed [17:0] t1_im_232_2 = 364; // sfix18 + parameter signed [17:0] t1_im_233_2 = 366; // sfix18 + parameter signed [17:0] t1_im_234_2 = 368; // sfix18 + parameter signed [17:0] t1_im_235_2 = 369; // sfix18 + parameter signed [17:0] t1_im_236_2 = 371; // sfix18 + parameter signed [17:0] t1_im_237_2 = 372; // sfix18 + parameter signed [17:0] t1_im_238_2 = 374; // sfix18 + parameter signed [17:0] t1_im_239_2 = 375; // sfix18 + parameter signed [17:0] t1_im_240_2 = 377; // sfix18 + parameter signed [17:0] t1_im_241_2 = 379; // sfix18 + parameter signed [17:0] t1_im_242_2 = 380; // sfix18 + parameter signed [17:0] t1_im_243_2 = 382; // sfix18 + parameter signed [17:0] t1_im_244_2 = 383; // sfix18 + parameter signed [17:0] t1_im_245_2 = 385; // sfix18 + parameter signed [17:0] t1_im_246_2 = 386; // sfix18 + parameter signed [17:0] t1_im_247_2 = 388; // sfix18 + parameter signed [17:0] t1_im_248_2 = 390; // sfix18 + parameter signed [17:0] t1_im_249_2 = 391; // sfix18 + parameter signed [17:0] t1_im_250_2 = 393; // sfix18 + parameter signed [17:0] t1_im_251_2 = 394; // sfix18 + parameter signed [17:0] t1_im_252_2 = 396; // sfix18 + parameter signed [17:0] t1_im_253_2 = 397; // sfix18 + parameter signed [17:0] t1_im_254_2 = 399; // sfix18 + parameter signed [17:0] t1_im_255_2 = 401; // sfix18 + parameter signed [17:0] t1_im_256_2 = 402; // sfix18 + parameter signed [17:0] t1_im_257_2 = 404; // sfix18 + parameter signed [17:0] t1_im_258_2 = 405; // sfix18 + parameter signed [17:0] t1_im_259_2 = 407; // sfix18 + parameter signed [17:0] t1_im_260_2 = 408; // sfix18 + parameter signed [17:0] t1_im_261_2 = 410; // sfix18 + parameter signed [17:0] t1_im_262_2 = 412; // sfix18 + parameter signed [17:0] t1_im_263_2 = 413; // sfix18 + parameter signed [17:0] t1_im_264_2 = 415; // sfix18 + parameter signed [17:0] t1_im_265_2 = 416; // sfix18 + parameter signed [17:0] t1_im_266_2 = 418; // sfix18 + parameter signed [17:0] t1_im_267_2 = 419; // sfix18 + parameter signed [17:0] t1_im_268_2 = 421; // sfix18 + parameter signed [17:0] t1_im_269_2 = 423; // sfix18 + parameter signed [17:0] t1_im_270_2 = 424; // sfix18 + parameter signed [17:0] t1_im_271_2 = 426; // sfix18 + parameter signed [17:0] t1_im_272_2 = 427; // sfix18 + parameter signed [17:0] t1_im_273_2 = 429; // sfix18 + parameter signed [17:0] t1_im_274_2 = 430; // sfix18 + parameter signed [17:0] t1_im_275_2 = 432; // sfix18 + parameter signed [17:0] t1_im_276_2 = 434; // sfix18 + parameter signed [17:0] t1_im_277_2 = 435; // sfix18 + parameter signed [17:0] t1_im_278_2 = 437; // sfix18 + parameter signed [17:0] t1_im_279_2 = 438; // sfix18 + parameter signed [17:0] t1_im_280_2 = 440; // sfix18 + parameter signed [17:0] t1_im_281_2 = 441; // sfix18 + parameter signed [17:0] t1_im_282_2 = 443; // sfix18 + parameter signed [17:0] t1_im_283_2 = 445; // sfix18 + parameter signed [17:0] t1_im_284_2 = 446; // sfix18 + parameter signed [17:0] t1_im_285_2 = 448; // sfix18 + parameter signed [17:0] t1_im_286_2 = 449; // sfix18 + parameter signed [17:0] t1_im_287_2 = 451; // sfix18 + parameter signed [17:0] t1_im_288_2 = 452; // sfix18 + parameter signed [17:0] t1_im_289_2 = 454; // sfix18 + parameter signed [17:0] t1_im_290_2 = 456; // sfix18 + parameter signed [17:0] t1_im_291_2 = 457; // sfix18 + parameter signed [17:0] t1_im_292_2 = 459; // sfix18 + parameter signed [17:0] t1_im_293_2 = 460; // sfix18 + parameter signed [17:0] t1_im_294_2 = 462; // sfix18 + parameter signed [17:0] t1_im_295_2 = 463; // sfix18 + parameter signed [17:0] t1_im_296_2 = 465; // sfix18 + parameter signed [17:0] t1_im_297_2 = 467; // sfix18 + parameter signed [17:0] t1_im_298_2 = 468; // sfix18 + parameter signed [17:0] t1_im_299_2 = 470; // sfix18 + parameter signed [17:0] t1_im_300_2 = 471; // sfix18 + parameter signed [17:0] t1_im_301_2 = 473; // sfix18 + parameter signed [17:0] t1_im_302_2 = 474; // sfix18 + parameter signed [17:0] t1_im_303_2 = 476; // sfix18 + parameter signed [17:0] t1_im_304_2 = 478; // sfix18 + parameter signed [17:0] t1_im_305_2 = 479; // sfix18 + parameter signed [17:0] t1_im_306_2 = 481; // sfix18 + parameter signed [17:0] t1_im_307_2 = 482; // sfix18 + parameter signed [17:0] t1_im_308_2 = 484; // sfix18 + parameter signed [17:0] t1_im_309_2 = 485; // sfix18 + parameter signed [17:0] t1_im_310_2 = 487; // sfix18 + parameter signed [17:0] t1_im_311_2 = 489; // sfix18 + parameter signed [17:0] t1_im_312_2 = 490; // sfix18 + parameter signed [17:0] t1_im_313_2 = 492; // sfix18 + parameter signed [17:0] t1_im_314_2 = 493; // sfix18 + parameter signed [17:0] t1_im_315_2 = 495; // sfix18 + parameter signed [17:0] t1_im_316_2 = 496; // sfix18 + parameter signed [17:0] t1_im_317_2 = 498; // sfix18 + parameter signed [17:0] t1_im_318_2 = 500; // sfix18 + parameter signed [17:0] t1_im_319_2 = 501; // sfix18 + parameter signed [17:0] t1_im_320_2 = 503; // sfix18 + parameter signed [17:0] t1_im_321_2 = 504; // sfix18 + parameter signed [17:0] t1_im_322_2 = 506; // sfix18 + parameter signed [17:0] t1_im_323_2 = 507; // sfix18 + parameter signed [17:0] t1_im_324_2 = 509; // sfix18 + parameter signed [17:0] t1_im_325_2 = 511; // sfix18 + parameter signed [17:0] t1_im_326_2 = 512; // sfix18 + parameter signed [17:0] t1_im_327_2 = 514; // sfix18 + parameter signed [17:0] t1_im_328_2 = 515; // sfix18 + parameter signed [17:0] t1_im_329_2 = 517; // sfix18 + parameter signed [17:0] t1_im_330_2 = 518; // sfix18 + parameter signed [17:0] t1_im_331_2 = 520; // sfix18 + parameter signed [17:0] t1_im_332_2 = 521; // sfix18 + parameter signed [17:0] t1_im_333_2 = 523; // sfix18 + parameter signed [17:0] t1_im_334_2 = 525; // sfix18 + parameter signed [17:0] t1_im_335_2 = 526; // sfix18 + parameter signed [17:0] t1_im_336_2 = 528; // sfix18 + parameter signed [17:0] t1_im_337_2 = 529; // sfix18 + parameter signed [17:0] t1_im_338_2 = 531; // sfix18 + parameter signed [17:0] t1_im_339_2 = 532; // sfix18 + parameter signed [17:0] t1_im_340_2 = 534; // sfix18 + parameter signed [17:0] t1_im_341_2 = 536; // sfix18 + parameter signed [17:0] t1_im_342_2 = 537; // sfix18 + parameter signed [17:0] t1_im_343_2 = 539; // sfix18 + parameter signed [17:0] t1_im_344_2 = 540; // sfix18 + parameter signed [17:0] t1_im_345_2 = 542; // sfix18 + parameter signed [17:0] t1_im_346_2 = 543; // sfix18 + parameter signed [17:0] t1_im_347_2 = 545; // sfix18 + parameter signed [17:0] t1_im_348_2 = 547; // sfix18 + parameter signed [17:0] t1_im_349_2 = 548; // sfix18 + parameter signed [17:0] t1_im_350_2 = 550; // sfix18 + parameter signed [17:0] t1_im_351_2 = 551; // sfix18 + parameter signed [17:0] t1_im_352_2 = 553; // sfix18 + parameter signed [17:0] t1_im_353_2 = 554; // sfix18 + parameter signed [17:0] t1_im_354_2 = 556; // sfix18 + parameter signed [17:0] t1_im_355_2 = 558; // sfix18 + parameter signed [17:0] t1_im_356_2 = 559; // sfix18 + parameter signed [17:0] t1_im_357_2 = 561; // sfix18 + parameter signed [17:0] t1_im_358_2 = 562; // sfix18 + parameter signed [17:0] t1_im_359_2 = 564; // sfix18 + parameter signed [17:0] t1_im_360_2 = 565; // sfix18 + parameter signed [17:0] t1_im_361_2 = 567; // sfix18 + parameter signed [17:0] t1_im_362_2 = 569; // sfix18 + parameter signed [17:0] t1_im_363_2 = 570; // sfix18 + parameter signed [17:0] t1_im_364_2 = 572; // sfix18 + parameter signed [17:0] t1_im_365_2 = 573; // sfix18 + parameter signed [17:0] t1_im_366_2 = 575; // sfix18 + parameter signed [17:0] t1_im_367_2 = 576; // sfix18 + parameter signed [17:0] t1_im_368_2 = 578; // sfix18 + parameter signed [17:0] t1_im_369_2 = 580; // sfix18 + parameter signed [17:0] t1_im_370_2 = 581; // sfix18 + parameter signed [17:0] t1_im_371_2 = 583; // sfix18 + parameter signed [17:0] t1_im_372_2 = 584; // sfix18 + parameter signed [17:0] t1_im_373_2 = 586; // sfix18 + parameter signed [17:0] t1_im_374_2 = 587; // sfix18 + parameter signed [17:0] t1_im_375_2 = 589; // sfix18 + parameter signed [17:0] t1_im_376_2 = 591; // sfix18 + parameter signed [17:0] t1_im_377_2 = 592; // sfix18 + parameter signed [17:0] t1_im_378_2 = 594; // sfix18 + parameter signed [17:0] t1_im_379_2 = 595; // sfix18 + parameter signed [17:0] t1_im_380_2 = 597; // sfix18 + parameter signed [17:0] t1_im_381_2 = 598; // sfix18 + parameter signed [17:0] t1_im_382_2 = 600; // sfix18 + parameter signed [17:0] t1_im_383_2 = 602; // sfix18 + parameter signed [17:0] t1_im_384_2 = 603; // sfix18 + parameter signed [17:0] t1_im_385_2 = 605; // sfix18 + parameter signed [17:0] t1_im_386_2 = 606; // sfix18 + parameter signed [17:0] t1_im_387_2 = 608; // sfix18 + parameter signed [17:0] t1_im_388_2 = 609; // sfix18 + parameter signed [17:0] t1_im_389_2 = 611; // sfix18 + parameter signed [17:0] t1_im_390_2 = 613; // sfix18 + parameter signed [17:0] t1_im_391_2 = 614; // sfix18 + parameter signed [17:0] t1_im_392_2 = 616; // sfix18 + parameter signed [17:0] t1_im_393_2 = 617; // sfix18 + parameter signed [17:0] t1_im_394_2 = 619; // sfix18 + parameter signed [17:0] t1_im_395_2 = 620; // sfix18 + parameter signed [17:0] t1_im_396_2 = 622; // sfix18 + parameter signed [17:0] t1_im_397_2 = 624; // sfix18 + parameter signed [17:0] t1_im_398_2 = 625; // sfix18 + parameter signed [17:0] t1_im_399_2 = 627; // sfix18 + parameter signed [17:0] t1_im_400_2 = 628; // sfix18 + parameter signed [17:0] t1_im_401_2 = 630; // sfix18 + parameter signed [17:0] t1_im_402_2 = 631; // sfix18 + parameter signed [17:0] t1_im_403_2 = 633; // sfix18 + parameter signed [17:0] t1_im_404_2 = 635; // sfix18 + parameter signed [17:0] t1_im_405_2 = 636; // sfix18 + parameter signed [17:0] t1_im_406_2 = 638; // sfix18 + parameter signed [17:0] t1_im_407_2 = 639; // sfix18 + parameter signed [17:0] t1_im_408_2 = 641; // sfix18 + parameter signed [17:0] t1_im_409_2 = 642; // sfix18 + parameter signed [17:0] t1_im_410_2 = 644; // sfix18 + parameter signed [17:0] t1_im_411_2 = 646; // sfix18 + parameter signed [17:0] t1_im_412_2 = 647; // sfix18 + parameter signed [17:0] t1_im_413_2 = 649; // sfix18 + parameter signed [17:0] t1_im_414_2 = 650; // sfix18 + parameter signed [17:0] t1_im_415_2 = 652; // sfix18 + parameter signed [17:0] t1_im_416_2 = 653; // sfix18 + parameter signed [17:0] t1_im_417_2 = 655; // sfix18 + parameter signed [17:0] t1_im_418_2 = 657; // sfix18 + parameter signed [17:0] t1_im_419_2 = 658; // sfix18 + parameter signed [17:0] t1_im_420_2 = 660; // sfix18 + parameter signed [17:0] t1_im_421_2 = 661; // sfix18 + parameter signed [17:0] t1_im_422_2 = 663; // sfix18 + parameter signed [17:0] t1_im_423_2 = 664; // sfix18 + parameter signed [17:0] t1_im_424_2 = 666; // sfix18 + parameter signed [17:0] t1_im_425_2 = 668; // sfix18 + parameter signed [17:0] t1_im_426_2 = 669; // sfix18 + parameter signed [17:0] t1_im_427_2 = 671; // sfix18 + parameter signed [17:0] t1_im_428_2 = 672; // sfix18 + parameter signed [17:0] t1_im_429_2 = 674; // sfix18 + parameter signed [17:0] t1_im_430_2 = 675; // sfix18 + parameter signed [17:0] t1_im_431_2 = 677; // sfix18 + parameter signed [17:0] t1_im_432_2 = 679; // sfix18 + parameter signed [17:0] t1_im_433_2 = 680; // sfix18 + parameter signed [17:0] t1_im_434_2 = 682; // sfix18 + parameter signed [17:0] t1_im_435_2 = 683; // sfix18 + parameter signed [17:0] t1_im_436_2 = 685; // sfix18 + parameter signed [17:0] t1_im_437_2 = 686; // sfix18 + parameter signed [17:0] t1_im_438_2 = 688; // sfix18 + parameter signed [17:0] t1_im_439_2 = 690; // sfix18 + parameter signed [17:0] t1_im_440_2 = 691; // sfix18 + parameter signed [17:0] t1_im_441_2 = 693; // sfix18 + parameter signed [17:0] t1_im_442_2 = 694; // sfix18 + parameter signed [17:0] t1_im_443_2 = 696; // sfix18 + parameter signed [17:0] t1_im_444_2 = 697; // sfix18 + parameter signed [17:0] t1_im_445_2 = 699; // sfix18 + parameter signed [17:0] t1_im_446_2 = 701; // sfix18 + parameter signed [17:0] t1_im_447_2 = 702; // sfix18 + parameter signed [17:0] t1_im_448_2 = 704; // sfix18 + parameter signed [17:0] t1_im_449_2 = 705; // sfix18 + parameter signed [17:0] t1_im_450_2 = 707; // sfix18 + parameter signed [17:0] t1_im_451_2 = 708; // sfix18 + parameter signed [17:0] t1_im_452_2 = 710; // sfix18 + parameter signed [17:0] t1_im_453_2 = 712; // sfix18 + parameter signed [17:0] t1_im_454_2 = 713; // sfix18 + parameter signed [17:0] t1_im_455_2 = 715; // sfix18 + parameter signed [17:0] t1_im_456_2 = 716; // sfix18 + parameter signed [17:0] t1_im_457_2 = 718; // sfix18 + parameter signed [17:0] t1_im_458_2 = 719; // sfix18 + parameter signed [17:0] t1_im_459_2 = 721; // sfix18 + parameter signed [17:0] t1_im_460_2 = 723; // sfix18 + parameter signed [17:0] t1_im_461_2 = 724; // sfix18 + parameter signed [17:0] t1_im_462_2 = 726; // sfix18 + parameter signed [17:0] t1_im_463_2 = 727; // sfix18 + parameter signed [17:0] t1_im_464_2 = 729; // sfix18 + parameter signed [17:0] t1_im_465_2 = 730; // sfix18 + parameter signed [17:0] t1_im_466_2 = 732; // sfix18 + parameter signed [17:0] t1_im_467_2 = 734; // sfix18 + parameter signed [17:0] t1_im_468_2 = 735; // sfix18 + parameter signed [17:0] t1_im_469_2 = 737; // sfix18 + parameter signed [17:0] t1_im_470_2 = 738; // sfix18 + parameter signed [17:0] t1_im_471_2 = 740; // sfix18 + parameter signed [17:0] t1_im_472_2 = 741; // sfix18 + parameter signed [17:0] t1_im_473_2 = 743; // sfix18 + parameter signed [17:0] t1_im_474_2 = 745; // sfix18 + parameter signed [17:0] t1_im_475_2 = 746; // sfix18 + parameter signed [17:0] t1_im_476_2 = 748; // sfix18 + parameter signed [17:0] t1_im_477_2 = 749; // sfix18 + parameter signed [17:0] t1_im_478_2 = 751; // sfix18 + parameter signed [17:0] t1_im_479_2 = 752; // sfix18 + parameter signed [17:0] t1_im_480_2 = 754; // sfix18 + parameter signed [17:0] t1_im_481_2 = 756; // sfix18 + parameter signed [17:0] t1_im_482_2 = 757; // sfix18 + parameter signed [17:0] t1_im_483_2 = 759; // sfix18 + parameter signed [17:0] t1_im_484_2 = 760; // sfix18 + parameter signed [17:0] t1_im_485_2 = 762; // sfix18 + parameter signed [17:0] t1_im_486_2 = 763; // sfix18 + parameter signed [17:0] t1_im_487_2 = 765; // sfix18 + parameter signed [17:0] t1_im_488_2 = 767; // sfix18 + parameter signed [17:0] t1_im_489_2 = 768; // sfix18 + parameter signed [17:0] t1_im_490_2 = 770; // sfix18 + parameter signed [17:0] t1_im_491_2 = 771; // sfix18 + parameter signed [17:0] t1_im_492_2 = 773; // sfix18 + parameter signed [17:0] t1_im_493_2 = 774; // sfix18 + parameter signed [17:0] t1_im_494_2 = 776; // sfix18 + parameter signed [17:0] t1_im_495_2 = 778; // sfix18 + parameter signed [17:0] t1_im_496_2 = 779; // sfix18 + parameter signed [17:0] t1_im_497_2 = 781; // sfix18 + parameter signed [17:0] t1_im_498_2 = 782; // sfix18 + parameter signed [17:0] t1_im_499_2 = 784; // sfix18 + parameter signed [17:0] t1_im_500_2 = 785; // sfix18 + parameter signed [17:0] t1_im_501_2 = 787; // sfix18 + parameter signed [17:0] t1_im_502_2 = 789; // sfix18 + parameter signed [17:0] t1_im_503_2 = 790; // sfix18 + parameter signed [17:0] t1_im_504_2 = 792; // sfix18 + parameter signed [17:0] t1_im_505_2 = 793; // sfix18 + parameter signed [17:0] t1_im_506_2 = 795; // sfix18 + parameter signed [17:0] t1_im_507_2 = 796; // sfix18 + parameter signed [17:0] t1_im_508_2 = 798; // sfix18 + parameter signed [17:0] t1_im_509_2 = 800; // sfix18 + parameter signed [17:0] t1_im_510_2 = 801; // sfix18 + parameter signed [17:0] t1_im_511_2 = 803; // sfix18 + + wire signed [17:0] Convert_Data_Type_out1; // sfix18_En14 + wire signed [35:0] Normalize_Gain_mul_temp; // sfix36_En33 + wire [17:0] Normalize_Gain_out1; // ufix18_En18 + wire [17:0] elec_pos_scaled; // ufix18 + wire [8:0] y; // ufix9 + wire [15:0] Data_Type_Conversion1_out1; // uint16 + wire signed [17:0] Direct_Lookup_Table_n_D_t1_re [0:511]; // sfix18_En16 [512] + wire signed [17:0] Direct_Lookup_Table_n_D_t1_im [0:511]; // sfix18_En16 [512] + wire signed [17:0] Direct_Lookup_Table_n_D_out1_re; // sfix18_En16 + wire signed [17:0] Direct_Lookup_Table_n_D_out1_im; // sfix18_En16 + wire [8:0] y_1; // ufix9 + wire [15:0] Data_Type_Conversion2_out1; // uint16 + wire signed [17:0] Direct_Lookup_Table_n_D_1_t1_re [0:511]; // sfix18_En16 [512] + wire signed [17:0] Direct_Lookup_Table_n_D_1_t1_im [0:511]; // sfix18_En16 [512] + wire signed [17:0] Direct_Lookup_Table_n_D_1_out1_re; // sfix18_En16 + wire signed [17:0] Direct_Lookup_Table_n_D_1_out1_im; // sfix18_En16 + wire signed [35:0] cos_coefficient; // sfix36_En32 + wire signed [35:0] sin_coefficient; // sfix36_En32 + wire signed [17:0] sin_coefficient_1; // sfix18_En16 + wire signed [17:0] cos_coefficient_1; // sfix18_En16 + + // Rotation Coefficients Sin Cos + // + // Calculate sine and cosine of electrical angle using look up table. + + + // /Convert_Data_Type + controllerHdl_Convert_Data_Type_block1 u_Convert_Data_Type (.In1(x), // sfix18_En14 + .Out1(Convert_Data_Type_out1) // sfix18_En14 + ); + + // /Normalize Gain + assign Normalize_Gain_mul_temp = 83443 * Convert_Data_Type_out1; + assign Normalize_Gain_out1 = ((Normalize_Gain_mul_temp[35] == 1'b0) && (Normalize_Gain_mul_temp[34:33] != 2'b00) ? 18'b111111111111111111 : + (Normalize_Gain_mul_temp[35] == 1'b1 ? 18'b000000000000000000 : + Normalize_Gain_mul_temp[32:15])); + + + + // /Remove Scaling + assign elec_pos_scaled = Normalize_Gain_out1; + + + + // /Mark_Extract_Bits + controllerHdl_Mark_Extract_Bits_block u_Mark_Extract_Bits (.In1(elec_pos_scaled), // ufix18 + .Out1(y) // ufix9 + ); + + // /Data Type Conversion1 + assign Data_Type_Conversion1_out1 = y; + + + + // /Direct Lookup Table (n-D) + assign Direct_Lookup_Table_n_D_t1_re[0] = t1_re_0; + assign Direct_Lookup_Table_n_D_t1_re[1] = t1_re_1; + assign Direct_Lookup_Table_n_D_t1_re[2] = t1_re_2; + assign Direct_Lookup_Table_n_D_t1_re[3] = t1_re_3; + assign Direct_Lookup_Table_n_D_t1_re[4] = t1_re_4; + assign Direct_Lookup_Table_n_D_t1_re[5] = t1_re_5; + assign Direct_Lookup_Table_n_D_t1_re[6] = t1_re_6; + assign Direct_Lookup_Table_n_D_t1_re[7] = t1_re_7; + assign Direct_Lookup_Table_n_D_t1_re[8] = t1_re_8; + assign Direct_Lookup_Table_n_D_t1_re[9] = t1_re_9; + assign Direct_Lookup_Table_n_D_t1_re[10] = t1_re_10; + assign Direct_Lookup_Table_n_D_t1_re[11] = t1_re_11; + assign Direct_Lookup_Table_n_D_t1_re[12] = t1_re_12; + assign Direct_Lookup_Table_n_D_t1_re[13] = t1_re_13; + assign Direct_Lookup_Table_n_D_t1_re[14] = t1_re_14; + assign Direct_Lookup_Table_n_D_t1_re[15] = t1_re_15; + assign Direct_Lookup_Table_n_D_t1_re[16] = t1_re_16; + assign Direct_Lookup_Table_n_D_t1_re[17] = t1_re_17; + assign Direct_Lookup_Table_n_D_t1_re[18] = t1_re_18; + assign Direct_Lookup_Table_n_D_t1_re[19] = t1_re_19; + assign Direct_Lookup_Table_n_D_t1_re[20] = t1_re_20; + assign Direct_Lookup_Table_n_D_t1_re[21] = t1_re_21; + assign Direct_Lookup_Table_n_D_t1_re[22] = t1_re_22; + assign Direct_Lookup_Table_n_D_t1_re[23] = t1_re_23; + assign Direct_Lookup_Table_n_D_t1_re[24] = t1_re_24; + assign Direct_Lookup_Table_n_D_t1_re[25] = t1_re_25; + assign Direct_Lookup_Table_n_D_t1_re[26] = t1_re_26; + assign Direct_Lookup_Table_n_D_t1_re[27] = t1_re_27; + assign Direct_Lookup_Table_n_D_t1_re[28] = t1_re_28; + assign Direct_Lookup_Table_n_D_t1_re[29] = t1_re_29; + assign Direct_Lookup_Table_n_D_t1_re[30] = t1_re_30; + assign Direct_Lookup_Table_n_D_t1_re[31] = t1_re_31; + assign Direct_Lookup_Table_n_D_t1_re[32] = t1_re_32; + assign Direct_Lookup_Table_n_D_t1_re[33] = t1_re_33; + assign Direct_Lookup_Table_n_D_t1_re[34] = t1_re_34; + assign Direct_Lookup_Table_n_D_t1_re[35] = t1_re_35; + assign Direct_Lookup_Table_n_D_t1_re[36] = t1_re_36; + assign Direct_Lookup_Table_n_D_t1_re[37] = t1_re_37; + assign Direct_Lookup_Table_n_D_t1_re[38] = t1_re_38; + assign Direct_Lookup_Table_n_D_t1_re[39] = t1_re_39; + assign Direct_Lookup_Table_n_D_t1_re[40] = t1_re_40; + assign Direct_Lookup_Table_n_D_t1_re[41] = t1_re_41; + assign Direct_Lookup_Table_n_D_t1_re[42] = t1_re_42; + assign Direct_Lookup_Table_n_D_t1_re[43] = t1_re_43; + assign Direct_Lookup_Table_n_D_t1_re[44] = t1_re_44; + assign Direct_Lookup_Table_n_D_t1_re[45] = t1_re_45; + assign Direct_Lookup_Table_n_D_t1_re[46] = t1_re_46; + assign Direct_Lookup_Table_n_D_t1_re[47] = t1_re_47; + assign Direct_Lookup_Table_n_D_t1_re[48] = t1_re_48; + assign Direct_Lookup_Table_n_D_t1_re[49] = t1_re_49; + assign Direct_Lookup_Table_n_D_t1_re[50] = t1_re_50; + assign Direct_Lookup_Table_n_D_t1_re[51] = t1_re_51; + assign Direct_Lookup_Table_n_D_t1_re[52] = t1_re_52; + assign Direct_Lookup_Table_n_D_t1_re[53] = t1_re_53; + assign Direct_Lookup_Table_n_D_t1_re[54] = t1_re_54; + assign Direct_Lookup_Table_n_D_t1_re[55] = t1_re_55; + assign Direct_Lookup_Table_n_D_t1_re[56] = t1_re_56; + assign Direct_Lookup_Table_n_D_t1_re[57] = t1_re_57; + assign Direct_Lookup_Table_n_D_t1_re[58] = t1_re_58; + assign Direct_Lookup_Table_n_D_t1_re[59] = t1_re_59; + assign Direct_Lookup_Table_n_D_t1_re[60] = t1_re_60; + assign Direct_Lookup_Table_n_D_t1_re[61] = t1_re_61; + assign Direct_Lookup_Table_n_D_t1_re[62] = t1_re_62; + assign Direct_Lookup_Table_n_D_t1_re[63] = t1_re_63; + assign Direct_Lookup_Table_n_D_t1_re[64] = t1_re_64; + assign Direct_Lookup_Table_n_D_t1_re[65] = t1_re_65; + assign Direct_Lookup_Table_n_D_t1_re[66] = t1_re_66; + assign Direct_Lookup_Table_n_D_t1_re[67] = t1_re_67; + assign Direct_Lookup_Table_n_D_t1_re[68] = t1_re_68; + assign Direct_Lookup_Table_n_D_t1_re[69] = t1_re_69; + assign Direct_Lookup_Table_n_D_t1_re[70] = t1_re_70; + assign Direct_Lookup_Table_n_D_t1_re[71] = t1_re_71; + assign Direct_Lookup_Table_n_D_t1_re[72] = t1_re_72; + assign Direct_Lookup_Table_n_D_t1_re[73] = t1_re_73; + assign Direct_Lookup_Table_n_D_t1_re[74] = t1_re_74; + assign Direct_Lookup_Table_n_D_t1_re[75] = t1_re_75; + assign Direct_Lookup_Table_n_D_t1_re[76] = t1_re_76; + assign Direct_Lookup_Table_n_D_t1_re[77] = t1_re_77; + assign Direct_Lookup_Table_n_D_t1_re[78] = t1_re_78; + assign Direct_Lookup_Table_n_D_t1_re[79] = t1_re_79; + assign Direct_Lookup_Table_n_D_t1_re[80] = t1_re_80; + assign Direct_Lookup_Table_n_D_t1_re[81] = t1_re_81; + assign Direct_Lookup_Table_n_D_t1_re[82] = t1_re_82; + assign Direct_Lookup_Table_n_D_t1_re[83] = t1_re_83; + assign Direct_Lookup_Table_n_D_t1_re[84] = t1_re_84; + assign Direct_Lookup_Table_n_D_t1_re[85] = t1_re_85; + assign Direct_Lookup_Table_n_D_t1_re[86] = t1_re_86; + assign Direct_Lookup_Table_n_D_t1_re[87] = t1_re_87; + assign Direct_Lookup_Table_n_D_t1_re[88] = t1_re_88; + assign Direct_Lookup_Table_n_D_t1_re[89] = t1_re_89; + assign Direct_Lookup_Table_n_D_t1_re[90] = t1_re_90; + assign Direct_Lookup_Table_n_D_t1_re[91] = t1_re_91; + assign Direct_Lookup_Table_n_D_t1_re[92] = t1_re_92; + assign Direct_Lookup_Table_n_D_t1_re[93] = t1_re_93; + assign Direct_Lookup_Table_n_D_t1_re[94] = t1_re_94; + assign Direct_Lookup_Table_n_D_t1_re[95] = t1_re_95; + assign Direct_Lookup_Table_n_D_t1_re[96] = t1_re_96; + assign Direct_Lookup_Table_n_D_t1_re[97] = t1_re_97; + assign Direct_Lookup_Table_n_D_t1_re[98] = t1_re_98; + assign Direct_Lookup_Table_n_D_t1_re[99] = t1_re_99; + assign Direct_Lookup_Table_n_D_t1_re[100] = t1_re_100; + assign Direct_Lookup_Table_n_D_t1_re[101] = t1_re_101; + assign Direct_Lookup_Table_n_D_t1_re[102] = t1_re_102; + assign Direct_Lookup_Table_n_D_t1_re[103] = t1_re_103; + assign Direct_Lookup_Table_n_D_t1_re[104] = t1_re_104; + assign Direct_Lookup_Table_n_D_t1_re[105] = t1_re_105; + assign Direct_Lookup_Table_n_D_t1_re[106] = t1_re_106; + assign Direct_Lookup_Table_n_D_t1_re[107] = t1_re_107; + assign Direct_Lookup_Table_n_D_t1_re[108] = t1_re_108; + assign Direct_Lookup_Table_n_D_t1_re[109] = t1_re_109; + assign Direct_Lookup_Table_n_D_t1_re[110] = t1_re_110; + assign Direct_Lookup_Table_n_D_t1_re[111] = t1_re_111; + assign Direct_Lookup_Table_n_D_t1_re[112] = t1_re_112; + assign Direct_Lookup_Table_n_D_t1_re[113] = t1_re_113; + assign Direct_Lookup_Table_n_D_t1_re[114] = t1_re_114; + assign Direct_Lookup_Table_n_D_t1_re[115] = t1_re_115; + assign Direct_Lookup_Table_n_D_t1_re[116] = t1_re_116; + assign Direct_Lookup_Table_n_D_t1_re[117] = t1_re_117; + assign Direct_Lookup_Table_n_D_t1_re[118] = t1_re_118; + assign Direct_Lookup_Table_n_D_t1_re[119] = t1_re_119; + assign Direct_Lookup_Table_n_D_t1_re[120] = t1_re_120; + assign Direct_Lookup_Table_n_D_t1_re[121] = t1_re_121; + assign Direct_Lookup_Table_n_D_t1_re[122] = t1_re_122; + assign Direct_Lookup_Table_n_D_t1_re[123] = t1_re_123; + assign Direct_Lookup_Table_n_D_t1_re[124] = t1_re_124; + assign Direct_Lookup_Table_n_D_t1_re[125] = t1_re_125; + assign Direct_Lookup_Table_n_D_t1_re[126] = t1_re_126; + assign Direct_Lookup_Table_n_D_t1_re[127] = t1_re_127; + assign Direct_Lookup_Table_n_D_t1_re[128] = t1_re_128; + assign Direct_Lookup_Table_n_D_t1_re[129] = t1_re_129; + assign Direct_Lookup_Table_n_D_t1_re[130] = t1_re_130; + assign Direct_Lookup_Table_n_D_t1_re[131] = t1_re_131; + assign Direct_Lookup_Table_n_D_t1_re[132] = t1_re_132; + assign Direct_Lookup_Table_n_D_t1_re[133] = t1_re_133; + assign Direct_Lookup_Table_n_D_t1_re[134] = t1_re_134; + assign Direct_Lookup_Table_n_D_t1_re[135] = t1_re_135; + assign Direct_Lookup_Table_n_D_t1_re[136] = t1_re_136; + assign Direct_Lookup_Table_n_D_t1_re[137] = t1_re_137; + assign Direct_Lookup_Table_n_D_t1_re[138] = t1_re_138; + assign Direct_Lookup_Table_n_D_t1_re[139] = t1_re_139; + assign Direct_Lookup_Table_n_D_t1_re[140] = t1_re_140; + assign Direct_Lookup_Table_n_D_t1_re[141] = t1_re_141; + assign Direct_Lookup_Table_n_D_t1_re[142] = t1_re_142; + assign Direct_Lookup_Table_n_D_t1_re[143] = t1_re_143; + assign Direct_Lookup_Table_n_D_t1_re[144] = t1_re_144; + assign Direct_Lookup_Table_n_D_t1_re[145] = t1_re_145; + assign Direct_Lookup_Table_n_D_t1_re[146] = t1_re_146; + assign Direct_Lookup_Table_n_D_t1_re[147] = t1_re_147; + assign Direct_Lookup_Table_n_D_t1_re[148] = t1_re_148; + assign Direct_Lookup_Table_n_D_t1_re[149] = t1_re_149; + assign Direct_Lookup_Table_n_D_t1_re[150] = t1_re_150; + assign Direct_Lookup_Table_n_D_t1_re[151] = t1_re_151; + assign Direct_Lookup_Table_n_D_t1_re[152] = t1_re_152; + assign Direct_Lookup_Table_n_D_t1_re[153] = t1_re_153; + assign Direct_Lookup_Table_n_D_t1_re[154] = t1_re_154; + assign Direct_Lookup_Table_n_D_t1_re[155] = t1_re_155; + assign Direct_Lookup_Table_n_D_t1_re[156] = t1_re_156; + assign Direct_Lookup_Table_n_D_t1_re[157] = t1_re_157; + assign Direct_Lookup_Table_n_D_t1_re[158] = t1_re_158; + assign Direct_Lookup_Table_n_D_t1_re[159] = t1_re_159; + assign Direct_Lookup_Table_n_D_t1_re[160] = t1_re_160; + assign Direct_Lookup_Table_n_D_t1_re[161] = t1_re_161; + assign Direct_Lookup_Table_n_D_t1_re[162] = t1_re_162; + assign Direct_Lookup_Table_n_D_t1_re[163] = t1_re_163; + assign Direct_Lookup_Table_n_D_t1_re[164] = t1_re_164; + assign Direct_Lookup_Table_n_D_t1_re[165] = t1_re_165; + assign Direct_Lookup_Table_n_D_t1_re[166] = t1_re_166; + assign Direct_Lookup_Table_n_D_t1_re[167] = t1_re_167; + assign Direct_Lookup_Table_n_D_t1_re[168] = t1_re_168; + assign Direct_Lookup_Table_n_D_t1_re[169] = t1_re_169; + assign Direct_Lookup_Table_n_D_t1_re[170] = t1_re_170; + assign Direct_Lookup_Table_n_D_t1_re[171] = t1_re_171; + assign Direct_Lookup_Table_n_D_t1_re[172] = t1_re_172; + assign Direct_Lookup_Table_n_D_t1_re[173] = t1_re_173; + assign Direct_Lookup_Table_n_D_t1_re[174] = t1_re_174; + assign Direct_Lookup_Table_n_D_t1_re[175] = t1_re_175; + assign Direct_Lookup_Table_n_D_t1_re[176] = t1_re_176; + assign Direct_Lookup_Table_n_D_t1_re[177] = t1_re_177; + assign Direct_Lookup_Table_n_D_t1_re[178] = t1_re_178; + assign Direct_Lookup_Table_n_D_t1_re[179] = t1_re_179; + assign Direct_Lookup_Table_n_D_t1_re[180] = t1_re_180; + assign Direct_Lookup_Table_n_D_t1_re[181] = t1_re_181; + assign Direct_Lookup_Table_n_D_t1_re[182] = t1_re_182; + assign Direct_Lookup_Table_n_D_t1_re[183] = t1_re_183; + assign Direct_Lookup_Table_n_D_t1_re[184] = t1_re_184; + assign Direct_Lookup_Table_n_D_t1_re[185] = t1_re_185; + assign Direct_Lookup_Table_n_D_t1_re[186] = t1_re_186; + assign Direct_Lookup_Table_n_D_t1_re[187] = t1_re_187; + assign Direct_Lookup_Table_n_D_t1_re[188] = t1_re_188; + assign Direct_Lookup_Table_n_D_t1_re[189] = t1_re_189; + assign Direct_Lookup_Table_n_D_t1_re[190] = t1_re_190; + assign Direct_Lookup_Table_n_D_t1_re[191] = t1_re_191; + assign Direct_Lookup_Table_n_D_t1_re[192] = t1_re_192; + assign Direct_Lookup_Table_n_D_t1_re[193] = t1_re_193; + assign Direct_Lookup_Table_n_D_t1_re[194] = t1_re_194; + assign Direct_Lookup_Table_n_D_t1_re[195] = t1_re_195; + assign Direct_Lookup_Table_n_D_t1_re[196] = t1_re_196; + assign Direct_Lookup_Table_n_D_t1_re[197] = t1_re_197; + assign Direct_Lookup_Table_n_D_t1_re[198] = t1_re_198; + assign Direct_Lookup_Table_n_D_t1_re[199] = t1_re_199; + assign Direct_Lookup_Table_n_D_t1_re[200] = t1_re_200; + assign Direct_Lookup_Table_n_D_t1_re[201] = t1_re_201; + assign Direct_Lookup_Table_n_D_t1_re[202] = t1_re_202; + assign Direct_Lookup_Table_n_D_t1_re[203] = t1_re_203; + assign Direct_Lookup_Table_n_D_t1_re[204] = t1_re_204; + assign Direct_Lookup_Table_n_D_t1_re[205] = t1_re_205; + assign Direct_Lookup_Table_n_D_t1_re[206] = t1_re_206; + assign Direct_Lookup_Table_n_D_t1_re[207] = t1_re_207; + assign Direct_Lookup_Table_n_D_t1_re[208] = t1_re_208; + assign Direct_Lookup_Table_n_D_t1_re[209] = t1_re_209; + assign Direct_Lookup_Table_n_D_t1_re[210] = t1_re_210; + assign Direct_Lookup_Table_n_D_t1_re[211] = t1_re_211; + assign Direct_Lookup_Table_n_D_t1_re[212] = t1_re_212; + assign Direct_Lookup_Table_n_D_t1_re[213] = t1_re_213; + assign Direct_Lookup_Table_n_D_t1_re[214] = t1_re_214; + assign Direct_Lookup_Table_n_D_t1_re[215] = t1_re_215; + assign Direct_Lookup_Table_n_D_t1_re[216] = t1_re_216; + assign Direct_Lookup_Table_n_D_t1_re[217] = t1_re_217; + assign Direct_Lookup_Table_n_D_t1_re[218] = t1_re_218; + assign Direct_Lookup_Table_n_D_t1_re[219] = t1_re_219; + assign Direct_Lookup_Table_n_D_t1_re[220] = t1_re_220; + assign Direct_Lookup_Table_n_D_t1_re[221] = t1_re_221; + assign Direct_Lookup_Table_n_D_t1_re[222] = t1_re_222; + assign Direct_Lookup_Table_n_D_t1_re[223] = t1_re_223; + assign Direct_Lookup_Table_n_D_t1_re[224] = t1_re_224; + assign Direct_Lookup_Table_n_D_t1_re[225] = t1_re_225; + assign Direct_Lookup_Table_n_D_t1_re[226] = t1_re_226; + assign Direct_Lookup_Table_n_D_t1_re[227] = t1_re_227; + assign Direct_Lookup_Table_n_D_t1_re[228] = t1_re_228; + assign Direct_Lookup_Table_n_D_t1_re[229] = t1_re_229; + assign Direct_Lookup_Table_n_D_t1_re[230] = t1_re_230; + assign Direct_Lookup_Table_n_D_t1_re[231] = t1_re_231; + assign Direct_Lookup_Table_n_D_t1_re[232] = t1_re_232; + assign Direct_Lookup_Table_n_D_t1_re[233] = t1_re_233; + assign Direct_Lookup_Table_n_D_t1_re[234] = t1_re_234; + assign Direct_Lookup_Table_n_D_t1_re[235] = t1_re_235; + assign Direct_Lookup_Table_n_D_t1_re[236] = t1_re_236; + assign Direct_Lookup_Table_n_D_t1_re[237] = t1_re_237; + assign Direct_Lookup_Table_n_D_t1_re[238] = t1_re_238; + assign Direct_Lookup_Table_n_D_t1_re[239] = t1_re_239; + assign Direct_Lookup_Table_n_D_t1_re[240] = t1_re_240; + assign Direct_Lookup_Table_n_D_t1_re[241] = t1_re_241; + assign Direct_Lookup_Table_n_D_t1_re[242] = t1_re_242; + assign Direct_Lookup_Table_n_D_t1_re[243] = t1_re_243; + assign Direct_Lookup_Table_n_D_t1_re[244] = t1_re_244; + assign Direct_Lookup_Table_n_D_t1_re[245] = t1_re_245; + assign Direct_Lookup_Table_n_D_t1_re[246] = t1_re_246; + assign Direct_Lookup_Table_n_D_t1_re[247] = t1_re_247; + assign Direct_Lookup_Table_n_D_t1_re[248] = t1_re_248; + assign Direct_Lookup_Table_n_D_t1_re[249] = t1_re_249; + assign Direct_Lookup_Table_n_D_t1_re[250] = t1_re_250; + assign Direct_Lookup_Table_n_D_t1_re[251] = t1_re_251; + assign Direct_Lookup_Table_n_D_t1_re[252] = t1_re_252; + assign Direct_Lookup_Table_n_D_t1_re[253] = t1_re_253; + assign Direct_Lookup_Table_n_D_t1_re[254] = t1_re_254; + assign Direct_Lookup_Table_n_D_t1_re[255] = t1_re_255; + assign Direct_Lookup_Table_n_D_t1_re[256] = t1_re_256; + assign Direct_Lookup_Table_n_D_t1_re[257] = t1_re_257; + assign Direct_Lookup_Table_n_D_t1_re[258] = t1_re_258; + assign Direct_Lookup_Table_n_D_t1_re[259] = t1_re_259; + assign Direct_Lookup_Table_n_D_t1_re[260] = t1_re_260; + assign Direct_Lookup_Table_n_D_t1_re[261] = t1_re_261; + assign Direct_Lookup_Table_n_D_t1_re[262] = t1_re_262; + assign Direct_Lookup_Table_n_D_t1_re[263] = t1_re_263; + assign Direct_Lookup_Table_n_D_t1_re[264] = t1_re_264; + assign Direct_Lookup_Table_n_D_t1_re[265] = t1_re_265; + assign Direct_Lookup_Table_n_D_t1_re[266] = t1_re_266; + assign Direct_Lookup_Table_n_D_t1_re[267] = t1_re_267; + assign Direct_Lookup_Table_n_D_t1_re[268] = t1_re_268; + assign Direct_Lookup_Table_n_D_t1_re[269] = t1_re_269; + assign Direct_Lookup_Table_n_D_t1_re[270] = t1_re_270; + assign Direct_Lookup_Table_n_D_t1_re[271] = t1_re_271; + assign Direct_Lookup_Table_n_D_t1_re[272] = t1_re_272; + assign Direct_Lookup_Table_n_D_t1_re[273] = t1_re_273; + assign Direct_Lookup_Table_n_D_t1_re[274] = t1_re_274; + assign Direct_Lookup_Table_n_D_t1_re[275] = t1_re_275; + assign Direct_Lookup_Table_n_D_t1_re[276] = t1_re_276; + assign Direct_Lookup_Table_n_D_t1_re[277] = t1_re_277; + assign Direct_Lookup_Table_n_D_t1_re[278] = t1_re_278; + assign Direct_Lookup_Table_n_D_t1_re[279] = t1_re_279; + assign Direct_Lookup_Table_n_D_t1_re[280] = t1_re_280; + assign Direct_Lookup_Table_n_D_t1_re[281] = t1_re_281; + assign Direct_Lookup_Table_n_D_t1_re[282] = t1_re_282; + assign Direct_Lookup_Table_n_D_t1_re[283] = t1_re_283; + assign Direct_Lookup_Table_n_D_t1_re[284] = t1_re_284; + assign Direct_Lookup_Table_n_D_t1_re[285] = t1_re_285; + assign Direct_Lookup_Table_n_D_t1_re[286] = t1_re_286; + assign Direct_Lookup_Table_n_D_t1_re[287] = t1_re_287; + assign Direct_Lookup_Table_n_D_t1_re[288] = t1_re_288; + assign Direct_Lookup_Table_n_D_t1_re[289] = t1_re_289; + assign Direct_Lookup_Table_n_D_t1_re[290] = t1_re_290; + assign Direct_Lookup_Table_n_D_t1_re[291] = t1_re_291; + assign Direct_Lookup_Table_n_D_t1_re[292] = t1_re_292; + assign Direct_Lookup_Table_n_D_t1_re[293] = t1_re_293; + assign Direct_Lookup_Table_n_D_t1_re[294] = t1_re_294; + assign Direct_Lookup_Table_n_D_t1_re[295] = t1_re_295; + assign Direct_Lookup_Table_n_D_t1_re[296] = t1_re_296; + assign Direct_Lookup_Table_n_D_t1_re[297] = t1_re_297; + assign Direct_Lookup_Table_n_D_t1_re[298] = t1_re_298; + assign Direct_Lookup_Table_n_D_t1_re[299] = t1_re_299; + assign Direct_Lookup_Table_n_D_t1_re[300] = t1_re_300; + assign Direct_Lookup_Table_n_D_t1_re[301] = t1_re_301; + assign Direct_Lookup_Table_n_D_t1_re[302] = t1_re_302; + assign Direct_Lookup_Table_n_D_t1_re[303] = t1_re_303; + assign Direct_Lookup_Table_n_D_t1_re[304] = t1_re_304; + assign Direct_Lookup_Table_n_D_t1_re[305] = t1_re_305; + assign Direct_Lookup_Table_n_D_t1_re[306] = t1_re_306; + assign Direct_Lookup_Table_n_D_t1_re[307] = t1_re_307; + assign Direct_Lookup_Table_n_D_t1_re[308] = t1_re_308; + assign Direct_Lookup_Table_n_D_t1_re[309] = t1_re_309; + assign Direct_Lookup_Table_n_D_t1_re[310] = t1_re_310; + assign Direct_Lookup_Table_n_D_t1_re[311] = t1_re_311; + assign Direct_Lookup_Table_n_D_t1_re[312] = t1_re_312; + assign Direct_Lookup_Table_n_D_t1_re[313] = t1_re_313; + assign Direct_Lookup_Table_n_D_t1_re[314] = t1_re_314; + assign Direct_Lookup_Table_n_D_t1_re[315] = t1_re_315; + assign Direct_Lookup_Table_n_D_t1_re[316] = t1_re_316; + assign Direct_Lookup_Table_n_D_t1_re[317] = t1_re_317; + assign Direct_Lookup_Table_n_D_t1_re[318] = t1_re_318; + assign Direct_Lookup_Table_n_D_t1_re[319] = t1_re_319; + assign Direct_Lookup_Table_n_D_t1_re[320] = t1_re_320; + assign Direct_Lookup_Table_n_D_t1_re[321] = t1_re_321; + assign Direct_Lookup_Table_n_D_t1_re[322] = t1_re_322; + assign Direct_Lookup_Table_n_D_t1_re[323] = t1_re_323; + assign Direct_Lookup_Table_n_D_t1_re[324] = t1_re_324; + assign Direct_Lookup_Table_n_D_t1_re[325] = t1_re_325; + assign Direct_Lookup_Table_n_D_t1_re[326] = t1_re_326; + assign Direct_Lookup_Table_n_D_t1_re[327] = t1_re_327; + assign Direct_Lookup_Table_n_D_t1_re[328] = t1_re_328; + assign Direct_Lookup_Table_n_D_t1_re[329] = t1_re_329; + assign Direct_Lookup_Table_n_D_t1_re[330] = t1_re_330; + assign Direct_Lookup_Table_n_D_t1_re[331] = t1_re_331; + assign Direct_Lookup_Table_n_D_t1_re[332] = t1_re_332; + assign Direct_Lookup_Table_n_D_t1_re[333] = t1_re_333; + assign Direct_Lookup_Table_n_D_t1_re[334] = t1_re_334; + assign Direct_Lookup_Table_n_D_t1_re[335] = t1_re_335; + assign Direct_Lookup_Table_n_D_t1_re[336] = t1_re_336; + assign Direct_Lookup_Table_n_D_t1_re[337] = t1_re_337; + assign Direct_Lookup_Table_n_D_t1_re[338] = t1_re_338; + assign Direct_Lookup_Table_n_D_t1_re[339] = t1_re_339; + assign Direct_Lookup_Table_n_D_t1_re[340] = t1_re_340; + assign Direct_Lookup_Table_n_D_t1_re[341] = t1_re_341; + assign Direct_Lookup_Table_n_D_t1_re[342] = t1_re_342; + assign Direct_Lookup_Table_n_D_t1_re[343] = t1_re_343; + assign Direct_Lookup_Table_n_D_t1_re[344] = t1_re_344; + assign Direct_Lookup_Table_n_D_t1_re[345] = t1_re_345; + assign Direct_Lookup_Table_n_D_t1_re[346] = t1_re_346; + assign Direct_Lookup_Table_n_D_t1_re[347] = t1_re_347; + assign Direct_Lookup_Table_n_D_t1_re[348] = t1_re_348; + assign Direct_Lookup_Table_n_D_t1_re[349] = t1_re_349; + assign Direct_Lookup_Table_n_D_t1_re[350] = t1_re_350; + assign Direct_Lookup_Table_n_D_t1_re[351] = t1_re_351; + assign Direct_Lookup_Table_n_D_t1_re[352] = t1_re_352; + assign Direct_Lookup_Table_n_D_t1_re[353] = t1_re_353; + assign Direct_Lookup_Table_n_D_t1_re[354] = t1_re_354; + assign Direct_Lookup_Table_n_D_t1_re[355] = t1_re_355; + assign Direct_Lookup_Table_n_D_t1_re[356] = t1_re_356; + assign Direct_Lookup_Table_n_D_t1_re[357] = t1_re_357; + assign Direct_Lookup_Table_n_D_t1_re[358] = t1_re_358; + assign Direct_Lookup_Table_n_D_t1_re[359] = t1_re_359; + assign Direct_Lookup_Table_n_D_t1_re[360] = t1_re_360; + assign Direct_Lookup_Table_n_D_t1_re[361] = t1_re_361; + assign Direct_Lookup_Table_n_D_t1_re[362] = t1_re_362; + assign Direct_Lookup_Table_n_D_t1_re[363] = t1_re_363; + assign Direct_Lookup_Table_n_D_t1_re[364] = t1_re_364; + assign Direct_Lookup_Table_n_D_t1_re[365] = t1_re_365; + assign Direct_Lookup_Table_n_D_t1_re[366] = t1_re_366; + assign Direct_Lookup_Table_n_D_t1_re[367] = t1_re_367; + assign Direct_Lookup_Table_n_D_t1_re[368] = t1_re_368; + assign Direct_Lookup_Table_n_D_t1_re[369] = t1_re_369; + assign Direct_Lookup_Table_n_D_t1_re[370] = t1_re_370; + assign Direct_Lookup_Table_n_D_t1_re[371] = t1_re_371; + assign Direct_Lookup_Table_n_D_t1_re[372] = t1_re_372; + assign Direct_Lookup_Table_n_D_t1_re[373] = t1_re_373; + assign Direct_Lookup_Table_n_D_t1_re[374] = t1_re_374; + assign Direct_Lookup_Table_n_D_t1_re[375] = t1_re_375; + assign Direct_Lookup_Table_n_D_t1_re[376] = t1_re_376; + assign Direct_Lookup_Table_n_D_t1_re[377] = t1_re_377; + assign Direct_Lookup_Table_n_D_t1_re[378] = t1_re_378; + assign Direct_Lookup_Table_n_D_t1_re[379] = t1_re_379; + assign Direct_Lookup_Table_n_D_t1_re[380] = t1_re_380; + assign Direct_Lookup_Table_n_D_t1_re[381] = t1_re_381; + assign Direct_Lookup_Table_n_D_t1_re[382] = t1_re_382; + assign Direct_Lookup_Table_n_D_t1_re[383] = t1_re_383; + assign Direct_Lookup_Table_n_D_t1_re[384] = t1_re_384; + assign Direct_Lookup_Table_n_D_t1_re[385] = t1_re_385; + assign Direct_Lookup_Table_n_D_t1_re[386] = t1_re_386; + assign Direct_Lookup_Table_n_D_t1_re[387] = t1_re_387; + assign Direct_Lookup_Table_n_D_t1_re[388] = t1_re_388; + assign Direct_Lookup_Table_n_D_t1_re[389] = t1_re_389; + assign Direct_Lookup_Table_n_D_t1_re[390] = t1_re_390; + assign Direct_Lookup_Table_n_D_t1_re[391] = t1_re_391; + assign Direct_Lookup_Table_n_D_t1_re[392] = t1_re_392; + assign Direct_Lookup_Table_n_D_t1_re[393] = t1_re_393; + assign Direct_Lookup_Table_n_D_t1_re[394] = t1_re_394; + assign Direct_Lookup_Table_n_D_t1_re[395] = t1_re_395; + assign Direct_Lookup_Table_n_D_t1_re[396] = t1_re_396; + assign Direct_Lookup_Table_n_D_t1_re[397] = t1_re_397; + assign Direct_Lookup_Table_n_D_t1_re[398] = t1_re_398; + assign Direct_Lookup_Table_n_D_t1_re[399] = t1_re_399; + assign Direct_Lookup_Table_n_D_t1_re[400] = t1_re_400; + assign Direct_Lookup_Table_n_D_t1_re[401] = t1_re_401; + assign Direct_Lookup_Table_n_D_t1_re[402] = t1_re_402; + assign Direct_Lookup_Table_n_D_t1_re[403] = t1_re_403; + assign Direct_Lookup_Table_n_D_t1_re[404] = t1_re_404; + assign Direct_Lookup_Table_n_D_t1_re[405] = t1_re_405; + assign Direct_Lookup_Table_n_D_t1_re[406] = t1_re_406; + assign Direct_Lookup_Table_n_D_t1_re[407] = t1_re_407; + assign Direct_Lookup_Table_n_D_t1_re[408] = t1_re_408; + assign Direct_Lookup_Table_n_D_t1_re[409] = t1_re_409; + assign Direct_Lookup_Table_n_D_t1_re[410] = t1_re_410; + assign Direct_Lookup_Table_n_D_t1_re[411] = t1_re_411; + assign Direct_Lookup_Table_n_D_t1_re[412] = t1_re_412; + assign Direct_Lookup_Table_n_D_t1_re[413] = t1_re_413; + assign Direct_Lookup_Table_n_D_t1_re[414] = t1_re_414; + assign Direct_Lookup_Table_n_D_t1_re[415] = t1_re_415; + assign Direct_Lookup_Table_n_D_t1_re[416] = t1_re_416; + assign Direct_Lookup_Table_n_D_t1_re[417] = t1_re_417; + assign Direct_Lookup_Table_n_D_t1_re[418] = t1_re_418; + assign Direct_Lookup_Table_n_D_t1_re[419] = t1_re_419; + assign Direct_Lookup_Table_n_D_t1_re[420] = t1_re_420; + assign Direct_Lookup_Table_n_D_t1_re[421] = t1_re_421; + assign Direct_Lookup_Table_n_D_t1_re[422] = t1_re_422; + assign Direct_Lookup_Table_n_D_t1_re[423] = t1_re_423; + assign Direct_Lookup_Table_n_D_t1_re[424] = t1_re_424; + assign Direct_Lookup_Table_n_D_t1_re[425] = t1_re_425; + assign Direct_Lookup_Table_n_D_t1_re[426] = t1_re_426; + assign Direct_Lookup_Table_n_D_t1_re[427] = t1_re_427; + assign Direct_Lookup_Table_n_D_t1_re[428] = t1_re_428; + assign Direct_Lookup_Table_n_D_t1_re[429] = t1_re_429; + assign Direct_Lookup_Table_n_D_t1_re[430] = t1_re_430; + assign Direct_Lookup_Table_n_D_t1_re[431] = t1_re_431; + assign Direct_Lookup_Table_n_D_t1_re[432] = t1_re_432; + assign Direct_Lookup_Table_n_D_t1_re[433] = t1_re_433; + assign Direct_Lookup_Table_n_D_t1_re[434] = t1_re_434; + assign Direct_Lookup_Table_n_D_t1_re[435] = t1_re_435; + assign Direct_Lookup_Table_n_D_t1_re[436] = t1_re_436; + assign Direct_Lookup_Table_n_D_t1_re[437] = t1_re_437; + assign Direct_Lookup_Table_n_D_t1_re[438] = t1_re_438; + assign Direct_Lookup_Table_n_D_t1_re[439] = t1_re_439; + assign Direct_Lookup_Table_n_D_t1_re[440] = t1_re_440; + assign Direct_Lookup_Table_n_D_t1_re[441] = t1_re_441; + assign Direct_Lookup_Table_n_D_t1_re[442] = t1_re_442; + assign Direct_Lookup_Table_n_D_t1_re[443] = t1_re_443; + assign Direct_Lookup_Table_n_D_t1_re[444] = t1_re_444; + assign Direct_Lookup_Table_n_D_t1_re[445] = t1_re_445; + assign Direct_Lookup_Table_n_D_t1_re[446] = t1_re_446; + assign Direct_Lookup_Table_n_D_t1_re[447] = t1_re_447; + assign Direct_Lookup_Table_n_D_t1_re[448] = t1_re_448; + assign Direct_Lookup_Table_n_D_t1_re[449] = t1_re_449; + assign Direct_Lookup_Table_n_D_t1_re[450] = t1_re_450; + assign Direct_Lookup_Table_n_D_t1_re[451] = t1_re_451; + assign Direct_Lookup_Table_n_D_t1_re[452] = t1_re_452; + assign Direct_Lookup_Table_n_D_t1_re[453] = t1_re_453; + assign Direct_Lookup_Table_n_D_t1_re[454] = t1_re_454; + assign Direct_Lookup_Table_n_D_t1_re[455] = t1_re_455; + assign Direct_Lookup_Table_n_D_t1_re[456] = t1_re_456; + assign Direct_Lookup_Table_n_D_t1_re[457] = t1_re_457; + assign Direct_Lookup_Table_n_D_t1_re[458] = t1_re_458; + assign Direct_Lookup_Table_n_D_t1_re[459] = t1_re_459; + assign Direct_Lookup_Table_n_D_t1_re[460] = t1_re_460; + assign Direct_Lookup_Table_n_D_t1_re[461] = t1_re_461; + assign Direct_Lookup_Table_n_D_t1_re[462] = t1_re_462; + assign Direct_Lookup_Table_n_D_t1_re[463] = t1_re_463; + assign Direct_Lookup_Table_n_D_t1_re[464] = t1_re_464; + assign Direct_Lookup_Table_n_D_t1_re[465] = t1_re_465; + assign Direct_Lookup_Table_n_D_t1_re[466] = t1_re_466; + assign Direct_Lookup_Table_n_D_t1_re[467] = t1_re_467; + assign Direct_Lookup_Table_n_D_t1_re[468] = t1_re_468; + assign Direct_Lookup_Table_n_D_t1_re[469] = t1_re_469; + assign Direct_Lookup_Table_n_D_t1_re[470] = t1_re_470; + assign Direct_Lookup_Table_n_D_t1_re[471] = t1_re_471; + assign Direct_Lookup_Table_n_D_t1_re[472] = t1_re_472; + assign Direct_Lookup_Table_n_D_t1_re[473] = t1_re_473; + assign Direct_Lookup_Table_n_D_t1_re[474] = t1_re_474; + assign Direct_Lookup_Table_n_D_t1_re[475] = t1_re_475; + assign Direct_Lookup_Table_n_D_t1_re[476] = t1_re_476; + assign Direct_Lookup_Table_n_D_t1_re[477] = t1_re_477; + assign Direct_Lookup_Table_n_D_t1_re[478] = t1_re_478; + assign Direct_Lookup_Table_n_D_t1_re[479] = t1_re_479; + assign Direct_Lookup_Table_n_D_t1_re[480] = t1_re_480; + assign Direct_Lookup_Table_n_D_t1_re[481] = t1_re_481; + assign Direct_Lookup_Table_n_D_t1_re[482] = t1_re_482; + assign Direct_Lookup_Table_n_D_t1_re[483] = t1_re_483; + assign Direct_Lookup_Table_n_D_t1_re[484] = t1_re_484; + assign Direct_Lookup_Table_n_D_t1_re[485] = t1_re_485; + assign Direct_Lookup_Table_n_D_t1_re[486] = t1_re_486; + assign Direct_Lookup_Table_n_D_t1_re[487] = t1_re_487; + assign Direct_Lookup_Table_n_D_t1_re[488] = t1_re_488; + assign Direct_Lookup_Table_n_D_t1_re[489] = t1_re_489; + assign Direct_Lookup_Table_n_D_t1_re[490] = t1_re_490; + assign Direct_Lookup_Table_n_D_t1_re[491] = t1_re_491; + assign Direct_Lookup_Table_n_D_t1_re[492] = t1_re_492; + assign Direct_Lookup_Table_n_D_t1_re[493] = t1_re_493; + assign Direct_Lookup_Table_n_D_t1_re[494] = t1_re_494; + assign Direct_Lookup_Table_n_D_t1_re[495] = t1_re_495; + assign Direct_Lookup_Table_n_D_t1_re[496] = t1_re_496; + assign Direct_Lookup_Table_n_D_t1_re[497] = t1_re_497; + assign Direct_Lookup_Table_n_D_t1_re[498] = t1_re_498; + assign Direct_Lookup_Table_n_D_t1_re[499] = t1_re_499; + assign Direct_Lookup_Table_n_D_t1_re[500] = t1_re_500; + assign Direct_Lookup_Table_n_D_t1_re[501] = t1_re_501; + assign Direct_Lookup_Table_n_D_t1_re[502] = t1_re_502; + assign Direct_Lookup_Table_n_D_t1_re[503] = t1_re_503; + assign Direct_Lookup_Table_n_D_t1_re[504] = t1_re_504; + assign Direct_Lookup_Table_n_D_t1_re[505] = t1_re_505; + assign Direct_Lookup_Table_n_D_t1_re[506] = t1_re_506; + assign Direct_Lookup_Table_n_D_t1_re[507] = t1_re_507; + assign Direct_Lookup_Table_n_D_t1_re[508] = t1_re_508; + assign Direct_Lookup_Table_n_D_t1_re[509] = t1_re_509; + assign Direct_Lookup_Table_n_D_t1_re[510] = t1_re_510; + assign Direct_Lookup_Table_n_D_t1_re[511] = t1_re_511; + assign Direct_Lookup_Table_n_D_t1_im[0] = t1_im_0; + assign Direct_Lookup_Table_n_D_t1_im[1] = t1_im_1; + assign Direct_Lookup_Table_n_D_t1_im[2] = t1_im_2; + assign Direct_Lookup_Table_n_D_t1_im[3] = t1_im_3; + assign Direct_Lookup_Table_n_D_t1_im[4] = t1_im_4; + assign Direct_Lookup_Table_n_D_t1_im[5] = t1_im_5; + assign Direct_Lookup_Table_n_D_t1_im[6] = t1_im_6; + assign Direct_Lookup_Table_n_D_t1_im[7] = t1_im_7; + assign Direct_Lookup_Table_n_D_t1_im[8] = t1_im_8; + assign Direct_Lookup_Table_n_D_t1_im[9] = t1_im_9; + assign Direct_Lookup_Table_n_D_t1_im[10] = t1_im_10; + assign Direct_Lookup_Table_n_D_t1_im[11] = t1_im_11; + assign Direct_Lookup_Table_n_D_t1_im[12] = t1_im_12; + assign Direct_Lookup_Table_n_D_t1_im[13] = t1_im_13; + assign Direct_Lookup_Table_n_D_t1_im[14] = t1_im_14; + assign Direct_Lookup_Table_n_D_t1_im[15] = t1_im_15; + assign Direct_Lookup_Table_n_D_t1_im[16] = t1_im_16; + assign Direct_Lookup_Table_n_D_t1_im[17] = t1_im_17; + assign Direct_Lookup_Table_n_D_t1_im[18] = t1_im_18; + assign Direct_Lookup_Table_n_D_t1_im[19] = t1_im_19; + assign Direct_Lookup_Table_n_D_t1_im[20] = t1_im_20; + assign Direct_Lookup_Table_n_D_t1_im[21] = t1_im_21; + assign Direct_Lookup_Table_n_D_t1_im[22] = t1_im_22; + assign Direct_Lookup_Table_n_D_t1_im[23] = t1_im_23; + assign Direct_Lookup_Table_n_D_t1_im[24] = t1_im_24; + assign Direct_Lookup_Table_n_D_t1_im[25] = t1_im_25; + assign Direct_Lookup_Table_n_D_t1_im[26] = t1_im_26; + assign Direct_Lookup_Table_n_D_t1_im[27] = t1_im_27; + assign Direct_Lookup_Table_n_D_t1_im[28] = t1_im_28; + assign Direct_Lookup_Table_n_D_t1_im[29] = t1_im_29; + assign Direct_Lookup_Table_n_D_t1_im[30] = t1_im_30; + assign Direct_Lookup_Table_n_D_t1_im[31] = t1_im_31; + assign Direct_Lookup_Table_n_D_t1_im[32] = t1_im_32; + assign Direct_Lookup_Table_n_D_t1_im[33] = t1_im_33; + assign Direct_Lookup_Table_n_D_t1_im[34] = t1_im_34; + assign Direct_Lookup_Table_n_D_t1_im[35] = t1_im_35; + assign Direct_Lookup_Table_n_D_t1_im[36] = t1_im_36; + assign Direct_Lookup_Table_n_D_t1_im[37] = t1_im_37; + assign Direct_Lookup_Table_n_D_t1_im[38] = t1_im_38; + assign Direct_Lookup_Table_n_D_t1_im[39] = t1_im_39; + assign Direct_Lookup_Table_n_D_t1_im[40] = t1_im_40; + assign Direct_Lookup_Table_n_D_t1_im[41] = t1_im_41; + assign Direct_Lookup_Table_n_D_t1_im[42] = t1_im_42; + assign Direct_Lookup_Table_n_D_t1_im[43] = t1_im_43; + assign Direct_Lookup_Table_n_D_t1_im[44] = t1_im_44; + assign Direct_Lookup_Table_n_D_t1_im[45] = t1_im_45; + assign Direct_Lookup_Table_n_D_t1_im[46] = t1_im_46; + assign Direct_Lookup_Table_n_D_t1_im[47] = t1_im_47; + assign Direct_Lookup_Table_n_D_t1_im[48] = t1_im_48; + assign Direct_Lookup_Table_n_D_t1_im[49] = t1_im_49; + assign Direct_Lookup_Table_n_D_t1_im[50] = t1_im_50; + assign Direct_Lookup_Table_n_D_t1_im[51] = t1_im_51; + assign Direct_Lookup_Table_n_D_t1_im[52] = t1_im_52; + assign Direct_Lookup_Table_n_D_t1_im[53] = t1_im_53; + assign Direct_Lookup_Table_n_D_t1_im[54] = t1_im_54; + assign Direct_Lookup_Table_n_D_t1_im[55] = t1_im_55; + assign Direct_Lookup_Table_n_D_t1_im[56] = t1_im_56; + assign Direct_Lookup_Table_n_D_t1_im[57] = t1_im_57; + assign Direct_Lookup_Table_n_D_t1_im[58] = t1_im_58; + assign Direct_Lookup_Table_n_D_t1_im[59] = t1_im_59; + assign Direct_Lookup_Table_n_D_t1_im[60] = t1_im_60; + assign Direct_Lookup_Table_n_D_t1_im[61] = t1_im_61; + assign Direct_Lookup_Table_n_D_t1_im[62] = t1_im_62; + assign Direct_Lookup_Table_n_D_t1_im[63] = t1_im_63; + assign Direct_Lookup_Table_n_D_t1_im[64] = t1_im_64; + assign Direct_Lookup_Table_n_D_t1_im[65] = t1_im_65; + assign Direct_Lookup_Table_n_D_t1_im[66] = t1_im_66; + assign Direct_Lookup_Table_n_D_t1_im[67] = t1_im_67; + assign Direct_Lookup_Table_n_D_t1_im[68] = t1_im_68; + assign Direct_Lookup_Table_n_D_t1_im[69] = t1_im_69; + assign Direct_Lookup_Table_n_D_t1_im[70] = t1_im_70; + assign Direct_Lookup_Table_n_D_t1_im[71] = t1_im_71; + assign Direct_Lookup_Table_n_D_t1_im[72] = t1_im_72; + assign Direct_Lookup_Table_n_D_t1_im[73] = t1_im_73; + assign Direct_Lookup_Table_n_D_t1_im[74] = t1_im_74; + assign Direct_Lookup_Table_n_D_t1_im[75] = t1_im_75; + assign Direct_Lookup_Table_n_D_t1_im[76] = t1_im_76; + assign Direct_Lookup_Table_n_D_t1_im[77] = t1_im_77; + assign Direct_Lookup_Table_n_D_t1_im[78] = t1_im_78; + assign Direct_Lookup_Table_n_D_t1_im[79] = t1_im_79; + assign Direct_Lookup_Table_n_D_t1_im[80] = t1_im_80; + assign Direct_Lookup_Table_n_D_t1_im[81] = t1_im_81; + assign Direct_Lookup_Table_n_D_t1_im[82] = t1_im_82; + assign Direct_Lookup_Table_n_D_t1_im[83] = t1_im_83; + assign Direct_Lookup_Table_n_D_t1_im[84] = t1_im_84; + assign Direct_Lookup_Table_n_D_t1_im[85] = t1_im_85; + assign Direct_Lookup_Table_n_D_t1_im[86] = t1_im_86; + assign Direct_Lookup_Table_n_D_t1_im[87] = t1_im_87; + assign Direct_Lookup_Table_n_D_t1_im[88] = t1_im_88; + assign Direct_Lookup_Table_n_D_t1_im[89] = t1_im_89; + assign Direct_Lookup_Table_n_D_t1_im[90] = t1_im_90; + assign Direct_Lookup_Table_n_D_t1_im[91] = t1_im_91; + assign Direct_Lookup_Table_n_D_t1_im[92] = t1_im_92; + assign Direct_Lookup_Table_n_D_t1_im[93] = t1_im_93; + assign Direct_Lookup_Table_n_D_t1_im[94] = t1_im_94; + assign Direct_Lookup_Table_n_D_t1_im[95] = t1_im_95; + assign Direct_Lookup_Table_n_D_t1_im[96] = t1_im_96; + assign Direct_Lookup_Table_n_D_t1_im[97] = t1_im_97; + assign Direct_Lookup_Table_n_D_t1_im[98] = t1_im_98; + assign Direct_Lookup_Table_n_D_t1_im[99] = t1_im_99; + assign Direct_Lookup_Table_n_D_t1_im[100] = t1_im_100; + assign Direct_Lookup_Table_n_D_t1_im[101] = t1_im_101; + assign Direct_Lookup_Table_n_D_t1_im[102] = t1_im_102; + assign Direct_Lookup_Table_n_D_t1_im[103] = t1_im_103; + assign Direct_Lookup_Table_n_D_t1_im[104] = t1_im_104; + assign Direct_Lookup_Table_n_D_t1_im[105] = t1_im_105; + assign Direct_Lookup_Table_n_D_t1_im[106] = t1_im_106; + assign Direct_Lookup_Table_n_D_t1_im[107] = t1_im_107; + assign Direct_Lookup_Table_n_D_t1_im[108] = t1_im_108; + assign Direct_Lookup_Table_n_D_t1_im[109] = t1_im_109; + assign Direct_Lookup_Table_n_D_t1_im[110] = t1_im_110; + assign Direct_Lookup_Table_n_D_t1_im[111] = t1_im_111; + assign Direct_Lookup_Table_n_D_t1_im[112] = t1_im_112; + assign Direct_Lookup_Table_n_D_t1_im[113] = t1_im_113; + assign Direct_Lookup_Table_n_D_t1_im[114] = t1_im_114; + assign Direct_Lookup_Table_n_D_t1_im[115] = t1_im_115; + assign Direct_Lookup_Table_n_D_t1_im[116] = t1_im_116; + assign Direct_Lookup_Table_n_D_t1_im[117] = t1_im_117; + assign Direct_Lookup_Table_n_D_t1_im[118] = t1_im_118; + assign Direct_Lookup_Table_n_D_t1_im[119] = t1_im_119; + assign Direct_Lookup_Table_n_D_t1_im[120] = t1_im_120; + assign Direct_Lookup_Table_n_D_t1_im[121] = t1_im_121; + assign Direct_Lookup_Table_n_D_t1_im[122] = t1_im_122; + assign Direct_Lookup_Table_n_D_t1_im[123] = t1_im_123; + assign Direct_Lookup_Table_n_D_t1_im[124] = t1_im_124; + assign Direct_Lookup_Table_n_D_t1_im[125] = t1_im_125; + assign Direct_Lookup_Table_n_D_t1_im[126] = t1_im_126; + assign Direct_Lookup_Table_n_D_t1_im[127] = t1_im_127; + assign Direct_Lookup_Table_n_D_t1_im[128] = t1_im_128; + assign Direct_Lookup_Table_n_D_t1_im[129] = t1_im_129; + assign Direct_Lookup_Table_n_D_t1_im[130] = t1_im_130; + assign Direct_Lookup_Table_n_D_t1_im[131] = t1_im_131; + assign Direct_Lookup_Table_n_D_t1_im[132] = t1_im_132; + assign Direct_Lookup_Table_n_D_t1_im[133] = t1_im_133; + assign Direct_Lookup_Table_n_D_t1_im[134] = t1_im_134; + assign Direct_Lookup_Table_n_D_t1_im[135] = t1_im_135; + assign Direct_Lookup_Table_n_D_t1_im[136] = t1_im_136; + assign Direct_Lookup_Table_n_D_t1_im[137] = t1_im_137; + assign Direct_Lookup_Table_n_D_t1_im[138] = t1_im_138; + assign Direct_Lookup_Table_n_D_t1_im[139] = t1_im_139; + assign Direct_Lookup_Table_n_D_t1_im[140] = t1_im_140; + assign Direct_Lookup_Table_n_D_t1_im[141] = t1_im_141; + assign Direct_Lookup_Table_n_D_t1_im[142] = t1_im_142; + assign Direct_Lookup_Table_n_D_t1_im[143] = t1_im_143; + assign Direct_Lookup_Table_n_D_t1_im[144] = t1_im_144; + assign Direct_Lookup_Table_n_D_t1_im[145] = t1_im_145; + assign Direct_Lookup_Table_n_D_t1_im[146] = t1_im_146; + assign Direct_Lookup_Table_n_D_t1_im[147] = t1_im_147; + assign Direct_Lookup_Table_n_D_t1_im[148] = t1_im_148; + assign Direct_Lookup_Table_n_D_t1_im[149] = t1_im_149; + assign Direct_Lookup_Table_n_D_t1_im[150] = t1_im_150; + assign Direct_Lookup_Table_n_D_t1_im[151] = t1_im_151; + assign Direct_Lookup_Table_n_D_t1_im[152] = t1_im_152; + assign Direct_Lookup_Table_n_D_t1_im[153] = t1_im_153; + assign Direct_Lookup_Table_n_D_t1_im[154] = t1_im_154; + assign Direct_Lookup_Table_n_D_t1_im[155] = t1_im_155; + assign Direct_Lookup_Table_n_D_t1_im[156] = t1_im_156; + assign Direct_Lookup_Table_n_D_t1_im[157] = t1_im_157; + assign Direct_Lookup_Table_n_D_t1_im[158] = t1_im_158; + assign Direct_Lookup_Table_n_D_t1_im[159] = t1_im_159; + assign Direct_Lookup_Table_n_D_t1_im[160] = t1_im_160; + assign Direct_Lookup_Table_n_D_t1_im[161] = t1_im_161; + assign Direct_Lookup_Table_n_D_t1_im[162] = t1_im_162; + assign Direct_Lookup_Table_n_D_t1_im[163] = t1_im_163; + assign Direct_Lookup_Table_n_D_t1_im[164] = t1_im_164; + assign Direct_Lookup_Table_n_D_t1_im[165] = t1_im_165; + assign Direct_Lookup_Table_n_D_t1_im[166] = t1_im_166; + assign Direct_Lookup_Table_n_D_t1_im[167] = t1_im_167; + assign Direct_Lookup_Table_n_D_t1_im[168] = t1_im_168; + assign Direct_Lookup_Table_n_D_t1_im[169] = t1_im_169; + assign Direct_Lookup_Table_n_D_t1_im[170] = t1_im_170; + assign Direct_Lookup_Table_n_D_t1_im[171] = t1_im_171; + assign Direct_Lookup_Table_n_D_t1_im[172] = t1_im_172; + assign Direct_Lookup_Table_n_D_t1_im[173] = t1_im_173; + assign Direct_Lookup_Table_n_D_t1_im[174] = t1_im_174; + assign Direct_Lookup_Table_n_D_t1_im[175] = t1_im_175; + assign Direct_Lookup_Table_n_D_t1_im[176] = t1_im_176; + assign Direct_Lookup_Table_n_D_t1_im[177] = t1_im_177; + assign Direct_Lookup_Table_n_D_t1_im[178] = t1_im_178; + assign Direct_Lookup_Table_n_D_t1_im[179] = t1_im_179; + assign Direct_Lookup_Table_n_D_t1_im[180] = t1_im_180; + assign Direct_Lookup_Table_n_D_t1_im[181] = t1_im_181; + assign Direct_Lookup_Table_n_D_t1_im[182] = t1_im_182; + assign Direct_Lookup_Table_n_D_t1_im[183] = t1_im_183; + assign Direct_Lookup_Table_n_D_t1_im[184] = t1_im_184; + assign Direct_Lookup_Table_n_D_t1_im[185] = t1_im_185; + assign Direct_Lookup_Table_n_D_t1_im[186] = t1_im_186; + assign Direct_Lookup_Table_n_D_t1_im[187] = t1_im_187; + assign Direct_Lookup_Table_n_D_t1_im[188] = t1_im_188; + assign Direct_Lookup_Table_n_D_t1_im[189] = t1_im_189; + assign Direct_Lookup_Table_n_D_t1_im[190] = t1_im_190; + assign Direct_Lookup_Table_n_D_t1_im[191] = t1_im_191; + assign Direct_Lookup_Table_n_D_t1_im[192] = t1_im_192; + assign Direct_Lookup_Table_n_D_t1_im[193] = t1_im_193; + assign Direct_Lookup_Table_n_D_t1_im[194] = t1_im_194; + assign Direct_Lookup_Table_n_D_t1_im[195] = t1_im_195; + assign Direct_Lookup_Table_n_D_t1_im[196] = t1_im_196; + assign Direct_Lookup_Table_n_D_t1_im[197] = t1_im_197; + assign Direct_Lookup_Table_n_D_t1_im[198] = t1_im_198; + assign Direct_Lookup_Table_n_D_t1_im[199] = t1_im_199; + assign Direct_Lookup_Table_n_D_t1_im[200] = t1_im_200; + assign Direct_Lookup_Table_n_D_t1_im[201] = t1_im_201; + assign Direct_Lookup_Table_n_D_t1_im[202] = t1_im_202; + assign Direct_Lookup_Table_n_D_t1_im[203] = t1_im_203; + assign Direct_Lookup_Table_n_D_t1_im[204] = t1_im_204; + assign Direct_Lookup_Table_n_D_t1_im[205] = t1_im_205; + assign Direct_Lookup_Table_n_D_t1_im[206] = t1_im_206; + assign Direct_Lookup_Table_n_D_t1_im[207] = t1_im_207; + assign Direct_Lookup_Table_n_D_t1_im[208] = t1_im_208; + assign Direct_Lookup_Table_n_D_t1_im[209] = t1_im_209; + assign Direct_Lookup_Table_n_D_t1_im[210] = t1_im_210; + assign Direct_Lookup_Table_n_D_t1_im[211] = t1_im_211; + assign Direct_Lookup_Table_n_D_t1_im[212] = t1_im_212; + assign Direct_Lookup_Table_n_D_t1_im[213] = t1_im_213; + assign Direct_Lookup_Table_n_D_t1_im[214] = t1_im_214; + assign Direct_Lookup_Table_n_D_t1_im[215] = t1_im_215; + assign Direct_Lookup_Table_n_D_t1_im[216] = t1_im_216; + assign Direct_Lookup_Table_n_D_t1_im[217] = t1_im_217; + assign Direct_Lookup_Table_n_D_t1_im[218] = t1_im_218; + assign Direct_Lookup_Table_n_D_t1_im[219] = t1_im_219; + assign Direct_Lookup_Table_n_D_t1_im[220] = t1_im_220; + assign Direct_Lookup_Table_n_D_t1_im[221] = t1_im_221; + assign Direct_Lookup_Table_n_D_t1_im[222] = t1_im_222; + assign Direct_Lookup_Table_n_D_t1_im[223] = t1_im_223; + assign Direct_Lookup_Table_n_D_t1_im[224] = t1_im_224; + assign Direct_Lookup_Table_n_D_t1_im[225] = t1_im_225; + assign Direct_Lookup_Table_n_D_t1_im[226] = t1_im_226; + assign Direct_Lookup_Table_n_D_t1_im[227] = t1_im_227; + assign Direct_Lookup_Table_n_D_t1_im[228] = t1_im_228; + assign Direct_Lookup_Table_n_D_t1_im[229] = t1_im_229; + assign Direct_Lookup_Table_n_D_t1_im[230] = t1_im_230; + assign Direct_Lookup_Table_n_D_t1_im[231] = t1_im_231; + assign Direct_Lookup_Table_n_D_t1_im[232] = t1_im_232; + assign Direct_Lookup_Table_n_D_t1_im[233] = t1_im_233; + assign Direct_Lookup_Table_n_D_t1_im[234] = t1_im_234; + assign Direct_Lookup_Table_n_D_t1_im[235] = t1_im_235; + assign Direct_Lookup_Table_n_D_t1_im[236] = t1_im_236; + assign Direct_Lookup_Table_n_D_t1_im[237] = t1_im_237; + assign Direct_Lookup_Table_n_D_t1_im[238] = t1_im_238; + assign Direct_Lookup_Table_n_D_t1_im[239] = t1_im_239; + assign Direct_Lookup_Table_n_D_t1_im[240] = t1_im_240; + assign Direct_Lookup_Table_n_D_t1_im[241] = t1_im_241; + assign Direct_Lookup_Table_n_D_t1_im[242] = t1_im_242; + assign Direct_Lookup_Table_n_D_t1_im[243] = t1_im_243; + assign Direct_Lookup_Table_n_D_t1_im[244] = t1_im_244; + assign Direct_Lookup_Table_n_D_t1_im[245] = t1_im_245; + assign Direct_Lookup_Table_n_D_t1_im[246] = t1_im_246; + assign Direct_Lookup_Table_n_D_t1_im[247] = t1_im_247; + assign Direct_Lookup_Table_n_D_t1_im[248] = t1_im_248; + assign Direct_Lookup_Table_n_D_t1_im[249] = t1_im_249; + assign Direct_Lookup_Table_n_D_t1_im[250] = t1_im_250; + assign Direct_Lookup_Table_n_D_t1_im[251] = t1_im_251; + assign Direct_Lookup_Table_n_D_t1_im[252] = t1_im_252; + assign Direct_Lookup_Table_n_D_t1_im[253] = t1_im_253; + assign Direct_Lookup_Table_n_D_t1_im[254] = t1_im_254; + assign Direct_Lookup_Table_n_D_t1_im[255] = t1_im_255; + assign Direct_Lookup_Table_n_D_t1_im[256] = t1_im_256; + assign Direct_Lookup_Table_n_D_t1_im[257] = t1_im_257; + assign Direct_Lookup_Table_n_D_t1_im[258] = t1_im_258; + assign Direct_Lookup_Table_n_D_t1_im[259] = t1_im_259; + assign Direct_Lookup_Table_n_D_t1_im[260] = t1_im_260; + assign Direct_Lookup_Table_n_D_t1_im[261] = t1_im_261; + assign Direct_Lookup_Table_n_D_t1_im[262] = t1_im_262; + assign Direct_Lookup_Table_n_D_t1_im[263] = t1_im_263; + assign Direct_Lookup_Table_n_D_t1_im[264] = t1_im_264; + assign Direct_Lookup_Table_n_D_t1_im[265] = t1_im_265; + assign Direct_Lookup_Table_n_D_t1_im[266] = t1_im_266; + assign Direct_Lookup_Table_n_D_t1_im[267] = t1_im_267; + assign Direct_Lookup_Table_n_D_t1_im[268] = t1_im_268; + assign Direct_Lookup_Table_n_D_t1_im[269] = t1_im_269; + assign Direct_Lookup_Table_n_D_t1_im[270] = t1_im_270; + assign Direct_Lookup_Table_n_D_t1_im[271] = t1_im_271; + assign Direct_Lookup_Table_n_D_t1_im[272] = t1_im_272; + assign Direct_Lookup_Table_n_D_t1_im[273] = t1_im_273; + assign Direct_Lookup_Table_n_D_t1_im[274] = t1_im_274; + assign Direct_Lookup_Table_n_D_t1_im[275] = t1_im_275; + assign Direct_Lookup_Table_n_D_t1_im[276] = t1_im_276; + assign Direct_Lookup_Table_n_D_t1_im[277] = t1_im_277; + assign Direct_Lookup_Table_n_D_t1_im[278] = t1_im_278; + assign Direct_Lookup_Table_n_D_t1_im[279] = t1_im_279; + assign Direct_Lookup_Table_n_D_t1_im[280] = t1_im_280; + assign Direct_Lookup_Table_n_D_t1_im[281] = t1_im_281; + assign Direct_Lookup_Table_n_D_t1_im[282] = t1_im_282; + assign Direct_Lookup_Table_n_D_t1_im[283] = t1_im_283; + assign Direct_Lookup_Table_n_D_t1_im[284] = t1_im_284; + assign Direct_Lookup_Table_n_D_t1_im[285] = t1_im_285; + assign Direct_Lookup_Table_n_D_t1_im[286] = t1_im_286; + assign Direct_Lookup_Table_n_D_t1_im[287] = t1_im_287; + assign Direct_Lookup_Table_n_D_t1_im[288] = t1_im_288; + assign Direct_Lookup_Table_n_D_t1_im[289] = t1_im_289; + assign Direct_Lookup_Table_n_D_t1_im[290] = t1_im_290; + assign Direct_Lookup_Table_n_D_t1_im[291] = t1_im_291; + assign Direct_Lookup_Table_n_D_t1_im[292] = t1_im_292; + assign Direct_Lookup_Table_n_D_t1_im[293] = t1_im_293; + assign Direct_Lookup_Table_n_D_t1_im[294] = t1_im_294; + assign Direct_Lookup_Table_n_D_t1_im[295] = t1_im_295; + assign Direct_Lookup_Table_n_D_t1_im[296] = t1_im_296; + assign Direct_Lookup_Table_n_D_t1_im[297] = t1_im_297; + assign Direct_Lookup_Table_n_D_t1_im[298] = t1_im_298; + assign Direct_Lookup_Table_n_D_t1_im[299] = t1_im_299; + assign Direct_Lookup_Table_n_D_t1_im[300] = t1_im_300; + assign Direct_Lookup_Table_n_D_t1_im[301] = t1_im_301; + assign Direct_Lookup_Table_n_D_t1_im[302] = t1_im_302; + assign Direct_Lookup_Table_n_D_t1_im[303] = t1_im_303; + assign Direct_Lookup_Table_n_D_t1_im[304] = t1_im_304; + assign Direct_Lookup_Table_n_D_t1_im[305] = t1_im_305; + assign Direct_Lookup_Table_n_D_t1_im[306] = t1_im_306; + assign Direct_Lookup_Table_n_D_t1_im[307] = t1_im_307; + assign Direct_Lookup_Table_n_D_t1_im[308] = t1_im_308; + assign Direct_Lookup_Table_n_D_t1_im[309] = t1_im_309; + assign Direct_Lookup_Table_n_D_t1_im[310] = t1_im_310; + assign Direct_Lookup_Table_n_D_t1_im[311] = t1_im_311; + assign Direct_Lookup_Table_n_D_t1_im[312] = t1_im_312; + assign Direct_Lookup_Table_n_D_t1_im[313] = t1_im_313; + assign Direct_Lookup_Table_n_D_t1_im[314] = t1_im_314; + assign Direct_Lookup_Table_n_D_t1_im[315] = t1_im_315; + assign Direct_Lookup_Table_n_D_t1_im[316] = t1_im_316; + assign Direct_Lookup_Table_n_D_t1_im[317] = t1_im_317; + assign Direct_Lookup_Table_n_D_t1_im[318] = t1_im_318; + assign Direct_Lookup_Table_n_D_t1_im[319] = t1_im_319; + assign Direct_Lookup_Table_n_D_t1_im[320] = t1_im_320; + assign Direct_Lookup_Table_n_D_t1_im[321] = t1_im_321; + assign Direct_Lookup_Table_n_D_t1_im[322] = t1_im_322; + assign Direct_Lookup_Table_n_D_t1_im[323] = t1_im_323; + assign Direct_Lookup_Table_n_D_t1_im[324] = t1_im_324; + assign Direct_Lookup_Table_n_D_t1_im[325] = t1_im_325; + assign Direct_Lookup_Table_n_D_t1_im[326] = t1_im_326; + assign Direct_Lookup_Table_n_D_t1_im[327] = t1_im_327; + assign Direct_Lookup_Table_n_D_t1_im[328] = t1_im_328; + assign Direct_Lookup_Table_n_D_t1_im[329] = t1_im_329; + assign Direct_Lookup_Table_n_D_t1_im[330] = t1_im_330; + assign Direct_Lookup_Table_n_D_t1_im[331] = t1_im_331; + assign Direct_Lookup_Table_n_D_t1_im[332] = t1_im_332; + assign Direct_Lookup_Table_n_D_t1_im[333] = t1_im_333; + assign Direct_Lookup_Table_n_D_t1_im[334] = t1_im_334; + assign Direct_Lookup_Table_n_D_t1_im[335] = t1_im_335; + assign Direct_Lookup_Table_n_D_t1_im[336] = t1_im_336; + assign Direct_Lookup_Table_n_D_t1_im[337] = t1_im_337; + assign Direct_Lookup_Table_n_D_t1_im[338] = t1_im_338; + assign Direct_Lookup_Table_n_D_t1_im[339] = t1_im_339; + assign Direct_Lookup_Table_n_D_t1_im[340] = t1_im_340; + assign Direct_Lookup_Table_n_D_t1_im[341] = t1_im_341; + assign Direct_Lookup_Table_n_D_t1_im[342] = t1_im_342; + assign Direct_Lookup_Table_n_D_t1_im[343] = t1_im_343; + assign Direct_Lookup_Table_n_D_t1_im[344] = t1_im_344; + assign Direct_Lookup_Table_n_D_t1_im[345] = t1_im_345; + assign Direct_Lookup_Table_n_D_t1_im[346] = t1_im_346; + assign Direct_Lookup_Table_n_D_t1_im[347] = t1_im_347; + assign Direct_Lookup_Table_n_D_t1_im[348] = t1_im_348; + assign Direct_Lookup_Table_n_D_t1_im[349] = t1_im_349; + assign Direct_Lookup_Table_n_D_t1_im[350] = t1_im_350; + assign Direct_Lookup_Table_n_D_t1_im[351] = t1_im_351; + assign Direct_Lookup_Table_n_D_t1_im[352] = t1_im_352; + assign Direct_Lookup_Table_n_D_t1_im[353] = t1_im_353; + assign Direct_Lookup_Table_n_D_t1_im[354] = t1_im_354; + assign Direct_Lookup_Table_n_D_t1_im[355] = t1_im_355; + assign Direct_Lookup_Table_n_D_t1_im[356] = t1_im_356; + assign Direct_Lookup_Table_n_D_t1_im[357] = t1_im_357; + assign Direct_Lookup_Table_n_D_t1_im[358] = t1_im_358; + assign Direct_Lookup_Table_n_D_t1_im[359] = t1_im_359; + assign Direct_Lookup_Table_n_D_t1_im[360] = t1_im_360; + assign Direct_Lookup_Table_n_D_t1_im[361] = t1_im_361; + assign Direct_Lookup_Table_n_D_t1_im[362] = t1_im_362; + assign Direct_Lookup_Table_n_D_t1_im[363] = t1_im_363; + assign Direct_Lookup_Table_n_D_t1_im[364] = t1_im_364; + assign Direct_Lookup_Table_n_D_t1_im[365] = t1_im_365; + assign Direct_Lookup_Table_n_D_t1_im[366] = t1_im_366; + assign Direct_Lookup_Table_n_D_t1_im[367] = t1_im_367; + assign Direct_Lookup_Table_n_D_t1_im[368] = t1_im_368; + assign Direct_Lookup_Table_n_D_t1_im[369] = t1_im_369; + assign Direct_Lookup_Table_n_D_t1_im[370] = t1_im_370; + assign Direct_Lookup_Table_n_D_t1_im[371] = t1_im_371; + assign Direct_Lookup_Table_n_D_t1_im[372] = t1_im_372; + assign Direct_Lookup_Table_n_D_t1_im[373] = t1_im_373; + assign Direct_Lookup_Table_n_D_t1_im[374] = t1_im_374; + assign Direct_Lookup_Table_n_D_t1_im[375] = t1_im_375; + assign Direct_Lookup_Table_n_D_t1_im[376] = t1_im_376; + assign Direct_Lookup_Table_n_D_t1_im[377] = t1_im_377; + assign Direct_Lookup_Table_n_D_t1_im[378] = t1_im_378; + assign Direct_Lookup_Table_n_D_t1_im[379] = t1_im_379; + assign Direct_Lookup_Table_n_D_t1_im[380] = t1_im_380; + assign Direct_Lookup_Table_n_D_t1_im[381] = t1_im_381; + assign Direct_Lookup_Table_n_D_t1_im[382] = t1_im_382; + assign Direct_Lookup_Table_n_D_t1_im[383] = t1_im_383; + assign Direct_Lookup_Table_n_D_t1_im[384] = t1_im_384; + assign Direct_Lookup_Table_n_D_t1_im[385] = t1_im_385; + assign Direct_Lookup_Table_n_D_t1_im[386] = t1_im_386; + assign Direct_Lookup_Table_n_D_t1_im[387] = t1_im_387; + assign Direct_Lookup_Table_n_D_t1_im[388] = t1_im_388; + assign Direct_Lookup_Table_n_D_t1_im[389] = t1_im_389; + assign Direct_Lookup_Table_n_D_t1_im[390] = t1_im_390; + assign Direct_Lookup_Table_n_D_t1_im[391] = t1_im_391; + assign Direct_Lookup_Table_n_D_t1_im[392] = t1_im_392; + assign Direct_Lookup_Table_n_D_t1_im[393] = t1_im_393; + assign Direct_Lookup_Table_n_D_t1_im[394] = t1_im_394; + assign Direct_Lookup_Table_n_D_t1_im[395] = t1_im_395; + assign Direct_Lookup_Table_n_D_t1_im[396] = t1_im_396; + assign Direct_Lookup_Table_n_D_t1_im[397] = t1_im_397; + assign Direct_Lookup_Table_n_D_t1_im[398] = t1_im_398; + assign Direct_Lookup_Table_n_D_t1_im[399] = t1_im_399; + assign Direct_Lookup_Table_n_D_t1_im[400] = t1_im_400; + assign Direct_Lookup_Table_n_D_t1_im[401] = t1_im_401; + assign Direct_Lookup_Table_n_D_t1_im[402] = t1_im_402; + assign Direct_Lookup_Table_n_D_t1_im[403] = t1_im_403; + assign Direct_Lookup_Table_n_D_t1_im[404] = t1_im_404; + assign Direct_Lookup_Table_n_D_t1_im[405] = t1_im_405; + assign Direct_Lookup_Table_n_D_t1_im[406] = t1_im_406; + assign Direct_Lookup_Table_n_D_t1_im[407] = t1_im_407; + assign Direct_Lookup_Table_n_D_t1_im[408] = t1_im_408; + assign Direct_Lookup_Table_n_D_t1_im[409] = t1_im_409; + assign Direct_Lookup_Table_n_D_t1_im[410] = t1_im_410; + assign Direct_Lookup_Table_n_D_t1_im[411] = t1_im_411; + assign Direct_Lookup_Table_n_D_t1_im[412] = t1_im_412; + assign Direct_Lookup_Table_n_D_t1_im[413] = t1_im_413; + assign Direct_Lookup_Table_n_D_t1_im[414] = t1_im_414; + assign Direct_Lookup_Table_n_D_t1_im[415] = t1_im_415; + assign Direct_Lookup_Table_n_D_t1_im[416] = t1_im_416; + assign Direct_Lookup_Table_n_D_t1_im[417] = t1_im_417; + assign Direct_Lookup_Table_n_D_t1_im[418] = t1_im_418; + assign Direct_Lookup_Table_n_D_t1_im[419] = t1_im_419; + assign Direct_Lookup_Table_n_D_t1_im[420] = t1_im_420; + assign Direct_Lookup_Table_n_D_t1_im[421] = t1_im_421; + assign Direct_Lookup_Table_n_D_t1_im[422] = t1_im_422; + assign Direct_Lookup_Table_n_D_t1_im[423] = t1_im_423; + assign Direct_Lookup_Table_n_D_t1_im[424] = t1_im_424; + assign Direct_Lookup_Table_n_D_t1_im[425] = t1_im_425; + assign Direct_Lookup_Table_n_D_t1_im[426] = t1_im_426; + assign Direct_Lookup_Table_n_D_t1_im[427] = t1_im_427; + assign Direct_Lookup_Table_n_D_t1_im[428] = t1_im_428; + assign Direct_Lookup_Table_n_D_t1_im[429] = t1_im_429; + assign Direct_Lookup_Table_n_D_t1_im[430] = t1_im_430; + assign Direct_Lookup_Table_n_D_t1_im[431] = t1_im_431; + assign Direct_Lookup_Table_n_D_t1_im[432] = t1_im_432; + assign Direct_Lookup_Table_n_D_t1_im[433] = t1_im_433; + assign Direct_Lookup_Table_n_D_t1_im[434] = t1_im_434; + assign Direct_Lookup_Table_n_D_t1_im[435] = t1_im_435; + assign Direct_Lookup_Table_n_D_t1_im[436] = t1_im_436; + assign Direct_Lookup_Table_n_D_t1_im[437] = t1_im_437; + assign Direct_Lookup_Table_n_D_t1_im[438] = t1_im_438; + assign Direct_Lookup_Table_n_D_t1_im[439] = t1_im_439; + assign Direct_Lookup_Table_n_D_t1_im[440] = t1_im_440; + assign Direct_Lookup_Table_n_D_t1_im[441] = t1_im_441; + assign Direct_Lookup_Table_n_D_t1_im[442] = t1_im_442; + assign Direct_Lookup_Table_n_D_t1_im[443] = t1_im_443; + assign Direct_Lookup_Table_n_D_t1_im[444] = t1_im_444; + assign Direct_Lookup_Table_n_D_t1_im[445] = t1_im_445; + assign Direct_Lookup_Table_n_D_t1_im[446] = t1_im_446; + assign Direct_Lookup_Table_n_D_t1_im[447] = t1_im_447; + assign Direct_Lookup_Table_n_D_t1_im[448] = t1_im_448; + assign Direct_Lookup_Table_n_D_t1_im[449] = t1_im_449; + assign Direct_Lookup_Table_n_D_t1_im[450] = t1_im_450; + assign Direct_Lookup_Table_n_D_t1_im[451] = t1_im_451; + assign Direct_Lookup_Table_n_D_t1_im[452] = t1_im_452; + assign Direct_Lookup_Table_n_D_t1_im[453] = t1_im_453; + assign Direct_Lookup_Table_n_D_t1_im[454] = t1_im_454; + assign Direct_Lookup_Table_n_D_t1_im[455] = t1_im_455; + assign Direct_Lookup_Table_n_D_t1_im[456] = t1_im_456; + assign Direct_Lookup_Table_n_D_t1_im[457] = t1_im_457; + assign Direct_Lookup_Table_n_D_t1_im[458] = t1_im_458; + assign Direct_Lookup_Table_n_D_t1_im[459] = t1_im_459; + assign Direct_Lookup_Table_n_D_t1_im[460] = t1_im_460; + assign Direct_Lookup_Table_n_D_t1_im[461] = t1_im_461; + assign Direct_Lookup_Table_n_D_t1_im[462] = t1_im_462; + assign Direct_Lookup_Table_n_D_t1_im[463] = t1_im_463; + assign Direct_Lookup_Table_n_D_t1_im[464] = t1_im_464; + assign Direct_Lookup_Table_n_D_t1_im[465] = t1_im_465; + assign Direct_Lookup_Table_n_D_t1_im[466] = t1_im_466; + assign Direct_Lookup_Table_n_D_t1_im[467] = t1_im_467; + assign Direct_Lookup_Table_n_D_t1_im[468] = t1_im_468; + assign Direct_Lookup_Table_n_D_t1_im[469] = t1_im_469; + assign Direct_Lookup_Table_n_D_t1_im[470] = t1_im_470; + assign Direct_Lookup_Table_n_D_t1_im[471] = t1_im_471; + assign Direct_Lookup_Table_n_D_t1_im[472] = t1_im_472; + assign Direct_Lookup_Table_n_D_t1_im[473] = t1_im_473; + assign Direct_Lookup_Table_n_D_t1_im[474] = t1_im_474; + assign Direct_Lookup_Table_n_D_t1_im[475] = t1_im_475; + assign Direct_Lookup_Table_n_D_t1_im[476] = t1_im_476; + assign Direct_Lookup_Table_n_D_t1_im[477] = t1_im_477; + assign Direct_Lookup_Table_n_D_t1_im[478] = t1_im_478; + assign Direct_Lookup_Table_n_D_t1_im[479] = t1_im_479; + assign Direct_Lookup_Table_n_D_t1_im[480] = t1_im_480; + assign Direct_Lookup_Table_n_D_t1_im[481] = t1_im_481; + assign Direct_Lookup_Table_n_D_t1_im[482] = t1_im_482; + assign Direct_Lookup_Table_n_D_t1_im[483] = t1_im_483; + assign Direct_Lookup_Table_n_D_t1_im[484] = t1_im_484; + assign Direct_Lookup_Table_n_D_t1_im[485] = t1_im_485; + assign Direct_Lookup_Table_n_D_t1_im[486] = t1_im_486; + assign Direct_Lookup_Table_n_D_t1_im[487] = t1_im_487; + assign Direct_Lookup_Table_n_D_t1_im[488] = t1_im_488; + assign Direct_Lookup_Table_n_D_t1_im[489] = t1_im_489; + assign Direct_Lookup_Table_n_D_t1_im[490] = t1_im_490; + assign Direct_Lookup_Table_n_D_t1_im[491] = t1_im_491; + assign Direct_Lookup_Table_n_D_t1_im[492] = t1_im_492; + assign Direct_Lookup_Table_n_D_t1_im[493] = t1_im_493; + assign Direct_Lookup_Table_n_D_t1_im[494] = t1_im_494; + assign Direct_Lookup_Table_n_D_t1_im[495] = t1_im_495; + assign Direct_Lookup_Table_n_D_t1_im[496] = t1_im_496; + assign Direct_Lookup_Table_n_D_t1_im[497] = t1_im_497; + assign Direct_Lookup_Table_n_D_t1_im[498] = t1_im_498; + assign Direct_Lookup_Table_n_D_t1_im[499] = t1_im_499; + assign Direct_Lookup_Table_n_D_t1_im[500] = t1_im_500; + assign Direct_Lookup_Table_n_D_t1_im[501] = t1_im_501; + assign Direct_Lookup_Table_n_D_t1_im[502] = t1_im_502; + assign Direct_Lookup_Table_n_D_t1_im[503] = t1_im_503; + assign Direct_Lookup_Table_n_D_t1_im[504] = t1_im_504; + assign Direct_Lookup_Table_n_D_t1_im[505] = t1_im_505; + assign Direct_Lookup_Table_n_D_t1_im[506] = t1_im_506; + assign Direct_Lookup_Table_n_D_t1_im[507] = t1_im_507; + assign Direct_Lookup_Table_n_D_t1_im[508] = t1_im_508; + assign Direct_Lookup_Table_n_D_t1_im[509] = t1_im_509; + assign Direct_Lookup_Table_n_D_t1_im[510] = t1_im_510; + assign Direct_Lookup_Table_n_D_t1_im[511] = t1_im_511; + assign Direct_Lookup_Table_n_D_out1_re = Direct_Lookup_Table_n_D_t1_re[Data_Type_Conversion1_out1]; + assign Direct_Lookup_Table_n_D_out1_im = Direct_Lookup_Table_n_D_t1_im[Data_Type_Conversion1_out1]; + + + + // /Mark_Extract_Bits1 + controllerHdl_Mark_Extract_Bits1 u_Mark_Extract_Bits1 (.In1(elec_pos_scaled), // ufix18 + .Out1(y_1) // ufix9 + ); + + // /Data Type Conversion2 + assign Data_Type_Conversion2_out1 = y_1; + + + + // /Direct Lookup Table (n-D)1 + assign Direct_Lookup_Table_n_D_1_t1_re[0] = t1_re_0_2; + assign Direct_Lookup_Table_n_D_1_t1_re[1] = t1_re_1_2; + assign Direct_Lookup_Table_n_D_1_t1_re[2] = t1_re_2_2; + assign Direct_Lookup_Table_n_D_1_t1_re[3] = t1_re_3_2; + assign Direct_Lookup_Table_n_D_1_t1_re[4] = t1_re_4_2; + assign Direct_Lookup_Table_n_D_1_t1_re[5] = t1_re_5_2; + assign Direct_Lookup_Table_n_D_1_t1_re[6] = t1_re_6_2; + assign Direct_Lookup_Table_n_D_1_t1_re[7] = t1_re_7_2; + assign Direct_Lookup_Table_n_D_1_t1_re[8] = t1_re_8_2; + assign Direct_Lookup_Table_n_D_1_t1_re[9] = t1_re_9_2; + assign Direct_Lookup_Table_n_D_1_t1_re[10] = t1_re_10_2; + assign Direct_Lookup_Table_n_D_1_t1_re[11] = t1_re_11_2; + assign Direct_Lookup_Table_n_D_1_t1_re[12] = t1_re_12_2; + assign Direct_Lookup_Table_n_D_1_t1_re[13] = t1_re_13_2; + assign Direct_Lookup_Table_n_D_1_t1_re[14] = t1_re_14_2; + assign Direct_Lookup_Table_n_D_1_t1_re[15] = t1_re_15_2; + assign Direct_Lookup_Table_n_D_1_t1_re[16] = t1_re_16_2; + assign Direct_Lookup_Table_n_D_1_t1_re[17] = t1_re_17_2; + assign Direct_Lookup_Table_n_D_1_t1_re[18] = t1_re_18_2; + assign Direct_Lookup_Table_n_D_1_t1_re[19] = t1_re_19_2; + assign Direct_Lookup_Table_n_D_1_t1_re[20] = t1_re_20_2; + assign Direct_Lookup_Table_n_D_1_t1_re[21] = t1_re_21_2; + assign Direct_Lookup_Table_n_D_1_t1_re[22] = t1_re_22_2; + assign Direct_Lookup_Table_n_D_1_t1_re[23] = t1_re_23_2; + assign Direct_Lookup_Table_n_D_1_t1_re[24] = t1_re_24_2; + assign Direct_Lookup_Table_n_D_1_t1_re[25] = t1_re_25_2; + assign Direct_Lookup_Table_n_D_1_t1_re[26] = t1_re_26_2; + assign Direct_Lookup_Table_n_D_1_t1_re[27] = t1_re_27_2; + assign Direct_Lookup_Table_n_D_1_t1_re[28] = t1_re_28_2; + assign Direct_Lookup_Table_n_D_1_t1_re[29] = t1_re_29_2; + assign Direct_Lookup_Table_n_D_1_t1_re[30] = t1_re_30_2; + assign Direct_Lookup_Table_n_D_1_t1_re[31] = t1_re_31_2; + assign Direct_Lookup_Table_n_D_1_t1_re[32] = t1_re_32_2; + assign Direct_Lookup_Table_n_D_1_t1_re[33] = t1_re_33_2; + assign Direct_Lookup_Table_n_D_1_t1_re[34] = t1_re_34_2; + assign Direct_Lookup_Table_n_D_1_t1_re[35] = t1_re_35_2; + assign Direct_Lookup_Table_n_D_1_t1_re[36] = t1_re_36_2; + assign Direct_Lookup_Table_n_D_1_t1_re[37] = t1_re_37_2; + assign Direct_Lookup_Table_n_D_1_t1_re[38] = t1_re_38_2; + assign Direct_Lookup_Table_n_D_1_t1_re[39] = t1_re_39_2; + assign Direct_Lookup_Table_n_D_1_t1_re[40] = t1_re_40_2; + assign Direct_Lookup_Table_n_D_1_t1_re[41] = t1_re_41_2; + assign Direct_Lookup_Table_n_D_1_t1_re[42] = t1_re_42_2; + assign Direct_Lookup_Table_n_D_1_t1_re[43] = t1_re_43_2; + assign Direct_Lookup_Table_n_D_1_t1_re[44] = t1_re_44_2; + assign Direct_Lookup_Table_n_D_1_t1_re[45] = t1_re_45_2; + assign Direct_Lookup_Table_n_D_1_t1_re[46] = t1_re_46_2; + assign Direct_Lookup_Table_n_D_1_t1_re[47] = t1_re_47_2; + assign Direct_Lookup_Table_n_D_1_t1_re[48] = t1_re_48_2; + assign Direct_Lookup_Table_n_D_1_t1_re[49] = t1_re_49_2; + assign Direct_Lookup_Table_n_D_1_t1_re[50] = t1_re_50_2; + assign Direct_Lookup_Table_n_D_1_t1_re[51] = t1_re_51_2; + assign Direct_Lookup_Table_n_D_1_t1_re[52] = t1_re_52_2; + assign Direct_Lookup_Table_n_D_1_t1_re[53] = t1_re_53_2; + assign Direct_Lookup_Table_n_D_1_t1_re[54] = t1_re_54_2; + assign Direct_Lookup_Table_n_D_1_t1_re[55] = t1_re_55_2; + assign Direct_Lookup_Table_n_D_1_t1_re[56] = t1_re_56_2; + assign Direct_Lookup_Table_n_D_1_t1_re[57] = t1_re_57_2; + assign Direct_Lookup_Table_n_D_1_t1_re[58] = t1_re_58_2; + assign Direct_Lookup_Table_n_D_1_t1_re[59] = t1_re_59_2; + assign Direct_Lookup_Table_n_D_1_t1_re[60] = t1_re_60_2; + assign Direct_Lookup_Table_n_D_1_t1_re[61] = t1_re_61_2; + assign Direct_Lookup_Table_n_D_1_t1_re[62] = t1_re_62_2; + assign Direct_Lookup_Table_n_D_1_t1_re[63] = t1_re_63_2; + assign Direct_Lookup_Table_n_D_1_t1_re[64] = t1_re_64_2; + assign Direct_Lookup_Table_n_D_1_t1_re[65] = t1_re_65_2; + assign Direct_Lookup_Table_n_D_1_t1_re[66] = t1_re_66_2; + assign Direct_Lookup_Table_n_D_1_t1_re[67] = t1_re_67_2; + assign Direct_Lookup_Table_n_D_1_t1_re[68] = t1_re_68_2; + assign Direct_Lookup_Table_n_D_1_t1_re[69] = t1_re_69_2; + assign Direct_Lookup_Table_n_D_1_t1_re[70] = t1_re_70_2; + assign Direct_Lookup_Table_n_D_1_t1_re[71] = t1_re_71_2; + assign Direct_Lookup_Table_n_D_1_t1_re[72] = t1_re_72_2; + assign Direct_Lookup_Table_n_D_1_t1_re[73] = t1_re_73_2; + assign Direct_Lookup_Table_n_D_1_t1_re[74] = t1_re_74_2; + assign Direct_Lookup_Table_n_D_1_t1_re[75] = t1_re_75_2; + assign Direct_Lookup_Table_n_D_1_t1_re[76] = t1_re_76_2; + assign Direct_Lookup_Table_n_D_1_t1_re[77] = t1_re_77_2; + assign Direct_Lookup_Table_n_D_1_t1_re[78] = t1_re_78_2; + assign Direct_Lookup_Table_n_D_1_t1_re[79] = t1_re_79_2; + assign Direct_Lookup_Table_n_D_1_t1_re[80] = t1_re_80_2; + assign Direct_Lookup_Table_n_D_1_t1_re[81] = t1_re_81_2; + assign Direct_Lookup_Table_n_D_1_t1_re[82] = t1_re_82_2; + assign Direct_Lookup_Table_n_D_1_t1_re[83] = t1_re_83_2; + assign Direct_Lookup_Table_n_D_1_t1_re[84] = t1_re_84_2; + assign Direct_Lookup_Table_n_D_1_t1_re[85] = t1_re_85_2; + assign Direct_Lookup_Table_n_D_1_t1_re[86] = t1_re_86_2; + assign Direct_Lookup_Table_n_D_1_t1_re[87] = t1_re_87_2; + assign Direct_Lookup_Table_n_D_1_t1_re[88] = t1_re_88_2; + assign Direct_Lookup_Table_n_D_1_t1_re[89] = t1_re_89_2; + assign Direct_Lookup_Table_n_D_1_t1_re[90] = t1_re_90_2; + assign Direct_Lookup_Table_n_D_1_t1_re[91] = t1_re_91_2; + assign Direct_Lookup_Table_n_D_1_t1_re[92] = t1_re_92_2; + assign Direct_Lookup_Table_n_D_1_t1_re[93] = t1_re_93_2; + assign Direct_Lookup_Table_n_D_1_t1_re[94] = t1_re_94_2; + assign Direct_Lookup_Table_n_D_1_t1_re[95] = t1_re_95_2; + assign Direct_Lookup_Table_n_D_1_t1_re[96] = t1_re_96_2; + assign Direct_Lookup_Table_n_D_1_t1_re[97] = t1_re_97_2; + assign Direct_Lookup_Table_n_D_1_t1_re[98] = t1_re_98_2; + assign Direct_Lookup_Table_n_D_1_t1_re[99] = t1_re_99_2; + assign Direct_Lookup_Table_n_D_1_t1_re[100] = t1_re_100_2; + assign Direct_Lookup_Table_n_D_1_t1_re[101] = t1_re_101_2; + assign Direct_Lookup_Table_n_D_1_t1_re[102] = t1_re_102_2; + assign Direct_Lookup_Table_n_D_1_t1_re[103] = t1_re_103_2; + assign Direct_Lookup_Table_n_D_1_t1_re[104] = t1_re_104_2; + assign Direct_Lookup_Table_n_D_1_t1_re[105] = t1_re_105_2; + assign Direct_Lookup_Table_n_D_1_t1_re[106] = t1_re_106_2; + assign Direct_Lookup_Table_n_D_1_t1_re[107] = t1_re_107_2; + assign Direct_Lookup_Table_n_D_1_t1_re[108] = t1_re_108_2; + assign Direct_Lookup_Table_n_D_1_t1_re[109] = t1_re_109_2; + assign Direct_Lookup_Table_n_D_1_t1_re[110] = t1_re_110_2; + assign Direct_Lookup_Table_n_D_1_t1_re[111] = t1_re_111_2; + assign Direct_Lookup_Table_n_D_1_t1_re[112] = t1_re_112_2; + assign Direct_Lookup_Table_n_D_1_t1_re[113] = t1_re_113_2; + assign Direct_Lookup_Table_n_D_1_t1_re[114] = t1_re_114_2; + assign Direct_Lookup_Table_n_D_1_t1_re[115] = t1_re_115_2; + assign Direct_Lookup_Table_n_D_1_t1_re[116] = t1_re_116_2; + assign Direct_Lookup_Table_n_D_1_t1_re[117] = t1_re_117_2; + assign Direct_Lookup_Table_n_D_1_t1_re[118] = t1_re_118_2; + assign Direct_Lookup_Table_n_D_1_t1_re[119] = t1_re_119_2; + assign Direct_Lookup_Table_n_D_1_t1_re[120] = t1_re_120_2; + assign Direct_Lookup_Table_n_D_1_t1_re[121] = t1_re_121_2; + assign Direct_Lookup_Table_n_D_1_t1_re[122] = t1_re_122_2; + assign Direct_Lookup_Table_n_D_1_t1_re[123] = t1_re_123_2; + assign Direct_Lookup_Table_n_D_1_t1_re[124] = t1_re_124_2; + assign Direct_Lookup_Table_n_D_1_t1_re[125] = t1_re_125_2; + assign Direct_Lookup_Table_n_D_1_t1_re[126] = t1_re_126_2; + assign Direct_Lookup_Table_n_D_1_t1_re[127] = t1_re_127_2; + assign Direct_Lookup_Table_n_D_1_t1_re[128] = t1_re_128_2; + assign Direct_Lookup_Table_n_D_1_t1_re[129] = t1_re_129_2; + assign Direct_Lookup_Table_n_D_1_t1_re[130] = t1_re_130_2; + assign Direct_Lookup_Table_n_D_1_t1_re[131] = t1_re_131_2; + assign Direct_Lookup_Table_n_D_1_t1_re[132] = t1_re_132_2; + assign Direct_Lookup_Table_n_D_1_t1_re[133] = t1_re_133_2; + assign Direct_Lookup_Table_n_D_1_t1_re[134] = t1_re_134_2; + assign Direct_Lookup_Table_n_D_1_t1_re[135] = t1_re_135_2; + assign Direct_Lookup_Table_n_D_1_t1_re[136] = t1_re_136_2; + assign Direct_Lookup_Table_n_D_1_t1_re[137] = t1_re_137_2; + assign Direct_Lookup_Table_n_D_1_t1_re[138] = t1_re_138_2; + assign Direct_Lookup_Table_n_D_1_t1_re[139] = t1_re_139_2; + assign Direct_Lookup_Table_n_D_1_t1_re[140] = t1_re_140_2; + assign Direct_Lookup_Table_n_D_1_t1_re[141] = t1_re_141_2; + assign Direct_Lookup_Table_n_D_1_t1_re[142] = t1_re_142_2; + assign Direct_Lookup_Table_n_D_1_t1_re[143] = t1_re_143_2; + assign Direct_Lookup_Table_n_D_1_t1_re[144] = t1_re_144_2; + assign Direct_Lookup_Table_n_D_1_t1_re[145] = t1_re_145_2; + assign Direct_Lookup_Table_n_D_1_t1_re[146] = t1_re_146_2; + assign Direct_Lookup_Table_n_D_1_t1_re[147] = t1_re_147_2; + assign Direct_Lookup_Table_n_D_1_t1_re[148] = t1_re_148_2; + assign Direct_Lookup_Table_n_D_1_t1_re[149] = t1_re_149_2; + assign Direct_Lookup_Table_n_D_1_t1_re[150] = t1_re_150_2; + assign Direct_Lookup_Table_n_D_1_t1_re[151] = t1_re_151_2; + assign Direct_Lookup_Table_n_D_1_t1_re[152] = t1_re_152_2; + assign Direct_Lookup_Table_n_D_1_t1_re[153] = t1_re_153_2; + assign Direct_Lookup_Table_n_D_1_t1_re[154] = t1_re_154_2; + assign Direct_Lookup_Table_n_D_1_t1_re[155] = t1_re_155_2; + assign Direct_Lookup_Table_n_D_1_t1_re[156] = t1_re_156_2; + assign Direct_Lookup_Table_n_D_1_t1_re[157] = t1_re_157_2; + assign Direct_Lookup_Table_n_D_1_t1_re[158] = t1_re_158_2; + assign Direct_Lookup_Table_n_D_1_t1_re[159] = t1_re_159_2; + assign Direct_Lookup_Table_n_D_1_t1_re[160] = t1_re_160_2; + assign Direct_Lookup_Table_n_D_1_t1_re[161] = t1_re_161_2; + assign Direct_Lookup_Table_n_D_1_t1_re[162] = t1_re_162_2; + assign Direct_Lookup_Table_n_D_1_t1_re[163] = t1_re_163_2; + assign Direct_Lookup_Table_n_D_1_t1_re[164] = t1_re_164_2; + assign Direct_Lookup_Table_n_D_1_t1_re[165] = t1_re_165_2; + assign Direct_Lookup_Table_n_D_1_t1_re[166] = t1_re_166_2; + assign Direct_Lookup_Table_n_D_1_t1_re[167] = t1_re_167_2; + assign Direct_Lookup_Table_n_D_1_t1_re[168] = t1_re_168_2; + assign Direct_Lookup_Table_n_D_1_t1_re[169] = t1_re_169_2; + assign Direct_Lookup_Table_n_D_1_t1_re[170] = t1_re_170_2; + assign Direct_Lookup_Table_n_D_1_t1_re[171] = t1_re_171_2; + assign Direct_Lookup_Table_n_D_1_t1_re[172] = t1_re_172_2; + assign Direct_Lookup_Table_n_D_1_t1_re[173] = t1_re_173_2; + assign Direct_Lookup_Table_n_D_1_t1_re[174] = t1_re_174_2; + assign Direct_Lookup_Table_n_D_1_t1_re[175] = t1_re_175_2; + assign Direct_Lookup_Table_n_D_1_t1_re[176] = t1_re_176_2; + assign Direct_Lookup_Table_n_D_1_t1_re[177] = t1_re_177_2; + assign Direct_Lookup_Table_n_D_1_t1_re[178] = t1_re_178_2; + assign Direct_Lookup_Table_n_D_1_t1_re[179] = t1_re_179_2; + assign Direct_Lookup_Table_n_D_1_t1_re[180] = t1_re_180_2; + assign Direct_Lookup_Table_n_D_1_t1_re[181] = t1_re_181_2; + assign Direct_Lookup_Table_n_D_1_t1_re[182] = t1_re_182_2; + assign Direct_Lookup_Table_n_D_1_t1_re[183] = t1_re_183_2; + assign Direct_Lookup_Table_n_D_1_t1_re[184] = t1_re_184_2; + assign Direct_Lookup_Table_n_D_1_t1_re[185] = t1_re_185_2; + assign Direct_Lookup_Table_n_D_1_t1_re[186] = t1_re_186_2; + assign Direct_Lookup_Table_n_D_1_t1_re[187] = t1_re_187_2; + assign Direct_Lookup_Table_n_D_1_t1_re[188] = t1_re_188_2; + assign Direct_Lookup_Table_n_D_1_t1_re[189] = t1_re_189_2; + assign Direct_Lookup_Table_n_D_1_t1_re[190] = t1_re_190_2; + assign Direct_Lookup_Table_n_D_1_t1_re[191] = t1_re_191_2; + assign Direct_Lookup_Table_n_D_1_t1_re[192] = t1_re_192_2; + assign Direct_Lookup_Table_n_D_1_t1_re[193] = t1_re_193_2; + assign Direct_Lookup_Table_n_D_1_t1_re[194] = t1_re_194_2; + assign Direct_Lookup_Table_n_D_1_t1_re[195] = t1_re_195_2; + assign Direct_Lookup_Table_n_D_1_t1_re[196] = t1_re_196_2; + assign Direct_Lookup_Table_n_D_1_t1_re[197] = t1_re_197_2; + assign Direct_Lookup_Table_n_D_1_t1_re[198] = t1_re_198_2; + assign Direct_Lookup_Table_n_D_1_t1_re[199] = t1_re_199_2; + assign Direct_Lookup_Table_n_D_1_t1_re[200] = t1_re_200_2; + assign Direct_Lookup_Table_n_D_1_t1_re[201] = t1_re_201_2; + assign Direct_Lookup_Table_n_D_1_t1_re[202] = t1_re_202_2; + assign Direct_Lookup_Table_n_D_1_t1_re[203] = t1_re_203_2; + assign Direct_Lookup_Table_n_D_1_t1_re[204] = t1_re_204_2; + assign Direct_Lookup_Table_n_D_1_t1_re[205] = t1_re_205_2; + assign Direct_Lookup_Table_n_D_1_t1_re[206] = t1_re_206_2; + assign Direct_Lookup_Table_n_D_1_t1_re[207] = t1_re_207_2; + assign Direct_Lookup_Table_n_D_1_t1_re[208] = t1_re_208_2; + assign Direct_Lookup_Table_n_D_1_t1_re[209] = t1_re_209_2; + assign Direct_Lookup_Table_n_D_1_t1_re[210] = t1_re_210_2; + assign Direct_Lookup_Table_n_D_1_t1_re[211] = t1_re_211_2; + assign Direct_Lookup_Table_n_D_1_t1_re[212] = t1_re_212_2; + assign Direct_Lookup_Table_n_D_1_t1_re[213] = t1_re_213_2; + assign Direct_Lookup_Table_n_D_1_t1_re[214] = t1_re_214_2; + assign Direct_Lookup_Table_n_D_1_t1_re[215] = t1_re_215_2; + assign Direct_Lookup_Table_n_D_1_t1_re[216] = t1_re_216_2; + assign Direct_Lookup_Table_n_D_1_t1_re[217] = t1_re_217_2; + assign Direct_Lookup_Table_n_D_1_t1_re[218] = t1_re_218_2; + assign Direct_Lookup_Table_n_D_1_t1_re[219] = t1_re_219_2; + assign Direct_Lookup_Table_n_D_1_t1_re[220] = t1_re_220_2; + assign Direct_Lookup_Table_n_D_1_t1_re[221] = t1_re_221_2; + assign Direct_Lookup_Table_n_D_1_t1_re[222] = t1_re_222_2; + assign Direct_Lookup_Table_n_D_1_t1_re[223] = t1_re_223_2; + assign Direct_Lookup_Table_n_D_1_t1_re[224] = t1_re_224_2; + assign Direct_Lookup_Table_n_D_1_t1_re[225] = t1_re_225_2; + assign Direct_Lookup_Table_n_D_1_t1_re[226] = t1_re_226_2; + assign Direct_Lookup_Table_n_D_1_t1_re[227] = t1_re_227_2; + assign Direct_Lookup_Table_n_D_1_t1_re[228] = t1_re_228_2; + assign Direct_Lookup_Table_n_D_1_t1_re[229] = t1_re_229_2; + assign Direct_Lookup_Table_n_D_1_t1_re[230] = t1_re_230_2; + assign Direct_Lookup_Table_n_D_1_t1_re[231] = t1_re_231_2; + assign Direct_Lookup_Table_n_D_1_t1_re[232] = t1_re_232_2; + assign Direct_Lookup_Table_n_D_1_t1_re[233] = t1_re_233_2; + assign Direct_Lookup_Table_n_D_1_t1_re[234] = t1_re_234_2; + assign Direct_Lookup_Table_n_D_1_t1_re[235] = t1_re_235_2; + assign Direct_Lookup_Table_n_D_1_t1_re[236] = t1_re_236_2; + assign Direct_Lookup_Table_n_D_1_t1_re[237] = t1_re_237_2; + assign Direct_Lookup_Table_n_D_1_t1_re[238] = t1_re_238_2; + assign Direct_Lookup_Table_n_D_1_t1_re[239] = t1_re_239_2; + assign Direct_Lookup_Table_n_D_1_t1_re[240] = t1_re_240_2; + assign Direct_Lookup_Table_n_D_1_t1_re[241] = t1_re_241_2; + assign Direct_Lookup_Table_n_D_1_t1_re[242] = t1_re_242_2; + assign Direct_Lookup_Table_n_D_1_t1_re[243] = t1_re_243_2; + assign Direct_Lookup_Table_n_D_1_t1_re[244] = t1_re_244_2; + assign Direct_Lookup_Table_n_D_1_t1_re[245] = t1_re_245_2; + assign Direct_Lookup_Table_n_D_1_t1_re[246] = t1_re_246_2; + assign Direct_Lookup_Table_n_D_1_t1_re[247] = t1_re_247_2; + assign Direct_Lookup_Table_n_D_1_t1_re[248] = t1_re_248_2; + assign Direct_Lookup_Table_n_D_1_t1_re[249] = t1_re_249_2; + assign Direct_Lookup_Table_n_D_1_t1_re[250] = t1_re_250_2; + assign Direct_Lookup_Table_n_D_1_t1_re[251] = t1_re_251_2; + assign Direct_Lookup_Table_n_D_1_t1_re[252] = t1_re_252_2; + assign Direct_Lookup_Table_n_D_1_t1_re[253] = t1_re_253_2; + assign Direct_Lookup_Table_n_D_1_t1_re[254] = t1_re_254_2; + assign Direct_Lookup_Table_n_D_1_t1_re[255] = t1_re_255_2; + assign Direct_Lookup_Table_n_D_1_t1_re[256] = t1_re_256_2; + assign Direct_Lookup_Table_n_D_1_t1_re[257] = t1_re_257_2; + assign Direct_Lookup_Table_n_D_1_t1_re[258] = t1_re_258_2; + assign Direct_Lookup_Table_n_D_1_t1_re[259] = t1_re_259_2; + assign Direct_Lookup_Table_n_D_1_t1_re[260] = t1_re_260_2; + assign Direct_Lookup_Table_n_D_1_t1_re[261] = t1_re_261_2; + assign Direct_Lookup_Table_n_D_1_t1_re[262] = t1_re_262_2; + assign Direct_Lookup_Table_n_D_1_t1_re[263] = t1_re_263_2; + assign Direct_Lookup_Table_n_D_1_t1_re[264] = t1_re_264_2; + assign Direct_Lookup_Table_n_D_1_t1_re[265] = t1_re_265_2; + assign Direct_Lookup_Table_n_D_1_t1_re[266] = t1_re_266_2; + assign Direct_Lookup_Table_n_D_1_t1_re[267] = t1_re_267_2; + assign Direct_Lookup_Table_n_D_1_t1_re[268] = t1_re_268_2; + assign Direct_Lookup_Table_n_D_1_t1_re[269] = t1_re_269_2; + assign Direct_Lookup_Table_n_D_1_t1_re[270] = t1_re_270_2; + assign Direct_Lookup_Table_n_D_1_t1_re[271] = t1_re_271_2; + assign Direct_Lookup_Table_n_D_1_t1_re[272] = t1_re_272_2; + assign Direct_Lookup_Table_n_D_1_t1_re[273] = t1_re_273_2; + assign Direct_Lookup_Table_n_D_1_t1_re[274] = t1_re_274_2; + assign Direct_Lookup_Table_n_D_1_t1_re[275] = t1_re_275_2; + assign Direct_Lookup_Table_n_D_1_t1_re[276] = t1_re_276_2; + assign Direct_Lookup_Table_n_D_1_t1_re[277] = t1_re_277_2; + assign Direct_Lookup_Table_n_D_1_t1_re[278] = t1_re_278_2; + assign Direct_Lookup_Table_n_D_1_t1_re[279] = t1_re_279_2; + assign Direct_Lookup_Table_n_D_1_t1_re[280] = t1_re_280_2; + assign Direct_Lookup_Table_n_D_1_t1_re[281] = t1_re_281_2; + assign Direct_Lookup_Table_n_D_1_t1_re[282] = t1_re_282_2; + assign Direct_Lookup_Table_n_D_1_t1_re[283] = t1_re_283_2; + assign Direct_Lookup_Table_n_D_1_t1_re[284] = t1_re_284_2; + assign Direct_Lookup_Table_n_D_1_t1_re[285] = t1_re_285_2; + assign Direct_Lookup_Table_n_D_1_t1_re[286] = t1_re_286_2; + assign Direct_Lookup_Table_n_D_1_t1_re[287] = t1_re_287_2; + assign Direct_Lookup_Table_n_D_1_t1_re[288] = t1_re_288_2; + assign Direct_Lookup_Table_n_D_1_t1_re[289] = t1_re_289_2; + assign Direct_Lookup_Table_n_D_1_t1_re[290] = t1_re_290_2; + assign Direct_Lookup_Table_n_D_1_t1_re[291] = t1_re_291_2; + assign Direct_Lookup_Table_n_D_1_t1_re[292] = t1_re_292_2; + assign Direct_Lookup_Table_n_D_1_t1_re[293] = t1_re_293_2; + assign Direct_Lookup_Table_n_D_1_t1_re[294] = t1_re_294_2; + assign Direct_Lookup_Table_n_D_1_t1_re[295] = t1_re_295_2; + assign Direct_Lookup_Table_n_D_1_t1_re[296] = t1_re_296_2; + assign Direct_Lookup_Table_n_D_1_t1_re[297] = t1_re_297_2; + assign Direct_Lookup_Table_n_D_1_t1_re[298] = t1_re_298_2; + assign Direct_Lookup_Table_n_D_1_t1_re[299] = t1_re_299_2; + assign Direct_Lookup_Table_n_D_1_t1_re[300] = t1_re_300_2; + assign Direct_Lookup_Table_n_D_1_t1_re[301] = t1_re_301_2; + assign Direct_Lookup_Table_n_D_1_t1_re[302] = t1_re_302_2; + assign Direct_Lookup_Table_n_D_1_t1_re[303] = t1_re_303_2; + assign Direct_Lookup_Table_n_D_1_t1_re[304] = t1_re_304_2; + assign Direct_Lookup_Table_n_D_1_t1_re[305] = t1_re_305_2; + assign Direct_Lookup_Table_n_D_1_t1_re[306] = t1_re_306_2; + assign Direct_Lookup_Table_n_D_1_t1_re[307] = t1_re_307_2; + assign Direct_Lookup_Table_n_D_1_t1_re[308] = t1_re_308_2; + assign Direct_Lookup_Table_n_D_1_t1_re[309] = t1_re_309_2; + assign Direct_Lookup_Table_n_D_1_t1_re[310] = t1_re_310_2; + assign Direct_Lookup_Table_n_D_1_t1_re[311] = t1_re_311_2; + assign Direct_Lookup_Table_n_D_1_t1_re[312] = t1_re_312_2; + assign Direct_Lookup_Table_n_D_1_t1_re[313] = t1_re_313_2; + assign Direct_Lookup_Table_n_D_1_t1_re[314] = t1_re_314_2; + assign Direct_Lookup_Table_n_D_1_t1_re[315] = t1_re_315_2; + assign Direct_Lookup_Table_n_D_1_t1_re[316] = t1_re_316_2; + assign Direct_Lookup_Table_n_D_1_t1_re[317] = t1_re_317_2; + assign Direct_Lookup_Table_n_D_1_t1_re[318] = t1_re_318_2; + assign Direct_Lookup_Table_n_D_1_t1_re[319] = t1_re_319_2; + assign Direct_Lookup_Table_n_D_1_t1_re[320] = t1_re_320_2; + assign Direct_Lookup_Table_n_D_1_t1_re[321] = t1_re_321_2; + assign Direct_Lookup_Table_n_D_1_t1_re[322] = t1_re_322_2; + assign Direct_Lookup_Table_n_D_1_t1_re[323] = t1_re_323_2; + assign Direct_Lookup_Table_n_D_1_t1_re[324] = t1_re_324_2; + assign Direct_Lookup_Table_n_D_1_t1_re[325] = t1_re_325_2; + assign Direct_Lookup_Table_n_D_1_t1_re[326] = t1_re_326_2; + assign Direct_Lookup_Table_n_D_1_t1_re[327] = t1_re_327_2; + assign Direct_Lookup_Table_n_D_1_t1_re[328] = t1_re_328_2; + assign Direct_Lookup_Table_n_D_1_t1_re[329] = t1_re_329_2; + assign Direct_Lookup_Table_n_D_1_t1_re[330] = t1_re_330_2; + assign Direct_Lookup_Table_n_D_1_t1_re[331] = t1_re_331_2; + assign Direct_Lookup_Table_n_D_1_t1_re[332] = t1_re_332_2; + assign Direct_Lookup_Table_n_D_1_t1_re[333] = t1_re_333_2; + assign Direct_Lookup_Table_n_D_1_t1_re[334] = t1_re_334_2; + assign Direct_Lookup_Table_n_D_1_t1_re[335] = t1_re_335_2; + assign Direct_Lookup_Table_n_D_1_t1_re[336] = t1_re_336_2; + assign Direct_Lookup_Table_n_D_1_t1_re[337] = t1_re_337_2; + assign Direct_Lookup_Table_n_D_1_t1_re[338] = t1_re_338_2; + assign Direct_Lookup_Table_n_D_1_t1_re[339] = t1_re_339_2; + assign Direct_Lookup_Table_n_D_1_t1_re[340] = t1_re_340_2; + assign Direct_Lookup_Table_n_D_1_t1_re[341] = t1_re_341_2; + assign Direct_Lookup_Table_n_D_1_t1_re[342] = t1_re_342_2; + assign Direct_Lookup_Table_n_D_1_t1_re[343] = t1_re_343_2; + assign Direct_Lookup_Table_n_D_1_t1_re[344] = t1_re_344_2; + assign Direct_Lookup_Table_n_D_1_t1_re[345] = t1_re_345_2; + assign Direct_Lookup_Table_n_D_1_t1_re[346] = t1_re_346_2; + assign Direct_Lookup_Table_n_D_1_t1_re[347] = t1_re_347_2; + assign Direct_Lookup_Table_n_D_1_t1_re[348] = t1_re_348_2; + assign Direct_Lookup_Table_n_D_1_t1_re[349] = t1_re_349_2; + assign Direct_Lookup_Table_n_D_1_t1_re[350] = t1_re_350_2; + assign Direct_Lookup_Table_n_D_1_t1_re[351] = t1_re_351_2; + assign Direct_Lookup_Table_n_D_1_t1_re[352] = t1_re_352_2; + assign Direct_Lookup_Table_n_D_1_t1_re[353] = t1_re_353_2; + assign Direct_Lookup_Table_n_D_1_t1_re[354] = t1_re_354_2; + assign Direct_Lookup_Table_n_D_1_t1_re[355] = t1_re_355_2; + assign Direct_Lookup_Table_n_D_1_t1_re[356] = t1_re_356_2; + assign Direct_Lookup_Table_n_D_1_t1_re[357] = t1_re_357_2; + assign Direct_Lookup_Table_n_D_1_t1_re[358] = t1_re_358_2; + assign Direct_Lookup_Table_n_D_1_t1_re[359] = t1_re_359_2; + assign Direct_Lookup_Table_n_D_1_t1_re[360] = t1_re_360_2; + assign Direct_Lookup_Table_n_D_1_t1_re[361] = t1_re_361_2; + assign Direct_Lookup_Table_n_D_1_t1_re[362] = t1_re_362_2; + assign Direct_Lookup_Table_n_D_1_t1_re[363] = t1_re_363_2; + assign Direct_Lookup_Table_n_D_1_t1_re[364] = t1_re_364_2; + assign Direct_Lookup_Table_n_D_1_t1_re[365] = t1_re_365_2; + assign Direct_Lookup_Table_n_D_1_t1_re[366] = t1_re_366_2; + assign Direct_Lookup_Table_n_D_1_t1_re[367] = t1_re_367_2; + assign Direct_Lookup_Table_n_D_1_t1_re[368] = t1_re_368_2; + assign Direct_Lookup_Table_n_D_1_t1_re[369] = t1_re_369_2; + assign Direct_Lookup_Table_n_D_1_t1_re[370] = t1_re_370_2; + assign Direct_Lookup_Table_n_D_1_t1_re[371] = t1_re_371_2; + assign Direct_Lookup_Table_n_D_1_t1_re[372] = t1_re_372_2; + assign Direct_Lookup_Table_n_D_1_t1_re[373] = t1_re_373_2; + assign Direct_Lookup_Table_n_D_1_t1_re[374] = t1_re_374_2; + assign Direct_Lookup_Table_n_D_1_t1_re[375] = t1_re_375_2; + assign Direct_Lookup_Table_n_D_1_t1_re[376] = t1_re_376_2; + assign Direct_Lookup_Table_n_D_1_t1_re[377] = t1_re_377_2; + assign Direct_Lookup_Table_n_D_1_t1_re[378] = t1_re_378_2; + assign Direct_Lookup_Table_n_D_1_t1_re[379] = t1_re_379_2; + assign Direct_Lookup_Table_n_D_1_t1_re[380] = t1_re_380_2; + assign Direct_Lookup_Table_n_D_1_t1_re[381] = t1_re_381_2; + assign Direct_Lookup_Table_n_D_1_t1_re[382] = t1_re_382_2; + assign Direct_Lookup_Table_n_D_1_t1_re[383] = t1_re_383_2; + assign Direct_Lookup_Table_n_D_1_t1_re[384] = t1_re_384_2; + assign Direct_Lookup_Table_n_D_1_t1_re[385] = t1_re_385_2; + assign Direct_Lookup_Table_n_D_1_t1_re[386] = t1_re_386_2; + assign Direct_Lookup_Table_n_D_1_t1_re[387] = t1_re_387_2; + assign Direct_Lookup_Table_n_D_1_t1_re[388] = t1_re_388_2; + assign Direct_Lookup_Table_n_D_1_t1_re[389] = t1_re_389_2; + assign Direct_Lookup_Table_n_D_1_t1_re[390] = t1_re_390_2; + assign Direct_Lookup_Table_n_D_1_t1_re[391] = t1_re_391_2; + assign Direct_Lookup_Table_n_D_1_t1_re[392] = t1_re_392_2; + assign Direct_Lookup_Table_n_D_1_t1_re[393] = t1_re_393_2; + assign Direct_Lookup_Table_n_D_1_t1_re[394] = t1_re_394_2; + assign Direct_Lookup_Table_n_D_1_t1_re[395] = t1_re_395_2; + assign Direct_Lookup_Table_n_D_1_t1_re[396] = t1_re_396_2; + assign Direct_Lookup_Table_n_D_1_t1_re[397] = t1_re_397_2; + assign Direct_Lookup_Table_n_D_1_t1_re[398] = t1_re_398_2; + assign Direct_Lookup_Table_n_D_1_t1_re[399] = t1_re_399_2; + assign Direct_Lookup_Table_n_D_1_t1_re[400] = t1_re_400_2; + assign Direct_Lookup_Table_n_D_1_t1_re[401] = t1_re_401_2; + assign Direct_Lookup_Table_n_D_1_t1_re[402] = t1_re_402_2; + assign Direct_Lookup_Table_n_D_1_t1_re[403] = t1_re_403_2; + assign Direct_Lookup_Table_n_D_1_t1_re[404] = t1_re_404_2; + assign Direct_Lookup_Table_n_D_1_t1_re[405] = t1_re_405_2; + assign Direct_Lookup_Table_n_D_1_t1_re[406] = t1_re_406_2; + assign Direct_Lookup_Table_n_D_1_t1_re[407] = t1_re_407_2; + assign Direct_Lookup_Table_n_D_1_t1_re[408] = t1_re_408_2; + assign Direct_Lookup_Table_n_D_1_t1_re[409] = t1_re_409_2; + assign Direct_Lookup_Table_n_D_1_t1_re[410] = t1_re_410_2; + assign Direct_Lookup_Table_n_D_1_t1_re[411] = t1_re_411_2; + assign Direct_Lookup_Table_n_D_1_t1_re[412] = t1_re_412_2; + assign Direct_Lookup_Table_n_D_1_t1_re[413] = t1_re_413_2; + assign Direct_Lookup_Table_n_D_1_t1_re[414] = t1_re_414_2; + assign Direct_Lookup_Table_n_D_1_t1_re[415] = t1_re_415_2; + assign Direct_Lookup_Table_n_D_1_t1_re[416] = t1_re_416_2; + assign Direct_Lookup_Table_n_D_1_t1_re[417] = t1_re_417_2; + assign Direct_Lookup_Table_n_D_1_t1_re[418] = t1_re_418_2; + assign Direct_Lookup_Table_n_D_1_t1_re[419] = t1_re_419_2; + assign Direct_Lookup_Table_n_D_1_t1_re[420] = t1_re_420_2; + assign Direct_Lookup_Table_n_D_1_t1_re[421] = t1_re_421_2; + assign Direct_Lookup_Table_n_D_1_t1_re[422] = t1_re_422_2; + assign Direct_Lookup_Table_n_D_1_t1_re[423] = t1_re_423_2; + assign Direct_Lookup_Table_n_D_1_t1_re[424] = t1_re_424_2; + assign Direct_Lookup_Table_n_D_1_t1_re[425] = t1_re_425_2; + assign Direct_Lookup_Table_n_D_1_t1_re[426] = t1_re_426_2; + assign Direct_Lookup_Table_n_D_1_t1_re[427] = t1_re_427_2; + assign Direct_Lookup_Table_n_D_1_t1_re[428] = t1_re_428_2; + assign Direct_Lookup_Table_n_D_1_t1_re[429] = t1_re_429_2; + assign Direct_Lookup_Table_n_D_1_t1_re[430] = t1_re_430_2; + assign Direct_Lookup_Table_n_D_1_t1_re[431] = t1_re_431_2; + assign Direct_Lookup_Table_n_D_1_t1_re[432] = t1_re_432_2; + assign Direct_Lookup_Table_n_D_1_t1_re[433] = t1_re_433_2; + assign Direct_Lookup_Table_n_D_1_t1_re[434] = t1_re_434_2; + assign Direct_Lookup_Table_n_D_1_t1_re[435] = t1_re_435_2; + assign Direct_Lookup_Table_n_D_1_t1_re[436] = t1_re_436_2; + assign Direct_Lookup_Table_n_D_1_t1_re[437] = t1_re_437_2; + assign Direct_Lookup_Table_n_D_1_t1_re[438] = t1_re_438_2; + assign Direct_Lookup_Table_n_D_1_t1_re[439] = t1_re_439_2; + assign Direct_Lookup_Table_n_D_1_t1_re[440] = t1_re_440_2; + assign Direct_Lookup_Table_n_D_1_t1_re[441] = t1_re_441_2; + assign Direct_Lookup_Table_n_D_1_t1_re[442] = t1_re_442_2; + assign Direct_Lookup_Table_n_D_1_t1_re[443] = t1_re_443_2; + assign Direct_Lookup_Table_n_D_1_t1_re[444] = t1_re_444_2; + assign Direct_Lookup_Table_n_D_1_t1_re[445] = t1_re_445_2; + assign Direct_Lookup_Table_n_D_1_t1_re[446] = t1_re_446_2; + assign Direct_Lookup_Table_n_D_1_t1_re[447] = t1_re_447_2; + assign Direct_Lookup_Table_n_D_1_t1_re[448] = t1_re_448_2; + assign Direct_Lookup_Table_n_D_1_t1_re[449] = t1_re_449_2; + assign Direct_Lookup_Table_n_D_1_t1_re[450] = t1_re_450_2; + assign Direct_Lookup_Table_n_D_1_t1_re[451] = t1_re_451_2; + assign Direct_Lookup_Table_n_D_1_t1_re[452] = t1_re_452_2; + assign Direct_Lookup_Table_n_D_1_t1_re[453] = t1_re_453_2; + assign Direct_Lookup_Table_n_D_1_t1_re[454] = t1_re_454_2; + assign Direct_Lookup_Table_n_D_1_t1_re[455] = t1_re_455_2; + assign Direct_Lookup_Table_n_D_1_t1_re[456] = t1_re_456_2; + assign Direct_Lookup_Table_n_D_1_t1_re[457] = t1_re_457_2; + assign Direct_Lookup_Table_n_D_1_t1_re[458] = t1_re_458_2; + assign Direct_Lookup_Table_n_D_1_t1_re[459] = t1_re_459_2; + assign Direct_Lookup_Table_n_D_1_t1_re[460] = t1_re_460_2; + assign Direct_Lookup_Table_n_D_1_t1_re[461] = t1_re_461_2; + assign Direct_Lookup_Table_n_D_1_t1_re[462] = t1_re_462_2; + assign Direct_Lookup_Table_n_D_1_t1_re[463] = t1_re_463_2; + assign Direct_Lookup_Table_n_D_1_t1_re[464] = t1_re_464_2; + assign Direct_Lookup_Table_n_D_1_t1_re[465] = t1_re_465_2; + assign Direct_Lookup_Table_n_D_1_t1_re[466] = t1_re_466_2; + assign Direct_Lookup_Table_n_D_1_t1_re[467] = t1_re_467_2; + assign Direct_Lookup_Table_n_D_1_t1_re[468] = t1_re_468_2; + assign Direct_Lookup_Table_n_D_1_t1_re[469] = t1_re_469_2; + assign Direct_Lookup_Table_n_D_1_t1_re[470] = t1_re_470_2; + assign Direct_Lookup_Table_n_D_1_t1_re[471] = t1_re_471_2; + assign Direct_Lookup_Table_n_D_1_t1_re[472] = t1_re_472_2; + assign Direct_Lookup_Table_n_D_1_t1_re[473] = t1_re_473_2; + assign Direct_Lookup_Table_n_D_1_t1_re[474] = t1_re_474_2; + assign Direct_Lookup_Table_n_D_1_t1_re[475] = t1_re_475_2; + assign Direct_Lookup_Table_n_D_1_t1_re[476] = t1_re_476_2; + assign Direct_Lookup_Table_n_D_1_t1_re[477] = t1_re_477_2; + assign Direct_Lookup_Table_n_D_1_t1_re[478] = t1_re_478_2; + assign Direct_Lookup_Table_n_D_1_t1_re[479] = t1_re_479_2; + assign Direct_Lookup_Table_n_D_1_t1_re[480] = t1_re_480_2; + assign Direct_Lookup_Table_n_D_1_t1_re[481] = t1_re_481_2; + assign Direct_Lookup_Table_n_D_1_t1_re[482] = t1_re_482_2; + assign Direct_Lookup_Table_n_D_1_t1_re[483] = t1_re_483_2; + assign Direct_Lookup_Table_n_D_1_t1_re[484] = t1_re_484_2; + assign Direct_Lookup_Table_n_D_1_t1_re[485] = t1_re_485_2; + assign Direct_Lookup_Table_n_D_1_t1_re[486] = t1_re_486_2; + assign Direct_Lookup_Table_n_D_1_t1_re[487] = t1_re_487_2; + assign Direct_Lookup_Table_n_D_1_t1_re[488] = t1_re_488_2; + assign Direct_Lookup_Table_n_D_1_t1_re[489] = t1_re_489_2; + assign Direct_Lookup_Table_n_D_1_t1_re[490] = t1_re_490_2; + assign Direct_Lookup_Table_n_D_1_t1_re[491] = t1_re_491_2; + assign Direct_Lookup_Table_n_D_1_t1_re[492] = t1_re_492_2; + assign Direct_Lookup_Table_n_D_1_t1_re[493] = t1_re_493_2; + assign Direct_Lookup_Table_n_D_1_t1_re[494] = t1_re_494_2; + assign Direct_Lookup_Table_n_D_1_t1_re[495] = t1_re_495_2; + assign Direct_Lookup_Table_n_D_1_t1_re[496] = t1_re_496_2; + assign Direct_Lookup_Table_n_D_1_t1_re[497] = t1_re_497_2; + assign Direct_Lookup_Table_n_D_1_t1_re[498] = t1_re_498_2; + assign Direct_Lookup_Table_n_D_1_t1_re[499] = t1_re_499_2; + assign Direct_Lookup_Table_n_D_1_t1_re[500] = t1_re_500_2; + assign Direct_Lookup_Table_n_D_1_t1_re[501] = t1_re_501_2; + assign Direct_Lookup_Table_n_D_1_t1_re[502] = t1_re_502_2; + assign Direct_Lookup_Table_n_D_1_t1_re[503] = t1_re_503_2; + assign Direct_Lookup_Table_n_D_1_t1_re[504] = t1_re_504_2; + assign Direct_Lookup_Table_n_D_1_t1_re[505] = t1_re_505_2; + assign Direct_Lookup_Table_n_D_1_t1_re[506] = t1_re_506_2; + assign Direct_Lookup_Table_n_D_1_t1_re[507] = t1_re_507_2; + assign Direct_Lookup_Table_n_D_1_t1_re[508] = t1_re_508_2; + assign Direct_Lookup_Table_n_D_1_t1_re[509] = t1_re_509_2; + assign Direct_Lookup_Table_n_D_1_t1_re[510] = t1_re_510_2; + assign Direct_Lookup_Table_n_D_1_t1_re[511] = t1_re_511_2; + assign Direct_Lookup_Table_n_D_1_t1_im[0] = t1_im_0_2; + assign Direct_Lookup_Table_n_D_1_t1_im[1] = t1_im_1_2; + assign Direct_Lookup_Table_n_D_1_t1_im[2] = t1_im_2_2; + assign Direct_Lookup_Table_n_D_1_t1_im[3] = t1_im_3_2; + assign Direct_Lookup_Table_n_D_1_t1_im[4] = t1_im_4_2; + assign Direct_Lookup_Table_n_D_1_t1_im[5] = t1_im_5_2; + assign Direct_Lookup_Table_n_D_1_t1_im[6] = t1_im_6_2; + assign Direct_Lookup_Table_n_D_1_t1_im[7] = t1_im_7_2; + assign Direct_Lookup_Table_n_D_1_t1_im[8] = t1_im_8_2; + assign Direct_Lookup_Table_n_D_1_t1_im[9] = t1_im_9_2; + assign Direct_Lookup_Table_n_D_1_t1_im[10] = t1_im_10_2; + assign Direct_Lookup_Table_n_D_1_t1_im[11] = t1_im_11_2; + assign Direct_Lookup_Table_n_D_1_t1_im[12] = t1_im_12_2; + assign Direct_Lookup_Table_n_D_1_t1_im[13] = t1_im_13_2; + assign Direct_Lookup_Table_n_D_1_t1_im[14] = t1_im_14_2; + assign Direct_Lookup_Table_n_D_1_t1_im[15] = t1_im_15_2; + assign Direct_Lookup_Table_n_D_1_t1_im[16] = t1_im_16_2; + assign Direct_Lookup_Table_n_D_1_t1_im[17] = t1_im_17_2; + assign Direct_Lookup_Table_n_D_1_t1_im[18] = t1_im_18_2; + assign Direct_Lookup_Table_n_D_1_t1_im[19] = t1_im_19_2; + assign Direct_Lookup_Table_n_D_1_t1_im[20] = t1_im_20_2; + assign Direct_Lookup_Table_n_D_1_t1_im[21] = t1_im_21_2; + assign Direct_Lookup_Table_n_D_1_t1_im[22] = t1_im_22_2; + assign Direct_Lookup_Table_n_D_1_t1_im[23] = t1_im_23_2; + assign Direct_Lookup_Table_n_D_1_t1_im[24] = t1_im_24_2; + assign Direct_Lookup_Table_n_D_1_t1_im[25] = t1_im_25_2; + assign Direct_Lookup_Table_n_D_1_t1_im[26] = t1_im_26_2; + assign Direct_Lookup_Table_n_D_1_t1_im[27] = t1_im_27_2; + assign Direct_Lookup_Table_n_D_1_t1_im[28] = t1_im_28_2; + assign Direct_Lookup_Table_n_D_1_t1_im[29] = t1_im_29_2; + assign Direct_Lookup_Table_n_D_1_t1_im[30] = t1_im_30_2; + assign Direct_Lookup_Table_n_D_1_t1_im[31] = t1_im_31_2; + assign Direct_Lookup_Table_n_D_1_t1_im[32] = t1_im_32_2; + assign Direct_Lookup_Table_n_D_1_t1_im[33] = t1_im_33_2; + assign Direct_Lookup_Table_n_D_1_t1_im[34] = t1_im_34_2; + assign Direct_Lookup_Table_n_D_1_t1_im[35] = t1_im_35_2; + assign Direct_Lookup_Table_n_D_1_t1_im[36] = t1_im_36_2; + assign Direct_Lookup_Table_n_D_1_t1_im[37] = t1_im_37_2; + assign Direct_Lookup_Table_n_D_1_t1_im[38] = t1_im_38_2; + assign Direct_Lookup_Table_n_D_1_t1_im[39] = t1_im_39_2; + assign Direct_Lookup_Table_n_D_1_t1_im[40] = t1_im_40_2; + assign Direct_Lookup_Table_n_D_1_t1_im[41] = t1_im_41_2; + assign Direct_Lookup_Table_n_D_1_t1_im[42] = t1_im_42_2; + assign Direct_Lookup_Table_n_D_1_t1_im[43] = t1_im_43_2; + assign Direct_Lookup_Table_n_D_1_t1_im[44] = t1_im_44_2; + assign Direct_Lookup_Table_n_D_1_t1_im[45] = t1_im_45_2; + assign Direct_Lookup_Table_n_D_1_t1_im[46] = t1_im_46_2; + assign Direct_Lookup_Table_n_D_1_t1_im[47] = t1_im_47_2; + assign Direct_Lookup_Table_n_D_1_t1_im[48] = t1_im_48_2; + assign Direct_Lookup_Table_n_D_1_t1_im[49] = t1_im_49_2; + assign Direct_Lookup_Table_n_D_1_t1_im[50] = t1_im_50_2; + assign Direct_Lookup_Table_n_D_1_t1_im[51] = t1_im_51_2; + assign Direct_Lookup_Table_n_D_1_t1_im[52] = t1_im_52_2; + assign Direct_Lookup_Table_n_D_1_t1_im[53] = t1_im_53_2; + assign Direct_Lookup_Table_n_D_1_t1_im[54] = t1_im_54_2; + assign Direct_Lookup_Table_n_D_1_t1_im[55] = t1_im_55_2; + assign Direct_Lookup_Table_n_D_1_t1_im[56] = t1_im_56_2; + assign Direct_Lookup_Table_n_D_1_t1_im[57] = t1_im_57_2; + assign Direct_Lookup_Table_n_D_1_t1_im[58] = t1_im_58_2; + assign Direct_Lookup_Table_n_D_1_t1_im[59] = t1_im_59_2; + assign Direct_Lookup_Table_n_D_1_t1_im[60] = t1_im_60_2; + assign Direct_Lookup_Table_n_D_1_t1_im[61] = t1_im_61_2; + assign Direct_Lookup_Table_n_D_1_t1_im[62] = t1_im_62_2; + assign Direct_Lookup_Table_n_D_1_t1_im[63] = t1_im_63_2; + assign Direct_Lookup_Table_n_D_1_t1_im[64] = t1_im_64_2; + assign Direct_Lookup_Table_n_D_1_t1_im[65] = t1_im_65_2; + assign Direct_Lookup_Table_n_D_1_t1_im[66] = t1_im_66_2; + assign Direct_Lookup_Table_n_D_1_t1_im[67] = t1_im_67_2; + assign Direct_Lookup_Table_n_D_1_t1_im[68] = t1_im_68_2; + assign Direct_Lookup_Table_n_D_1_t1_im[69] = t1_im_69_2; + assign Direct_Lookup_Table_n_D_1_t1_im[70] = t1_im_70_2; + assign Direct_Lookup_Table_n_D_1_t1_im[71] = t1_im_71_2; + assign Direct_Lookup_Table_n_D_1_t1_im[72] = t1_im_72_2; + assign Direct_Lookup_Table_n_D_1_t1_im[73] = t1_im_73_2; + assign Direct_Lookup_Table_n_D_1_t1_im[74] = t1_im_74_2; + assign Direct_Lookup_Table_n_D_1_t1_im[75] = t1_im_75_2; + assign Direct_Lookup_Table_n_D_1_t1_im[76] = t1_im_76_2; + assign Direct_Lookup_Table_n_D_1_t1_im[77] = t1_im_77_2; + assign Direct_Lookup_Table_n_D_1_t1_im[78] = t1_im_78_2; + assign Direct_Lookup_Table_n_D_1_t1_im[79] = t1_im_79_2; + assign Direct_Lookup_Table_n_D_1_t1_im[80] = t1_im_80_2; + assign Direct_Lookup_Table_n_D_1_t1_im[81] = t1_im_81_2; + assign Direct_Lookup_Table_n_D_1_t1_im[82] = t1_im_82_2; + assign Direct_Lookup_Table_n_D_1_t1_im[83] = t1_im_83_2; + assign Direct_Lookup_Table_n_D_1_t1_im[84] = t1_im_84_2; + assign Direct_Lookup_Table_n_D_1_t1_im[85] = t1_im_85_2; + assign Direct_Lookup_Table_n_D_1_t1_im[86] = t1_im_86_2; + assign Direct_Lookup_Table_n_D_1_t1_im[87] = t1_im_87_2; + assign Direct_Lookup_Table_n_D_1_t1_im[88] = t1_im_88_2; + assign Direct_Lookup_Table_n_D_1_t1_im[89] = t1_im_89_2; + assign Direct_Lookup_Table_n_D_1_t1_im[90] = t1_im_90_2; + assign Direct_Lookup_Table_n_D_1_t1_im[91] = t1_im_91_2; + assign Direct_Lookup_Table_n_D_1_t1_im[92] = t1_im_92_2; + assign Direct_Lookup_Table_n_D_1_t1_im[93] = t1_im_93_2; + assign Direct_Lookup_Table_n_D_1_t1_im[94] = t1_im_94_2; + assign Direct_Lookup_Table_n_D_1_t1_im[95] = t1_im_95_2; + assign Direct_Lookup_Table_n_D_1_t1_im[96] = t1_im_96_2; + assign Direct_Lookup_Table_n_D_1_t1_im[97] = t1_im_97_2; + assign Direct_Lookup_Table_n_D_1_t1_im[98] = t1_im_98_2; + assign Direct_Lookup_Table_n_D_1_t1_im[99] = t1_im_99_2; + assign Direct_Lookup_Table_n_D_1_t1_im[100] = t1_im_100_2; + assign Direct_Lookup_Table_n_D_1_t1_im[101] = t1_im_101_2; + assign Direct_Lookup_Table_n_D_1_t1_im[102] = t1_im_102_2; + assign Direct_Lookup_Table_n_D_1_t1_im[103] = t1_im_103_2; + assign Direct_Lookup_Table_n_D_1_t1_im[104] = t1_im_104_2; + assign Direct_Lookup_Table_n_D_1_t1_im[105] = t1_im_105_2; + assign Direct_Lookup_Table_n_D_1_t1_im[106] = t1_im_106_2; + assign Direct_Lookup_Table_n_D_1_t1_im[107] = t1_im_107_2; + assign Direct_Lookup_Table_n_D_1_t1_im[108] = t1_im_108_2; + assign Direct_Lookup_Table_n_D_1_t1_im[109] = t1_im_109_2; + assign Direct_Lookup_Table_n_D_1_t1_im[110] = t1_im_110_2; + assign Direct_Lookup_Table_n_D_1_t1_im[111] = t1_im_111_2; + assign Direct_Lookup_Table_n_D_1_t1_im[112] = t1_im_112_2; + assign Direct_Lookup_Table_n_D_1_t1_im[113] = t1_im_113_2; + assign Direct_Lookup_Table_n_D_1_t1_im[114] = t1_im_114_2; + assign Direct_Lookup_Table_n_D_1_t1_im[115] = t1_im_115_2; + assign Direct_Lookup_Table_n_D_1_t1_im[116] = t1_im_116_2; + assign Direct_Lookup_Table_n_D_1_t1_im[117] = t1_im_117_2; + assign Direct_Lookup_Table_n_D_1_t1_im[118] = t1_im_118_2; + assign Direct_Lookup_Table_n_D_1_t1_im[119] = t1_im_119_2; + assign Direct_Lookup_Table_n_D_1_t1_im[120] = t1_im_120_2; + assign Direct_Lookup_Table_n_D_1_t1_im[121] = t1_im_121_2; + assign Direct_Lookup_Table_n_D_1_t1_im[122] = t1_im_122_2; + assign Direct_Lookup_Table_n_D_1_t1_im[123] = t1_im_123_2; + assign Direct_Lookup_Table_n_D_1_t1_im[124] = t1_im_124_2; + assign Direct_Lookup_Table_n_D_1_t1_im[125] = t1_im_125_2; + assign Direct_Lookup_Table_n_D_1_t1_im[126] = t1_im_126_2; + assign Direct_Lookup_Table_n_D_1_t1_im[127] = t1_im_127_2; + assign Direct_Lookup_Table_n_D_1_t1_im[128] = t1_im_128_2; + assign Direct_Lookup_Table_n_D_1_t1_im[129] = t1_im_129_2; + assign Direct_Lookup_Table_n_D_1_t1_im[130] = t1_im_130_2; + assign Direct_Lookup_Table_n_D_1_t1_im[131] = t1_im_131_2; + assign Direct_Lookup_Table_n_D_1_t1_im[132] = t1_im_132_2; + assign Direct_Lookup_Table_n_D_1_t1_im[133] = t1_im_133_2; + assign Direct_Lookup_Table_n_D_1_t1_im[134] = t1_im_134_2; + assign Direct_Lookup_Table_n_D_1_t1_im[135] = t1_im_135_2; + assign Direct_Lookup_Table_n_D_1_t1_im[136] = t1_im_136_2; + assign Direct_Lookup_Table_n_D_1_t1_im[137] = t1_im_137_2; + assign Direct_Lookup_Table_n_D_1_t1_im[138] = t1_im_138_2; + assign Direct_Lookup_Table_n_D_1_t1_im[139] = t1_im_139_2; + assign Direct_Lookup_Table_n_D_1_t1_im[140] = t1_im_140_2; + assign Direct_Lookup_Table_n_D_1_t1_im[141] = t1_im_141_2; + assign Direct_Lookup_Table_n_D_1_t1_im[142] = t1_im_142_2; + assign Direct_Lookup_Table_n_D_1_t1_im[143] = t1_im_143_2; + assign Direct_Lookup_Table_n_D_1_t1_im[144] = t1_im_144_2; + assign Direct_Lookup_Table_n_D_1_t1_im[145] = t1_im_145_2; + assign Direct_Lookup_Table_n_D_1_t1_im[146] = t1_im_146_2; + assign Direct_Lookup_Table_n_D_1_t1_im[147] = t1_im_147_2; + assign Direct_Lookup_Table_n_D_1_t1_im[148] = t1_im_148_2; + assign Direct_Lookup_Table_n_D_1_t1_im[149] = t1_im_149_2; + assign Direct_Lookup_Table_n_D_1_t1_im[150] = t1_im_150_2; + assign Direct_Lookup_Table_n_D_1_t1_im[151] = t1_im_151_2; + assign Direct_Lookup_Table_n_D_1_t1_im[152] = t1_im_152_2; + assign Direct_Lookup_Table_n_D_1_t1_im[153] = t1_im_153_2; + assign Direct_Lookup_Table_n_D_1_t1_im[154] = t1_im_154_2; + assign Direct_Lookup_Table_n_D_1_t1_im[155] = t1_im_155_2; + assign Direct_Lookup_Table_n_D_1_t1_im[156] = t1_im_156_2; + assign Direct_Lookup_Table_n_D_1_t1_im[157] = t1_im_157_2; + assign Direct_Lookup_Table_n_D_1_t1_im[158] = t1_im_158_2; + assign Direct_Lookup_Table_n_D_1_t1_im[159] = t1_im_159_2; + assign Direct_Lookup_Table_n_D_1_t1_im[160] = t1_im_160_2; + assign Direct_Lookup_Table_n_D_1_t1_im[161] = t1_im_161_2; + assign Direct_Lookup_Table_n_D_1_t1_im[162] = t1_im_162_2; + assign Direct_Lookup_Table_n_D_1_t1_im[163] = t1_im_163_2; + assign Direct_Lookup_Table_n_D_1_t1_im[164] = t1_im_164_2; + assign Direct_Lookup_Table_n_D_1_t1_im[165] = t1_im_165_2; + assign Direct_Lookup_Table_n_D_1_t1_im[166] = t1_im_166_2; + assign Direct_Lookup_Table_n_D_1_t1_im[167] = t1_im_167_2; + assign Direct_Lookup_Table_n_D_1_t1_im[168] = t1_im_168_2; + assign Direct_Lookup_Table_n_D_1_t1_im[169] = t1_im_169_2; + assign Direct_Lookup_Table_n_D_1_t1_im[170] = t1_im_170_2; + assign Direct_Lookup_Table_n_D_1_t1_im[171] = t1_im_171_2; + assign Direct_Lookup_Table_n_D_1_t1_im[172] = t1_im_172_2; + assign Direct_Lookup_Table_n_D_1_t1_im[173] = t1_im_173_2; + assign Direct_Lookup_Table_n_D_1_t1_im[174] = t1_im_174_2; + assign Direct_Lookup_Table_n_D_1_t1_im[175] = t1_im_175_2; + assign Direct_Lookup_Table_n_D_1_t1_im[176] = t1_im_176_2; + assign Direct_Lookup_Table_n_D_1_t1_im[177] = t1_im_177_2; + assign Direct_Lookup_Table_n_D_1_t1_im[178] = t1_im_178_2; + assign Direct_Lookup_Table_n_D_1_t1_im[179] = t1_im_179_2; + assign Direct_Lookup_Table_n_D_1_t1_im[180] = t1_im_180_2; + assign Direct_Lookup_Table_n_D_1_t1_im[181] = t1_im_181_2; + assign Direct_Lookup_Table_n_D_1_t1_im[182] = t1_im_182_2; + assign Direct_Lookup_Table_n_D_1_t1_im[183] = t1_im_183_2; + assign Direct_Lookup_Table_n_D_1_t1_im[184] = t1_im_184_2; + assign Direct_Lookup_Table_n_D_1_t1_im[185] = t1_im_185_2; + assign Direct_Lookup_Table_n_D_1_t1_im[186] = t1_im_186_2; + assign Direct_Lookup_Table_n_D_1_t1_im[187] = t1_im_187_2; + assign Direct_Lookup_Table_n_D_1_t1_im[188] = t1_im_188_2; + assign Direct_Lookup_Table_n_D_1_t1_im[189] = t1_im_189_2; + assign Direct_Lookup_Table_n_D_1_t1_im[190] = t1_im_190_2; + assign Direct_Lookup_Table_n_D_1_t1_im[191] = t1_im_191_2; + assign Direct_Lookup_Table_n_D_1_t1_im[192] = t1_im_192_2; + assign Direct_Lookup_Table_n_D_1_t1_im[193] = t1_im_193_2; + assign Direct_Lookup_Table_n_D_1_t1_im[194] = t1_im_194_2; + assign Direct_Lookup_Table_n_D_1_t1_im[195] = t1_im_195_2; + assign Direct_Lookup_Table_n_D_1_t1_im[196] = t1_im_196_2; + assign Direct_Lookup_Table_n_D_1_t1_im[197] = t1_im_197_2; + assign Direct_Lookup_Table_n_D_1_t1_im[198] = t1_im_198_2; + assign Direct_Lookup_Table_n_D_1_t1_im[199] = t1_im_199_2; + assign Direct_Lookup_Table_n_D_1_t1_im[200] = t1_im_200_2; + assign Direct_Lookup_Table_n_D_1_t1_im[201] = t1_im_201_2; + assign Direct_Lookup_Table_n_D_1_t1_im[202] = t1_im_202_2; + assign Direct_Lookup_Table_n_D_1_t1_im[203] = t1_im_203_2; + assign Direct_Lookup_Table_n_D_1_t1_im[204] = t1_im_204_2; + assign Direct_Lookup_Table_n_D_1_t1_im[205] = t1_im_205_2; + assign Direct_Lookup_Table_n_D_1_t1_im[206] = t1_im_206_2; + assign Direct_Lookup_Table_n_D_1_t1_im[207] = t1_im_207_2; + assign Direct_Lookup_Table_n_D_1_t1_im[208] = t1_im_208_2; + assign Direct_Lookup_Table_n_D_1_t1_im[209] = t1_im_209_2; + assign Direct_Lookup_Table_n_D_1_t1_im[210] = t1_im_210_2; + assign Direct_Lookup_Table_n_D_1_t1_im[211] = t1_im_211_2; + assign Direct_Lookup_Table_n_D_1_t1_im[212] = t1_im_212_2; + assign Direct_Lookup_Table_n_D_1_t1_im[213] = t1_im_213_2; + assign Direct_Lookup_Table_n_D_1_t1_im[214] = t1_im_214_2; + assign Direct_Lookup_Table_n_D_1_t1_im[215] = t1_im_215_2; + assign Direct_Lookup_Table_n_D_1_t1_im[216] = t1_im_216_2; + assign Direct_Lookup_Table_n_D_1_t1_im[217] = t1_im_217_2; + assign Direct_Lookup_Table_n_D_1_t1_im[218] = t1_im_218_2; + assign Direct_Lookup_Table_n_D_1_t1_im[219] = t1_im_219_2; + assign Direct_Lookup_Table_n_D_1_t1_im[220] = t1_im_220_2; + assign Direct_Lookup_Table_n_D_1_t1_im[221] = t1_im_221_2; + assign Direct_Lookup_Table_n_D_1_t1_im[222] = t1_im_222_2; + assign Direct_Lookup_Table_n_D_1_t1_im[223] = t1_im_223_2; + assign Direct_Lookup_Table_n_D_1_t1_im[224] = t1_im_224_2; + assign Direct_Lookup_Table_n_D_1_t1_im[225] = t1_im_225_2; + assign Direct_Lookup_Table_n_D_1_t1_im[226] = t1_im_226_2; + assign Direct_Lookup_Table_n_D_1_t1_im[227] = t1_im_227_2; + assign Direct_Lookup_Table_n_D_1_t1_im[228] = t1_im_228_2; + assign Direct_Lookup_Table_n_D_1_t1_im[229] = t1_im_229_2; + assign Direct_Lookup_Table_n_D_1_t1_im[230] = t1_im_230_2; + assign Direct_Lookup_Table_n_D_1_t1_im[231] = t1_im_231_2; + assign Direct_Lookup_Table_n_D_1_t1_im[232] = t1_im_232_2; + assign Direct_Lookup_Table_n_D_1_t1_im[233] = t1_im_233_2; + assign Direct_Lookup_Table_n_D_1_t1_im[234] = t1_im_234_2; + assign Direct_Lookup_Table_n_D_1_t1_im[235] = t1_im_235_2; + assign Direct_Lookup_Table_n_D_1_t1_im[236] = t1_im_236_2; + assign Direct_Lookup_Table_n_D_1_t1_im[237] = t1_im_237_2; + assign Direct_Lookup_Table_n_D_1_t1_im[238] = t1_im_238_2; + assign Direct_Lookup_Table_n_D_1_t1_im[239] = t1_im_239_2; + assign Direct_Lookup_Table_n_D_1_t1_im[240] = t1_im_240_2; + assign Direct_Lookup_Table_n_D_1_t1_im[241] = t1_im_241_2; + assign Direct_Lookup_Table_n_D_1_t1_im[242] = t1_im_242_2; + assign Direct_Lookup_Table_n_D_1_t1_im[243] = t1_im_243_2; + assign Direct_Lookup_Table_n_D_1_t1_im[244] = t1_im_244_2; + assign Direct_Lookup_Table_n_D_1_t1_im[245] = t1_im_245_2; + assign Direct_Lookup_Table_n_D_1_t1_im[246] = t1_im_246_2; + assign Direct_Lookup_Table_n_D_1_t1_im[247] = t1_im_247_2; + assign Direct_Lookup_Table_n_D_1_t1_im[248] = t1_im_248_2; + assign Direct_Lookup_Table_n_D_1_t1_im[249] = t1_im_249_2; + assign Direct_Lookup_Table_n_D_1_t1_im[250] = t1_im_250_2; + assign Direct_Lookup_Table_n_D_1_t1_im[251] = t1_im_251_2; + assign Direct_Lookup_Table_n_D_1_t1_im[252] = t1_im_252_2; + assign Direct_Lookup_Table_n_D_1_t1_im[253] = t1_im_253_2; + assign Direct_Lookup_Table_n_D_1_t1_im[254] = t1_im_254_2; + assign Direct_Lookup_Table_n_D_1_t1_im[255] = t1_im_255_2; + assign Direct_Lookup_Table_n_D_1_t1_im[256] = t1_im_256_2; + assign Direct_Lookup_Table_n_D_1_t1_im[257] = t1_im_257_2; + assign Direct_Lookup_Table_n_D_1_t1_im[258] = t1_im_258_2; + assign Direct_Lookup_Table_n_D_1_t1_im[259] = t1_im_259_2; + assign Direct_Lookup_Table_n_D_1_t1_im[260] = t1_im_260_2; + assign Direct_Lookup_Table_n_D_1_t1_im[261] = t1_im_261_2; + assign Direct_Lookup_Table_n_D_1_t1_im[262] = t1_im_262_2; + assign Direct_Lookup_Table_n_D_1_t1_im[263] = t1_im_263_2; + assign Direct_Lookup_Table_n_D_1_t1_im[264] = t1_im_264_2; + assign Direct_Lookup_Table_n_D_1_t1_im[265] = t1_im_265_2; + assign Direct_Lookup_Table_n_D_1_t1_im[266] = t1_im_266_2; + assign Direct_Lookup_Table_n_D_1_t1_im[267] = t1_im_267_2; + assign Direct_Lookup_Table_n_D_1_t1_im[268] = t1_im_268_2; + assign Direct_Lookup_Table_n_D_1_t1_im[269] = t1_im_269_2; + assign Direct_Lookup_Table_n_D_1_t1_im[270] = t1_im_270_2; + assign Direct_Lookup_Table_n_D_1_t1_im[271] = t1_im_271_2; + assign Direct_Lookup_Table_n_D_1_t1_im[272] = t1_im_272_2; + assign Direct_Lookup_Table_n_D_1_t1_im[273] = t1_im_273_2; + assign Direct_Lookup_Table_n_D_1_t1_im[274] = t1_im_274_2; + assign Direct_Lookup_Table_n_D_1_t1_im[275] = t1_im_275_2; + assign Direct_Lookup_Table_n_D_1_t1_im[276] = t1_im_276_2; + assign Direct_Lookup_Table_n_D_1_t1_im[277] = t1_im_277_2; + assign Direct_Lookup_Table_n_D_1_t1_im[278] = t1_im_278_2; + assign Direct_Lookup_Table_n_D_1_t1_im[279] = t1_im_279_2; + assign Direct_Lookup_Table_n_D_1_t1_im[280] = t1_im_280_2; + assign Direct_Lookup_Table_n_D_1_t1_im[281] = t1_im_281_2; + assign Direct_Lookup_Table_n_D_1_t1_im[282] = t1_im_282_2; + assign Direct_Lookup_Table_n_D_1_t1_im[283] = t1_im_283_2; + assign Direct_Lookup_Table_n_D_1_t1_im[284] = t1_im_284_2; + assign Direct_Lookup_Table_n_D_1_t1_im[285] = t1_im_285_2; + assign Direct_Lookup_Table_n_D_1_t1_im[286] = t1_im_286_2; + assign Direct_Lookup_Table_n_D_1_t1_im[287] = t1_im_287_2; + assign Direct_Lookup_Table_n_D_1_t1_im[288] = t1_im_288_2; + assign Direct_Lookup_Table_n_D_1_t1_im[289] = t1_im_289_2; + assign Direct_Lookup_Table_n_D_1_t1_im[290] = t1_im_290_2; + assign Direct_Lookup_Table_n_D_1_t1_im[291] = t1_im_291_2; + assign Direct_Lookup_Table_n_D_1_t1_im[292] = t1_im_292_2; + assign Direct_Lookup_Table_n_D_1_t1_im[293] = t1_im_293_2; + assign Direct_Lookup_Table_n_D_1_t1_im[294] = t1_im_294_2; + assign Direct_Lookup_Table_n_D_1_t1_im[295] = t1_im_295_2; + assign Direct_Lookup_Table_n_D_1_t1_im[296] = t1_im_296_2; + assign Direct_Lookup_Table_n_D_1_t1_im[297] = t1_im_297_2; + assign Direct_Lookup_Table_n_D_1_t1_im[298] = t1_im_298_2; + assign Direct_Lookup_Table_n_D_1_t1_im[299] = t1_im_299_2; + assign Direct_Lookup_Table_n_D_1_t1_im[300] = t1_im_300_2; + assign Direct_Lookup_Table_n_D_1_t1_im[301] = t1_im_301_2; + assign Direct_Lookup_Table_n_D_1_t1_im[302] = t1_im_302_2; + assign Direct_Lookup_Table_n_D_1_t1_im[303] = t1_im_303_2; + assign Direct_Lookup_Table_n_D_1_t1_im[304] = t1_im_304_2; + assign Direct_Lookup_Table_n_D_1_t1_im[305] = t1_im_305_2; + assign Direct_Lookup_Table_n_D_1_t1_im[306] = t1_im_306_2; + assign Direct_Lookup_Table_n_D_1_t1_im[307] = t1_im_307_2; + assign Direct_Lookup_Table_n_D_1_t1_im[308] = t1_im_308_2; + assign Direct_Lookup_Table_n_D_1_t1_im[309] = t1_im_309_2; + assign Direct_Lookup_Table_n_D_1_t1_im[310] = t1_im_310_2; + assign Direct_Lookup_Table_n_D_1_t1_im[311] = t1_im_311_2; + assign Direct_Lookup_Table_n_D_1_t1_im[312] = t1_im_312_2; + assign Direct_Lookup_Table_n_D_1_t1_im[313] = t1_im_313_2; + assign Direct_Lookup_Table_n_D_1_t1_im[314] = t1_im_314_2; + assign Direct_Lookup_Table_n_D_1_t1_im[315] = t1_im_315_2; + assign Direct_Lookup_Table_n_D_1_t1_im[316] = t1_im_316_2; + assign Direct_Lookup_Table_n_D_1_t1_im[317] = t1_im_317_2; + assign Direct_Lookup_Table_n_D_1_t1_im[318] = t1_im_318_2; + assign Direct_Lookup_Table_n_D_1_t1_im[319] = t1_im_319_2; + assign Direct_Lookup_Table_n_D_1_t1_im[320] = t1_im_320_2; + assign Direct_Lookup_Table_n_D_1_t1_im[321] = t1_im_321_2; + assign Direct_Lookup_Table_n_D_1_t1_im[322] = t1_im_322_2; + assign Direct_Lookup_Table_n_D_1_t1_im[323] = t1_im_323_2; + assign Direct_Lookup_Table_n_D_1_t1_im[324] = t1_im_324_2; + assign Direct_Lookup_Table_n_D_1_t1_im[325] = t1_im_325_2; + assign Direct_Lookup_Table_n_D_1_t1_im[326] = t1_im_326_2; + assign Direct_Lookup_Table_n_D_1_t1_im[327] = t1_im_327_2; + assign Direct_Lookup_Table_n_D_1_t1_im[328] = t1_im_328_2; + assign Direct_Lookup_Table_n_D_1_t1_im[329] = t1_im_329_2; + assign Direct_Lookup_Table_n_D_1_t1_im[330] = t1_im_330_2; + assign Direct_Lookup_Table_n_D_1_t1_im[331] = t1_im_331_2; + assign Direct_Lookup_Table_n_D_1_t1_im[332] = t1_im_332_2; + assign Direct_Lookup_Table_n_D_1_t1_im[333] = t1_im_333_2; + assign Direct_Lookup_Table_n_D_1_t1_im[334] = t1_im_334_2; + assign Direct_Lookup_Table_n_D_1_t1_im[335] = t1_im_335_2; + assign Direct_Lookup_Table_n_D_1_t1_im[336] = t1_im_336_2; + assign Direct_Lookup_Table_n_D_1_t1_im[337] = t1_im_337_2; + assign Direct_Lookup_Table_n_D_1_t1_im[338] = t1_im_338_2; + assign Direct_Lookup_Table_n_D_1_t1_im[339] = t1_im_339_2; + assign Direct_Lookup_Table_n_D_1_t1_im[340] = t1_im_340_2; + assign Direct_Lookup_Table_n_D_1_t1_im[341] = t1_im_341_2; + assign Direct_Lookup_Table_n_D_1_t1_im[342] = t1_im_342_2; + assign Direct_Lookup_Table_n_D_1_t1_im[343] = t1_im_343_2; + assign Direct_Lookup_Table_n_D_1_t1_im[344] = t1_im_344_2; + assign Direct_Lookup_Table_n_D_1_t1_im[345] = t1_im_345_2; + assign Direct_Lookup_Table_n_D_1_t1_im[346] = t1_im_346_2; + assign Direct_Lookup_Table_n_D_1_t1_im[347] = t1_im_347_2; + assign Direct_Lookup_Table_n_D_1_t1_im[348] = t1_im_348_2; + assign Direct_Lookup_Table_n_D_1_t1_im[349] = t1_im_349_2; + assign Direct_Lookup_Table_n_D_1_t1_im[350] = t1_im_350_2; + assign Direct_Lookup_Table_n_D_1_t1_im[351] = t1_im_351_2; + assign Direct_Lookup_Table_n_D_1_t1_im[352] = t1_im_352_2; + assign Direct_Lookup_Table_n_D_1_t1_im[353] = t1_im_353_2; + assign Direct_Lookup_Table_n_D_1_t1_im[354] = t1_im_354_2; + assign Direct_Lookup_Table_n_D_1_t1_im[355] = t1_im_355_2; + assign Direct_Lookup_Table_n_D_1_t1_im[356] = t1_im_356_2; + assign Direct_Lookup_Table_n_D_1_t1_im[357] = t1_im_357_2; + assign Direct_Lookup_Table_n_D_1_t1_im[358] = t1_im_358_2; + assign Direct_Lookup_Table_n_D_1_t1_im[359] = t1_im_359_2; + assign Direct_Lookup_Table_n_D_1_t1_im[360] = t1_im_360_2; + assign Direct_Lookup_Table_n_D_1_t1_im[361] = t1_im_361_2; + assign Direct_Lookup_Table_n_D_1_t1_im[362] = t1_im_362_2; + assign Direct_Lookup_Table_n_D_1_t1_im[363] = t1_im_363_2; + assign Direct_Lookup_Table_n_D_1_t1_im[364] = t1_im_364_2; + assign Direct_Lookup_Table_n_D_1_t1_im[365] = t1_im_365_2; + assign Direct_Lookup_Table_n_D_1_t1_im[366] = t1_im_366_2; + assign Direct_Lookup_Table_n_D_1_t1_im[367] = t1_im_367_2; + assign Direct_Lookup_Table_n_D_1_t1_im[368] = t1_im_368_2; + assign Direct_Lookup_Table_n_D_1_t1_im[369] = t1_im_369_2; + assign Direct_Lookup_Table_n_D_1_t1_im[370] = t1_im_370_2; + assign Direct_Lookup_Table_n_D_1_t1_im[371] = t1_im_371_2; + assign Direct_Lookup_Table_n_D_1_t1_im[372] = t1_im_372_2; + assign Direct_Lookup_Table_n_D_1_t1_im[373] = t1_im_373_2; + assign Direct_Lookup_Table_n_D_1_t1_im[374] = t1_im_374_2; + assign Direct_Lookup_Table_n_D_1_t1_im[375] = t1_im_375_2; + assign Direct_Lookup_Table_n_D_1_t1_im[376] = t1_im_376_2; + assign Direct_Lookup_Table_n_D_1_t1_im[377] = t1_im_377_2; + assign Direct_Lookup_Table_n_D_1_t1_im[378] = t1_im_378_2; + assign Direct_Lookup_Table_n_D_1_t1_im[379] = t1_im_379_2; + assign Direct_Lookup_Table_n_D_1_t1_im[380] = t1_im_380_2; + assign Direct_Lookup_Table_n_D_1_t1_im[381] = t1_im_381_2; + assign Direct_Lookup_Table_n_D_1_t1_im[382] = t1_im_382_2; + assign Direct_Lookup_Table_n_D_1_t1_im[383] = t1_im_383_2; + assign Direct_Lookup_Table_n_D_1_t1_im[384] = t1_im_384_2; + assign Direct_Lookup_Table_n_D_1_t1_im[385] = t1_im_385_2; + assign Direct_Lookup_Table_n_D_1_t1_im[386] = t1_im_386_2; + assign Direct_Lookup_Table_n_D_1_t1_im[387] = t1_im_387_2; + assign Direct_Lookup_Table_n_D_1_t1_im[388] = t1_im_388_2; + assign Direct_Lookup_Table_n_D_1_t1_im[389] = t1_im_389_2; + assign Direct_Lookup_Table_n_D_1_t1_im[390] = t1_im_390_2; + assign Direct_Lookup_Table_n_D_1_t1_im[391] = t1_im_391_2; + assign Direct_Lookup_Table_n_D_1_t1_im[392] = t1_im_392_2; + assign Direct_Lookup_Table_n_D_1_t1_im[393] = t1_im_393_2; + assign Direct_Lookup_Table_n_D_1_t1_im[394] = t1_im_394_2; + assign Direct_Lookup_Table_n_D_1_t1_im[395] = t1_im_395_2; + assign Direct_Lookup_Table_n_D_1_t1_im[396] = t1_im_396_2; + assign Direct_Lookup_Table_n_D_1_t1_im[397] = t1_im_397_2; + assign Direct_Lookup_Table_n_D_1_t1_im[398] = t1_im_398_2; + assign Direct_Lookup_Table_n_D_1_t1_im[399] = t1_im_399_2; + assign Direct_Lookup_Table_n_D_1_t1_im[400] = t1_im_400_2; + assign Direct_Lookup_Table_n_D_1_t1_im[401] = t1_im_401_2; + assign Direct_Lookup_Table_n_D_1_t1_im[402] = t1_im_402_2; + assign Direct_Lookup_Table_n_D_1_t1_im[403] = t1_im_403_2; + assign Direct_Lookup_Table_n_D_1_t1_im[404] = t1_im_404_2; + assign Direct_Lookup_Table_n_D_1_t1_im[405] = t1_im_405_2; + assign Direct_Lookup_Table_n_D_1_t1_im[406] = t1_im_406_2; + assign Direct_Lookup_Table_n_D_1_t1_im[407] = t1_im_407_2; + assign Direct_Lookup_Table_n_D_1_t1_im[408] = t1_im_408_2; + assign Direct_Lookup_Table_n_D_1_t1_im[409] = t1_im_409_2; + assign Direct_Lookup_Table_n_D_1_t1_im[410] = t1_im_410_2; + assign Direct_Lookup_Table_n_D_1_t1_im[411] = t1_im_411_2; + assign Direct_Lookup_Table_n_D_1_t1_im[412] = t1_im_412_2; + assign Direct_Lookup_Table_n_D_1_t1_im[413] = t1_im_413_2; + assign Direct_Lookup_Table_n_D_1_t1_im[414] = t1_im_414_2; + assign Direct_Lookup_Table_n_D_1_t1_im[415] = t1_im_415_2; + assign Direct_Lookup_Table_n_D_1_t1_im[416] = t1_im_416_2; + assign Direct_Lookup_Table_n_D_1_t1_im[417] = t1_im_417_2; + assign Direct_Lookup_Table_n_D_1_t1_im[418] = t1_im_418_2; + assign Direct_Lookup_Table_n_D_1_t1_im[419] = t1_im_419_2; + assign Direct_Lookup_Table_n_D_1_t1_im[420] = t1_im_420_2; + assign Direct_Lookup_Table_n_D_1_t1_im[421] = t1_im_421_2; + assign Direct_Lookup_Table_n_D_1_t1_im[422] = t1_im_422_2; + assign Direct_Lookup_Table_n_D_1_t1_im[423] = t1_im_423_2; + assign Direct_Lookup_Table_n_D_1_t1_im[424] = t1_im_424_2; + assign Direct_Lookup_Table_n_D_1_t1_im[425] = t1_im_425_2; + assign Direct_Lookup_Table_n_D_1_t1_im[426] = t1_im_426_2; + assign Direct_Lookup_Table_n_D_1_t1_im[427] = t1_im_427_2; + assign Direct_Lookup_Table_n_D_1_t1_im[428] = t1_im_428_2; + assign Direct_Lookup_Table_n_D_1_t1_im[429] = t1_im_429_2; + assign Direct_Lookup_Table_n_D_1_t1_im[430] = t1_im_430_2; + assign Direct_Lookup_Table_n_D_1_t1_im[431] = t1_im_431_2; + assign Direct_Lookup_Table_n_D_1_t1_im[432] = t1_im_432_2; + assign Direct_Lookup_Table_n_D_1_t1_im[433] = t1_im_433_2; + assign Direct_Lookup_Table_n_D_1_t1_im[434] = t1_im_434_2; + assign Direct_Lookup_Table_n_D_1_t1_im[435] = t1_im_435_2; + assign Direct_Lookup_Table_n_D_1_t1_im[436] = t1_im_436_2; + assign Direct_Lookup_Table_n_D_1_t1_im[437] = t1_im_437_2; + assign Direct_Lookup_Table_n_D_1_t1_im[438] = t1_im_438_2; + assign Direct_Lookup_Table_n_D_1_t1_im[439] = t1_im_439_2; + assign Direct_Lookup_Table_n_D_1_t1_im[440] = t1_im_440_2; + assign Direct_Lookup_Table_n_D_1_t1_im[441] = t1_im_441_2; + assign Direct_Lookup_Table_n_D_1_t1_im[442] = t1_im_442_2; + assign Direct_Lookup_Table_n_D_1_t1_im[443] = t1_im_443_2; + assign Direct_Lookup_Table_n_D_1_t1_im[444] = t1_im_444_2; + assign Direct_Lookup_Table_n_D_1_t1_im[445] = t1_im_445_2; + assign Direct_Lookup_Table_n_D_1_t1_im[446] = t1_im_446_2; + assign Direct_Lookup_Table_n_D_1_t1_im[447] = t1_im_447_2; + assign Direct_Lookup_Table_n_D_1_t1_im[448] = t1_im_448_2; + assign Direct_Lookup_Table_n_D_1_t1_im[449] = t1_im_449_2; + assign Direct_Lookup_Table_n_D_1_t1_im[450] = t1_im_450_2; + assign Direct_Lookup_Table_n_D_1_t1_im[451] = t1_im_451_2; + assign Direct_Lookup_Table_n_D_1_t1_im[452] = t1_im_452_2; + assign Direct_Lookup_Table_n_D_1_t1_im[453] = t1_im_453_2; + assign Direct_Lookup_Table_n_D_1_t1_im[454] = t1_im_454_2; + assign Direct_Lookup_Table_n_D_1_t1_im[455] = t1_im_455_2; + assign Direct_Lookup_Table_n_D_1_t1_im[456] = t1_im_456_2; + assign Direct_Lookup_Table_n_D_1_t1_im[457] = t1_im_457_2; + assign Direct_Lookup_Table_n_D_1_t1_im[458] = t1_im_458_2; + assign Direct_Lookup_Table_n_D_1_t1_im[459] = t1_im_459_2; + assign Direct_Lookup_Table_n_D_1_t1_im[460] = t1_im_460_2; + assign Direct_Lookup_Table_n_D_1_t1_im[461] = t1_im_461_2; + assign Direct_Lookup_Table_n_D_1_t1_im[462] = t1_im_462_2; + assign Direct_Lookup_Table_n_D_1_t1_im[463] = t1_im_463_2; + assign Direct_Lookup_Table_n_D_1_t1_im[464] = t1_im_464_2; + assign Direct_Lookup_Table_n_D_1_t1_im[465] = t1_im_465_2; + assign Direct_Lookup_Table_n_D_1_t1_im[466] = t1_im_466_2; + assign Direct_Lookup_Table_n_D_1_t1_im[467] = t1_im_467_2; + assign Direct_Lookup_Table_n_D_1_t1_im[468] = t1_im_468_2; + assign Direct_Lookup_Table_n_D_1_t1_im[469] = t1_im_469_2; + assign Direct_Lookup_Table_n_D_1_t1_im[470] = t1_im_470_2; + assign Direct_Lookup_Table_n_D_1_t1_im[471] = t1_im_471_2; + assign Direct_Lookup_Table_n_D_1_t1_im[472] = t1_im_472_2; + assign Direct_Lookup_Table_n_D_1_t1_im[473] = t1_im_473_2; + assign Direct_Lookup_Table_n_D_1_t1_im[474] = t1_im_474_2; + assign Direct_Lookup_Table_n_D_1_t1_im[475] = t1_im_475_2; + assign Direct_Lookup_Table_n_D_1_t1_im[476] = t1_im_476_2; + assign Direct_Lookup_Table_n_D_1_t1_im[477] = t1_im_477_2; + assign Direct_Lookup_Table_n_D_1_t1_im[478] = t1_im_478_2; + assign Direct_Lookup_Table_n_D_1_t1_im[479] = t1_im_479_2; + assign Direct_Lookup_Table_n_D_1_t1_im[480] = t1_im_480_2; + assign Direct_Lookup_Table_n_D_1_t1_im[481] = t1_im_481_2; + assign Direct_Lookup_Table_n_D_1_t1_im[482] = t1_im_482_2; + assign Direct_Lookup_Table_n_D_1_t1_im[483] = t1_im_483_2; + assign Direct_Lookup_Table_n_D_1_t1_im[484] = t1_im_484_2; + assign Direct_Lookup_Table_n_D_1_t1_im[485] = t1_im_485_2; + assign Direct_Lookup_Table_n_D_1_t1_im[486] = t1_im_486_2; + assign Direct_Lookup_Table_n_D_1_t1_im[487] = t1_im_487_2; + assign Direct_Lookup_Table_n_D_1_t1_im[488] = t1_im_488_2; + assign Direct_Lookup_Table_n_D_1_t1_im[489] = t1_im_489_2; + assign Direct_Lookup_Table_n_D_1_t1_im[490] = t1_im_490_2; + assign Direct_Lookup_Table_n_D_1_t1_im[491] = t1_im_491_2; + assign Direct_Lookup_Table_n_D_1_t1_im[492] = t1_im_492_2; + assign Direct_Lookup_Table_n_D_1_t1_im[493] = t1_im_493_2; + assign Direct_Lookup_Table_n_D_1_t1_im[494] = t1_im_494_2; + assign Direct_Lookup_Table_n_D_1_t1_im[495] = t1_im_495_2; + assign Direct_Lookup_Table_n_D_1_t1_im[496] = t1_im_496_2; + assign Direct_Lookup_Table_n_D_1_t1_im[497] = t1_im_497_2; + assign Direct_Lookup_Table_n_D_1_t1_im[498] = t1_im_498_2; + assign Direct_Lookup_Table_n_D_1_t1_im[499] = t1_im_499_2; + assign Direct_Lookup_Table_n_D_1_t1_im[500] = t1_im_500_2; + assign Direct_Lookup_Table_n_D_1_t1_im[501] = t1_im_501_2; + assign Direct_Lookup_Table_n_D_1_t1_im[502] = t1_im_502_2; + assign Direct_Lookup_Table_n_D_1_t1_im[503] = t1_im_503_2; + assign Direct_Lookup_Table_n_D_1_t1_im[504] = t1_im_504_2; + assign Direct_Lookup_Table_n_D_1_t1_im[505] = t1_im_505_2; + assign Direct_Lookup_Table_n_D_1_t1_im[506] = t1_im_506_2; + assign Direct_Lookup_Table_n_D_1_t1_im[507] = t1_im_507_2; + assign Direct_Lookup_Table_n_D_1_t1_im[508] = t1_im_508_2; + assign Direct_Lookup_Table_n_D_1_t1_im[509] = t1_im_509_2; + assign Direct_Lookup_Table_n_D_1_t1_im[510] = t1_im_510_2; + assign Direct_Lookup_Table_n_D_1_t1_im[511] = t1_im_511_2; + assign Direct_Lookup_Table_n_D_1_out1_re = Direct_Lookup_Table_n_D_1_t1_re[Data_Type_Conversion2_out1]; + assign Direct_Lookup_Table_n_D_1_out1_im = Direct_Lookup_Table_n_D_1_t1_im[Data_Type_Conversion2_out1]; + + + + // /Complex_Multiply + controllerHdl_Complex_Multiply u_Complex_Multiply (.In1_re(Direct_Lookup_Table_n_D_out1_re), // sfix18_En16 + .In1_im(Direct_Lookup_Table_n_D_out1_im), // sfix18_En16 + .In2_re(Direct_Lookup_Table_n_D_1_out1_re), // sfix18_En16 + .In2_im(Direct_Lookup_Table_n_D_1_out1_im), // sfix18_En16 + .Re(cos_coefficient), // sfix36_En32 + .Im(sin_coefficient) // sfix36_En32 + ); + + // /Data Type Conversion3 + assign sin_coefficient_1 = sin_coefficient[33:16]; + + + + assign sin = sin_coefficient_1; + + // /Data Type Conversion + assign cos_coefficient_1 = cos_coefficient[33:16]; + + + + assign cos = cos_coefficient_1; + +endmodule // controllerHdl_Sin_Cos + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_StandBy.v b/library/controllerperipheralhdladi_pcore/controllerHdl_StandBy.v new file mode 100644 index 000000000..4164744fa --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_StandBy.v @@ -0,0 +1,59 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_StandBy.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_StandBy +// Source Path: controllerHdl/Field_Oriented_Control/StandBy +// Hierarchy Level: 3 +// +// Simulink subsystem description for controllerHdl/Field_Oriented_Control/StandBy: +// +// Stand By mode for controller outputs constant phase voltages. +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_StandBy + ( + Phase_Voltages_0, + Phase_Voltages_1, + Phase_Voltages_2 + ); + + + output signed [19:0] Phase_Voltages_0; // sfix20_En12 + output signed [19:0] Phase_Voltages_1; // sfix20_En12 + output signed [19:0] Phase_Voltages_2; // sfix20_En12 + + + wire signed [19:0] Constant_out1 [0:2]; // sfix20_En12 [3] + + // StandBy + // + // Block Description: Controller outputs constant phase voltages. + + + // /Constant + assign Constant_out1[0] = 20'sb00000000000000000000; + assign Constant_out1[1] = 20'sb00000000000000000000; + assign Constant_out1[2] = 20'sb00000000000000000000; + + + + assign Phase_Voltages_0 = Constant_out1[0]; + + assign Phase_Voltages_1 = Constant_out1[1]; + + assign Phase_Voltages_2 = Constant_out1[2]; + +endmodule // controllerHdl_StandBy + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Transform_dq_to_ABC.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Transform_dq_to_ABC.v new file mode 100644 index 000000000..ef6c4a59f --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Transform_dq_to_ABC.v @@ -0,0 +1,77 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Transform_dq_to_ABC.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Transform_dq_to_ABC +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Transform_dq_to_ABC + ( + d, + q, + sin, + cos, + ABC_0, + ABC_1, + ABC_2 + ); + + + input signed [17:0] d; // sfix18_En12 + input signed [17:0] q; // sfix18_En12 + input signed [17:0] sin; // sfix18_En16 + input signed [17:0] cos; // sfix18_En16 + output signed [17:0] ABC_0; // sfix18_En13 + output signed [17:0] ABC_1; // sfix18_En13 + output signed [17:0] ABC_2; // sfix18_En13 + + + wire signed [17:0] Inverse_Park_Transform_out1; // sfix18_En10 + wire signed [17:0] Inverse_Park_Transform_out2; // sfix18_En10 + wire signed [17:0] Inverse_Clarke_Transform_out1_0; // sfix18_En13 + wire signed [17:0] Inverse_Clarke_Transform_out1_1; // sfix18_En13 + wire signed [17:0] Inverse_Clarke_Transform_out1_2; // sfix18_En13 + + // Transform Coordinates dq to ABC + // + // Converts the two coordinate time invariant system (dq) to a three-phase time and speed dependent system (ABC). + + + // /Inverse_Park_Transform + controllerHdl_Inverse_Park_Transform u_Inverse_Park_Transform (.direct_voltage(d), // sfix18_En12 + .quadrature_voltage(q), // sfix18_En12 + .sin_coefficient(sin), // sfix18_En16 + .cos_coefficient(cos), // sfix18_En16 + .alpha_voltage(Inverse_Park_Transform_out1), // sfix18_En10 + .beta_voltage(Inverse_Park_Transform_out2) // sfix18_En10 + ); + + // /Inverse_Clarke_Transform + controllerHdl_Inverse_Clarke_Transform u_Inverse_Clarke_Transform (.alpha_voltage(Inverse_Park_Transform_out1), // sfix18_En10 + .beta_voltage(Inverse_Park_Transform_out2), // sfix18_En10 + .phase_voltages_0(Inverse_Clarke_Transform_out1_0), // sfix18_En13 + .phase_voltages_1(Inverse_Clarke_Transform_out1_1), // sfix18_En13 + .phase_voltages_2(Inverse_Clarke_Transform_out1_2) // sfix18_En13 + ); + + assign ABC_0 = Inverse_Clarke_Transform_out1_0; + + assign ABC_1 = Inverse_Clarke_Transform_out1_1; + + assign ABC_2 = Inverse_Clarke_Transform_out1_2; + +endmodule // controllerHdl_Transform_dq_to_ABC + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_2pi.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_2pi.v new file mode 100644 index 000000000..e841b62b4 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_2pi.v @@ -0,0 +1,124 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Wrap_2pi.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Wrap_2pi +// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Encoder_To_Rotor_Position/Wrap_2pi +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Wrap_2pi + ( + x, + wrap + ); + + + input signed [18:0] x; // sfix19_En14 + output signed [17:0] wrap; // sfix18_En14 + + + wire signed [18:0] Two_Pi1_out1; // sfix19_En14 + wire signed [18:0] Two_Pi3_out1; // sfix19_En14 + wire Relational_Operator1_relop1; + wire signed [19:0] x_dtc; // sfix20_En14 + wire signed [18:0] Two_Pi2_out1; // sfix19_En14 + wire signed [18:0] Two_Pi_out1; // sfix19_En14 + wire Relational_Operator_relop1; + wire signed [19:0] Add2_add_cast; // sfix20_En14 + wire signed [19:0] Add2_add_cast_1; // sfix20_En14 + wire signed [19:0] Add2_out1; // sfix20_En14 + wire signed [19:0] Switch1_out1; // sfix20_En14 + wire signed [17:0] Switch1_out1_dtc; // sfix18_En14 + wire signed [19:0] Add1_sub_cast; // sfix20_En14 + wire signed [19:0] Add1_sub_cast_1; // sfix20_En14 + wire signed [19:0] Add1_out1; // sfix20_En14 + wire signed [17:0] Add1_out1_dtc; // sfix18_En14 + wire signed [17:0] Switch_out1; // sfix18_En14 + + + // /Two Pi1 + assign Two_Pi1_out1 = 19'sb0011001001000100000; + + + + // /Two Pi3 + assign Two_Pi3_out1 = 19'sb0000000000000000000; + + + + // /Relational Operator1 + assign Relational_Operator1_relop1 = (x < Two_Pi3_out1 ? 1'b1 : + 1'b0); + + + + assign x_dtc = x; + + + + // /Two Pi2 + assign Two_Pi2_out1 = 19'sb0011001001000100000; + + + + // /Two Pi + assign Two_Pi_out1 = 19'sb0011001001000100000; + + + + // /Relational Operator + assign Relational_Operator_relop1 = (x >= Two_Pi1_out1 ? 1'b1 : + 1'b0); + + + + // /Add2 + assign Add2_add_cast = x; + assign Add2_add_cast_1 = Two_Pi2_out1; + assign Add2_out1 = Add2_add_cast + Add2_add_cast_1; + + + + // /Switch1 + assign Switch1_out1 = (Relational_Operator1_relop1 == 1'b0 ? x_dtc : + Add2_out1); + + + + assign Switch1_out1_dtc = Switch1_out1[17:0]; + + + + // /Add1 + assign Add1_sub_cast = x; + assign Add1_sub_cast_1 = Two_Pi_out1; + assign Add1_out1 = Add1_sub_cast - Add1_sub_cast_1; + + + + assign Add1_out1_dtc = Add1_out1[17:0]; + + + + // /Switch + assign Switch_out1 = (Relational_Operator_relop1 == 1'b0 ? Switch1_out1_dtc : + Add1_out1_dtc); + + + + assign wrap = Switch_out1; + +endmodule // controllerHdl_Wrap_2pi + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_2pi_Once.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_2pi_Once.v new file mode 100644 index 000000000..54c647210 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_2pi_Once.v @@ -0,0 +1,105 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Wrap_2pi_Once.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Wrap_2pi_Once +// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Electrical_Velocity_To_Position/Wrap_2pi_Once +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Wrap_2pi_Once + ( + x, + wrap + ); + + + input signed [31:0] x; // sfix32_En27 + output signed [31:0] wrap; // sfix32_En27 + + + wire signed [31:0] Two_Pi1_out1; // sfix32_En27 + wire Relational_Operator_relop1; + wire signed [31:0] Two_Pi3_out1; // sfix32_En27 + wire Relational_Operator1_relop1; + wire signed [31:0] Two_Pi2_out1; // sfix32_En27 + wire signed [31:0] Add2_out1; // sfix32_En27 + wire signed [31:0] Switch1_out1; // sfix32_En27 + wire signed [31:0] Two_Pi_out1; // sfix32_En27 + wire signed [31:0] Add1_out1; // sfix32_En27 + wire signed [31:0] Switch_out1; // sfix32_En27 + + // Wrap 2pi Once + + + // /Two Pi1 + assign Two_Pi1_out1 = 32'sb00110010010000111111011010101001; + + + + // /Relational Operator + assign Relational_Operator_relop1 = (x >= Two_Pi1_out1 ? 1'b1 : + 1'b0); + + + + // /Two Pi3 + assign Two_Pi3_out1 = 32'sb00000000000000000000000000000000; + + + + // /Relational Operator1 + assign Relational_Operator1_relop1 = (x < Two_Pi3_out1 ? 1'b1 : + 1'b0); + + + + // /Two Pi2 + assign Two_Pi2_out1 = 32'sb00110010010000111111011010101001; + + + + // /Add2 + assign Add2_out1 = x + Two_Pi2_out1; + + + + // /Switch1 + assign Switch1_out1 = (Relational_Operator1_relop1 == 1'b0 ? x : + Add2_out1); + + + + // /Two Pi + assign Two_Pi_out1 = 32'sb00110010010000111111011010101001; + + + + // /Add1 + // + // /Position_Hi_Data_Type + assign Add1_out1 = x - Two_Pi_out1; + + + + // /Switch + assign Switch_out1 = (Relational_Operator_relop1 == 1'b0 ? Switch1_out1 : + Add1_out1); + + + + assign wrap = Switch_out1; + +endmodule // controllerHdl_Wrap_2pi_Once + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_NegPi_To_Pi.v b/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_NegPi_To_Pi.v new file mode 100644 index 000000000..7202d29c3 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_NegPi_To_Pi.v @@ -0,0 +1,129 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Wrap_NegPi_To_Pi.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_Wrap_NegPi_To_Pi +// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Calculate_Rotor_Velocity/Wrap_NegPi_To_Pi +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_Wrap_NegPi_To_Pi + ( + position, + wrap + ); + + + input signed [18:0] position; // sfix19_En14 + output signed [17:0] wrap; // sfix18_En15 + + + wire signed [18:0] Constant1_out1; // sfix19_En14 + wire signed [18:0] Constant_out1; // sfix19_En14 + wire Relational_Operator1_relop1; + wire position_less_than_pi; + wire signed [19:0] Data_Type_Conversion_out1; // sfix20_En14 + wire signed [18:0] Constant3_out1; // sfix19_En14 + wire Relational_Operator_relop1; + wire position_greater_than_pi; + wire signed [19:0] Add1_add_cast; // sfix20_En14 + wire signed [19:0] Add1_add_cast_1; // sfix20_En14 + wire signed [19:0] wrap_position_less_than_neg_pi; // sfix20_En14 + wire signed [19:0] Switch2_out1; // sfix20_En14 + wire signed [18:0] Constant2_out1; // sfix19_En14 + wire signed [19:0] Add_sub_cast; // sfix20_En14 + wire signed [19:0] Add_sub_cast_1; // sfix20_En14 + wire signed [19:0] wrap_position_greater_than_pi; // sfix20_En14 + wire signed [19:0] Switch1_out1; // sfix20_En14 + wire signed [17:0] Angle_Data_Type_out1; // sfix18_En15 + + // Wrap Angle + + + // /Constant1 + assign Constant1_out1 = 19'sb0001100100100010000; + + + + // /Constant + assign Constant_out1 = 19'sb1110011011011110000; + + + + // /Relational Operator1 + assign Relational_Operator1_relop1 = (position < Constant_out1 ? 1'b1 : + 1'b0); + + + + assign position_less_than_pi = Relational_Operator1_relop1; + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = position; + + + + // /Constant3 + assign Constant3_out1 = 19'sb0011001001000100000; + + + + // /Relational Operator + assign Relational_Operator_relop1 = (position >= Constant1_out1 ? 1'b1 : + 1'b0); + + + + assign position_greater_than_pi = Relational_Operator_relop1; + + // /Add1 + assign Add1_add_cast = position; + assign Add1_add_cast_1 = Constant3_out1; + assign wrap_position_less_than_neg_pi = Add1_add_cast + Add1_add_cast_1; + + + + // /Switch2 + assign Switch2_out1 = (position_less_than_pi == 1'b0 ? Data_Type_Conversion_out1 : + wrap_position_less_than_neg_pi); + + + + // /Constant2 + assign Constant2_out1 = 19'sb0011001001000100000; + + + + // /Add + assign Add_sub_cast = position; + assign Add_sub_cast_1 = Constant2_out1; + assign wrap_position_greater_than_pi = Add_sub_cast - Add_sub_cast_1; + + + + // /Switch1 + assign Switch1_out1 = (position_greater_than_pi == 1'b0 ? Switch2_out1 : + wrap_position_greater_than_pi); + + + + // /Angle_Data_Type + assign Angle_Data_Type_out1 = {Switch1_out1[16:0], 1'b0}; + + + + assign wrap = Angle_Data_Type_out1; + +endmodule // controllerHdl_Wrap_NegPi_To_Pi + diff --git a/library/controllerperipheralhdladi_pcore/controllerHdl_controllerHdl.v b/library/controllerperipheralhdladi_pcore/controllerHdl_controllerHdl.v new file mode 100644 index 000000000..584368702 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerHdl_controllerHdl.v @@ -0,0 +1,235 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_controllerHdl.v +// Created: 2014-08-27 21:15:34 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerHdl_controllerHdl +// Source Path: controllerHdl +// Hierarchy Level: 1 +// +// Simulink model description for controllerHdl: +// +// Controller Algorithm for Permanent Magnet Synchronous Machine +// +// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control. +// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals. +// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages. +// +// Simulink subsystem description for controllerHdl: +// +// Controller Algorithm for Permanent Magnet Synchronous Machine +// +// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control. +// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals. +// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages. +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerHdl_controllerHdl + ( + CLK_IN, + reset, + enb_1_2000_0, + adc_current_0, + adc_current_1, + encoder_valid, + encoder_count, + controller_mode, + command, + param_velocity_p_gain, + param_velocity_i_gain, + param_current_p_gain, + param_current_i_gain, + param_open_loop_bias, + param_open_loop_scalar, + param_encoder_zero_offset, + pwm_compare_0, + pwm_compare_1, + pwm_compare_2, + phase_voltages_0, + phase_voltages_1, + phase_voltages_2, + phase_currents_0, + phase_currents_1, + rotor_position, + electrical_position, + rotor_velocity, + dq_currents_0, + dq_currents_1, + electrical_position_err_reg + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input signed [17:0] adc_current_0; // sfix18_En17 + input signed [17:0] adc_current_1; // sfix18_En17 + input encoder_valid; + input [15:0] encoder_count; // uint16 + input [1:0] controller_mode; // ufix2 + input signed [17:0] command; // sfix18_En8 + input signed [17:0] param_velocity_p_gain; // sfix18_En16 + input signed [17:0] param_velocity_i_gain; // sfix18_En15 + input signed [17:0] param_current_p_gain; // sfix18_En10 + input signed [17:0] param_current_i_gain; // sfix18_En2 + input signed [17:0] param_open_loop_bias; // sfix18_En14 + input signed [17:0] param_open_loop_scalar; // sfix18_En16 + input signed [17:0] param_encoder_zero_offset; // sfix18_En14 + output [15:0] pwm_compare_0; // uint16 + output [15:0] pwm_compare_1; // uint16 + output [15:0] pwm_compare_2; // uint16 + output signed [19:0] phase_voltages_0; // sfix20_En12 + output signed [19:0] phase_voltages_1; // sfix20_En12 + output signed [19:0] phase_voltages_2; // sfix20_En12 + output signed [17:0] phase_currents_0; // sfix18_En15 + output signed [17:0] phase_currents_1; // sfix18_En15 + output signed [17:0] rotor_position; // sfix18_En14 + output signed [17:0] electrical_position; // sfix18_En14 + output signed [17:0] rotor_velocity; // sfix18_En8 + output signed [17:0] dq_currents_0; // sfix18_En15 + output signed [17:0] dq_currents_1; // sfix18_En15 + output signed [18:0] electrical_position_err_reg; // sfix19_En14 + + + wire Encoder_To_Position_And_Velocity_out1; + wire signed [17:0] Encoder_To_Position_And_Velocity_out2; // sfix18_En14 + wire signed [17:0] Encoder_To_Position_And_Velocity_out3; // sfix18_En14 + wire signed [17:0] Encoder_To_Position_And_Velocity_out4; // sfix18_En8 + wire signed [17:0] phase_currents_0_1; // sfix18_En15 + wire signed [17:0] phase_currents_1_1; // sfix18_En15 + wire signed [17:0] phase_currents [0:1]; // sfix18_En15 [2] + wire signed [19:0] Field_Oriented_Control_out1_0; // sfix20_En12 + wire signed [19:0] Field_Oriented_Control_out1_1; // sfix20_En12 + wire signed [19:0] Field_Oriented_Control_out1_2; // sfix20_En12 + wire signed [17:0] Field_Oriented_Control_out2_0; // sfix18_En15 + wire signed [17:0] Field_Oriented_Control_out2_1; // sfix18_En15 + wire signed [17:0] Field_Oriented_Control_out3; // sfix18_En14 + wire [15:0] pwm_compare_0_1; // uint16 + wire [15:0] pwm_compare_1_1; // uint16 + wire [15:0] pwm_compare_2_1; // uint16 + wire [15:0] pwm_compare [0:2]; // uint16 [3] + wire signed [18:0] Add_sub_cast; // sfix19_En14 + wire signed [18:0] Add_sub_cast_1; // sfix19_En14 + wire signed [18:0] Add_out1; // sfix19_En14 + wire signed [18:0] MATLAB_Function_out1; // sfix19_En14 + + // Controller HDL + // + // Copyright 2013 The MathWorks, Inc. + + + // /Encoder_To_Position_And_Velocity + controllerHdl_Encoder_To_Position_And_Velocity u_Encoder_To_Position_And_Velocity (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .encoder_valid(encoder_valid), + .encoder_counter(encoder_count), // uint16 + .param_zero_offset(param_encoder_zero_offset), // sfix18_En14 + .position_valid(Encoder_To_Position_And_Velocity_out1), + .rotor_position(Encoder_To_Position_And_Velocity_out2), // sfix18_En14 + .electrical_position(Encoder_To_Position_And_Velocity_out3), // sfix18_En14 + .rotor_velocity(Encoder_To_Position_And_Velocity_out4) // sfix18_En8 + ); + + // /ADC_Peripheral_To_Phase_Current + controllerHdl_ADC_Peripheral_To_Phase_Current u_ADC_Peripheral_To_Phase_Current (.adc_0(adc_current_0), // sfix18_En17 + .adc_1(adc_current_1), // sfix18_En17 + .phase_currents_0(phase_currents_0_1), // sfix18_En15 + .phase_currents_1(phase_currents_1_1) // sfix18_En15 + ); + + assign phase_currents[0] = phase_currents_0_1; + assign phase_currents[1] = phase_currents_1_1; + + // /Field_Oriented_Control + controllerHdl_Field_Oriented_Control u_Field_Oriented_Control (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .controller_mode(controller_mode), // ufix2 + .command(command), // sfix18_En8 + .electrical_postion(Encoder_To_Position_And_Velocity_out3), // sfix18_En14 + .rotor_velocity(Encoder_To_Position_And_Velocity_out4), // sfix18_En8 + .phase_currents_0(phase_currents[0]), // sfix18_En15 + .phase_currents_1(phase_currents[1]), // sfix18_En15 + .param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16 + .param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15 + .param_current_p_gain(param_current_p_gain), // sfix18_En10 + .param_current_i_gain(param_current_i_gain), // sfix18_En2 + .param_open_loop_bias(param_open_loop_bias), // sfix18_En14 + .param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16 + .phase_voltages_0(Field_Oriented_Control_out1_0), // sfix20_En12 + .phase_voltages_1(Field_Oriented_Control_out1_1), // sfix20_En12 + .phase_voltages_2(Field_Oriented_Control_out1_2), // sfix20_En12 + .dq_current_0(Field_Oriented_Control_out2_0), // sfix18_En15 + .dq_current_1(Field_Oriented_Control_out2_1), // sfix18_En15 + .electrical_position_ol(Field_Oriented_Control_out3) // sfix18_En14 + ); + + // /Phase_Voltages_To_Compare_Values + controllerHdl_Phase_Voltages_To_Compare_Values u_Phase_Voltages_To_Compare_Values (.V_0(Field_Oriented_Control_out1_0), // sfix20_En12 + .V_1(Field_Oriented_Control_out1_1), // sfix20_En12 + .V_2(Field_Oriented_Control_out1_2), // sfix20_En12 + .C_0(pwm_compare_0_1), // uint16 + .C_1(pwm_compare_1_1), // uint16 + .C_2(pwm_compare_2_1) // uint16 + ); + + assign pwm_compare[0] = pwm_compare_0_1; + assign pwm_compare[1] = pwm_compare_1_1; + assign pwm_compare[2] = pwm_compare_2_1; + + assign pwm_compare_0 = pwm_compare[0]; + + assign pwm_compare_1 = pwm_compare[1]; + + assign pwm_compare_2 = pwm_compare[2]; + + assign phase_voltages_0 = Field_Oriented_Control_out1_0; + + assign phase_voltages_1 = Field_Oriented_Control_out1_1; + + assign phase_voltages_2 = Field_Oriented_Control_out1_2; + + assign phase_currents_0 = phase_currents[0]; + + assign phase_currents_1 = phase_currents[1]; + + assign rotor_position = Encoder_To_Position_And_Velocity_out2; + + assign electrical_position = Encoder_To_Position_And_Velocity_out3; + + assign rotor_velocity = Encoder_To_Position_And_Velocity_out4; + + assign dq_currents_0 = Field_Oriented_Control_out2_0; + + assign dq_currents_1 = Field_Oriented_Control_out2_1; + + // /Add + assign Add_sub_cast = Field_Oriented_Control_out3; + assign Add_sub_cast_1 = Encoder_To_Position_And_Velocity_out3; + assign Add_out1 = Add_sub_cast - Add_sub_cast_1; + + + + // /MATLAB Function + controllerHdl_MATLAB_Function_block3 u_MATLAB_Function (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .u(Add_out1), // sfix19_En14 + .y(MATLAB_Function_out1) // sfix19_En14 + ); + + assign electrical_position_err_reg = MATLAB_Function_out1; + +endmodule // controllerHdl_controllerHdl + diff --git a/library/controllerperipheralhdladi_pcore/controllerPeripheralHdlAdi.v b/library/controllerperipheralhdladi_pcore/controllerPeripheralHdlAdi.v new file mode 100644 index 000000000..7f0266e7c --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerPeripheralHdlAdi.v @@ -0,0 +1,492 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerPeripheralHdlAdi.v +// Created: 2014-08-28 10:13:59 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// +// -- ------------------------------------------------------------- +// -- Rate and Clocking Details +// -- ------------------------------------------------------------- +// Model base rate: 2e-08 +// Target subsystem base rate: 2e-08 +// +// +// Clock Enable Sample Time +// -- ------------------------------------------------------------- +// ce_out_0 2e-08 +// ce_out_1 4e-05 +// -- ------------------------------------------------------------- +// +// +// Output Signal Clock Enable Sample Time +// -- ------------------------------------------------------------- +// pwm_a ce_out_0 2e-08 +// pwm_b ce_out_0 2e-08 +// pwm_c ce_out_0 2e-08 +// mon_phase_voltage_a ce_out_1 4e-05 +// mon_phase_voltage_b ce_out_1 4e-05 +// mon_phase_current_a ce_out_1 4e-05 +// mon_phase_current_b ce_out_1 4e-05 +// mon_rotor_position ce_out_1 4e-05 +// mon_electrical_position ce_out_1 4e-05 +// mon_rotor_velocity ce_out_1 4e-05 +// mon_d_current ce_out_1 4e-05 +// mon_q_current ce_out_1 4e-05 +// axi_electrical_pos_err ce_out_1 4e-05 +// -- ------------------------------------------------------------- +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerPeripheralHdlAdi +// Source Path: controllerPeripheralHdlAdi +// Hierarchy Level: 0 +// +// Simulink model description for controllerPeripheralHdlAdi: +// +// Controller Algorithm for Permanent Magnet Synchronous Machine +// +// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control. +// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals. +// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages. +// +// Simulink subsystem description for controllerPeripheralHdlAdi: +// +// Controller Algorithm for Permanent Magnet Synchronous Machine +// +// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control. +// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals. +// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages. +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerPeripheralHdlAdi + ( + CLK_IN, + reset, + clk_enable, + adc_current1, + adc_current2, + encoder_a, + encoder_b, + encoder_index, + axi_controller_mode, + axi_command, + axi_velocity_p_gain, + axi_velocity_i_gain, + axi_current_p_gain, + axi_current_i_gain, + axi_open_loop_bias, + axi_open_loop_scalar, + axi_encoder_zero_offset, + ce_out_0, + ce_out_1, + pwm_a, + pwm_b, + pwm_c, + mon_phase_voltage_a, + mon_phase_voltage_b, + mon_phase_current_a, + mon_phase_current_b, + mon_rotor_position, + mon_electrical_position, + mon_rotor_velocity, + mon_d_current, + mon_q_current, + axi_electrical_pos_err + ); + + + input CLK_IN; + input reset; + input clk_enable; + input signed [17:0] adc_current1; // sfix18_En17 + input signed [17:0] adc_current2; // sfix18_En17 + input encoder_a; + input encoder_b; + input encoder_index; + input [1:0] axi_controller_mode; // ufix2 + input signed [17:0] axi_command; // sfix18_En8 + input signed [17:0] axi_velocity_p_gain; // sfix18_En16 + input signed [17:0] axi_velocity_i_gain; // sfix18_En15 + input signed [17:0] axi_current_p_gain; // sfix18_En10 + input signed [17:0] axi_current_i_gain; // sfix18_En2 + input signed [17:0] axi_open_loop_bias; // sfix18_En14 + input signed [17:0] axi_open_loop_scalar; // sfix18_En16 + input signed [17:0] axi_encoder_zero_offset; // sfix18_En14 + output ce_out_0; + output ce_out_1; + output pwm_a; + output pwm_b; + output pwm_c; + output signed [31:0] mon_phase_voltage_a; // int32 + output signed [31:0] mon_phase_voltage_b; // int32 + output signed [31:0] mon_phase_current_a; // int32 + output signed [31:0] mon_phase_current_b; // int32 + output signed [31:0] mon_rotor_position; // int32 + output signed [31:0] mon_electrical_position; // int32 + output signed [31:0] mon_rotor_velocity; // int32 + output signed [31:0] mon_d_current; // int32 + output signed [31:0] mon_q_current; // int32 + output signed [18:0] axi_electrical_pos_err; // sfix19_En14 + + + wire enb_1_2000_0; + wire enb_1_2000_1; + wire enb; + wire enb_1_1_1; + reg signed [17:0] Delay1_out1; // sfix18_En17 + reg signed [17:0] Delay7_out1; // sfix18_En17 + wire Rate_Transition2_out1; + wire [15:0] Rate_Transition6_out1; // uint16 + wire [15:0] Controller_out1_0; // uint16 + wire [15:0] Controller_out1_1; // uint16 + wire [15:0] Controller_out1_2; // uint16 + wire signed [19:0] Controller_out2_0; // sfix20_En12 + wire signed [19:0] Controller_out2_1; // sfix20_En12 + wire signed [19:0] Controller_out2_2; // sfix20_En12 + wire signed [17:0] Controller_out3_0; // sfix18_En15 + wire signed [17:0] Controller_out3_1; // sfix18_En15 + wire signed [17:0] Controller_out4; // sfix18_En14 + wire signed [17:0] Controller_out5; // sfix18_En14 + wire signed [17:0] Controller_out6; // sfix18_En8 + wire signed [17:0] Controller_out7_0; // sfix18_En15 + wire signed [17:0] Controller_out7_1; // sfix18_En15 + wire signed [18:0] Controller_out8; // sfix19_En14 + reg Delay2_out1; + reg Delay3_out1; + reg Delay4_out1; + wire Encoder_Peripheral_Hardware_Specification_out1; + wire [15:0] Encoder_Peripheral_Hardware_Specification_out2; // uint16 + reg Rate_Transition2_bypass_reg; // ufix1 + reg [15:0] Rate_Transition6_bypass_reg; // ufix16 + wire [15:0] Controller_out1 [0:2]; // uint16 [3] + reg [15:0] Rate_Transition1_out1 [0:2]; // uint16 [3] + wire PWM_out1_0; + wire PWM_out1_1; + wire PWM_out1_2; + wire [0:2] PWM_out1; // boolean [3] + reg [0:2] Delay5_out1; // boolean [3] + wire signed [19:0] Controller_out2 [0:2]; // sfix20_En12 [3] + wire signed [31:0] Data_Type_Conversion_cast; // sfix32_En12 + wire signed [31:0] Data_Type_Conversion_cast_1; // sfix32_En12 + wire signed [31:0] Data_Type_Conversion_cast_2; // sfix32_En12 + wire signed [31:0] Data_Type_Conversion_out1 [0:2]; // int32 [3] + wire signed [17:0] Controller_out3 [0:1]; // sfix18_En15 [2] + wire signed [31:0] Data_Type_Conversion1_cast; // sfix32_En15 + wire signed [31:0] Data_Type_Conversion1_cast_1; // sfix32_En15 + wire signed [31:0] Data_Type_Conversion1_out1 [0:1]; // int32 [2] + wire signed [31:0] Data_Type_Conversion2_out1; // int32 + wire signed [31:0] Data_Type_Conversion3_out1; // int32 + wire signed [31:0] Data_Type_Conversion4_out1; // int32 + wire signed [17:0] Controller_out7 [0:1]; // sfix18_En15 [2] + wire signed [31:0] Data_Type_Conversion5_cast; // sfix32_En15 + wire signed [31:0] Data_Type_Conversion5_cast_1; // sfix32_En15 + wire signed [31:0] Data_Type_Conversion5_out1 [0:1]; // int32 [2] + + // Controller Peripheral HDL + // Analog Devices Reference Framework + // + // Copyright 2013 The MathWorks, Inc. + + + controllerPeripheralHdlAdi_tc u_controllerPeripheralHdlAdi_tc (.CLK_IN(CLK_IN), + .reset(reset), + .clk_enable(clk_enable), + .enb(enb), + .enb_1_1_1(enb_1_1_1), + .enb_1_2000_0(enb_1_2000_0), + .enb_1_2000_1(enb_1_2000_1) + ); + + // /Delay1 + // + // /Mux + always @(posedge CLK_IN) + begin : Delay1_process + if (reset == 1'b1) begin + Delay1_out1 <= 18'sb000000000000000000; + end + else if (enb_1_2000_0) begin + Delay1_out1 <= adc_current1; + end + end + + + + // /Delay7 + always @(posedge CLK_IN) + begin : Delay7_process + if (reset == 1'b1) begin + Delay7_out1 <= 18'sb000000000000000000; + end + else if (enb_1_2000_0) begin + Delay7_out1 <= adc_current2; + end + end + + + + // /Delay2 + always @(posedge CLK_IN) + begin : Delay2_process + if (reset == 1'b1) begin + Delay2_out1 <= 1'b0; + end + else if (enb) begin + Delay2_out1 <= encoder_a; + end + end + + + + // /Delay3 + always @(posedge CLK_IN) + begin : Delay3_process + if (reset == 1'b1) begin + Delay3_out1 <= 1'b0; + end + else if (enb) begin + Delay3_out1 <= encoder_b; + end + end + + + + // /Delay4 + always @(posedge CLK_IN) + begin : Delay4_process + if (reset == 1'b1) begin + Delay4_out1 <= 1'b0; + end + else if (enb) begin + Delay4_out1 <= encoder_index; + end + end + + + + // /Encoder_Peripheral_Hardware_Specification + Encoder_Peripheral_Hardware_Specification u_Encoder_Peripheral_Hardware_Specification (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .a(Delay2_out1), + .b(Delay3_out1), + .index(Delay4_out1), + .valid(Encoder_Peripheral_Hardware_Specification_out1), + .count(Encoder_Peripheral_Hardware_Specification_out2) // uint16 + ); + + // /Rate Transition2 + always @(posedge CLK_IN) + begin : Rate_Transition2_bypass_process + if (reset == 1'b1) begin + Rate_Transition2_bypass_reg <= 1'b0; + end + else if (enb_1_2000_1) begin + Rate_Transition2_bypass_reg <= Encoder_Peripheral_Hardware_Specification_out1; + end + end + + assign Rate_Transition2_out1 = (enb_1_2000_1 == 1'b1 ? Encoder_Peripheral_Hardware_Specification_out1 : + Rate_Transition2_bypass_reg); + + + + // /Rate Transition6 + always @(posedge CLK_IN) + begin : Rate_Transition6_bypass_process + if (reset == 1'b1) begin + Rate_Transition6_bypass_reg <= 16'b0000000000000000; + end + else if (enb_1_2000_1) begin + Rate_Transition6_bypass_reg <= Encoder_Peripheral_Hardware_Specification_out2; + end + end + + assign Rate_Transition6_out1 = (enb_1_2000_1 == 1'b1 ? Encoder_Peripheral_Hardware_Specification_out2 : + Rate_Transition6_bypass_reg); + + + + // /Controller + controllerHdl_controllerHdl u_Controller (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .adc_current_0(Delay1_out1), // sfix18_En17 + .adc_current_1(Delay7_out1), // sfix18_En17 + .encoder_valid(Rate_Transition2_out1), + .encoder_count(Rate_Transition6_out1), // uint16 + .controller_mode(axi_controller_mode), // ufix2 + .command(axi_command), // sfix18_En8 + .param_velocity_p_gain(axi_velocity_p_gain), // sfix18_En16 + .param_velocity_i_gain(axi_velocity_i_gain), // sfix18_En15 + .param_current_p_gain(axi_current_p_gain), // sfix18_En10 + .param_current_i_gain(axi_current_i_gain), // sfix18_En2 + .param_open_loop_bias(axi_open_loop_bias), // sfix18_En14 + .param_open_loop_scalar(axi_open_loop_scalar), // sfix18_En16 + .param_encoder_zero_offset(axi_encoder_zero_offset), // sfix18_En14 + .pwm_compare_0(Controller_out1_0), // uint16 + .pwm_compare_1(Controller_out1_1), // uint16 + .pwm_compare_2(Controller_out1_2), // uint16 + .phase_voltages_0(Controller_out2_0), // sfix20_En12 + .phase_voltages_1(Controller_out2_1), // sfix20_En12 + .phase_voltages_2(Controller_out2_2), // sfix20_En12 + .phase_currents_0(Controller_out3_0), // sfix18_En15 + .phase_currents_1(Controller_out3_1), // sfix18_En15 + .rotor_position(Controller_out4), // sfix18_En14 + .electrical_position(Controller_out5), // sfix18_En14 + .rotor_velocity(Controller_out6), // sfix18_En8 + .dq_currents_0(Controller_out7_0), // sfix18_En15 + .dq_currents_1(Controller_out7_1), // sfix18_En15 + .electrical_position_err_reg(Controller_out8) // sfix19_En14 + ); + + assign Controller_out1[0] = Controller_out1_0; + assign Controller_out1[1] = Controller_out1_1; + assign Controller_out1[2] = Controller_out1_2; + + // /Rate Transition1 + always @(posedge CLK_IN) + begin : Rate_Transition1_process + if (reset == 1'b1) begin + Rate_Transition1_out1[0] <= 16'b0000000000000000; + Rate_Transition1_out1[1] <= 16'b0000000000000000; + Rate_Transition1_out1[2] <= 16'b0000000000000000; + end + else if (enb_1_2000_0) begin + Rate_Transition1_out1[0] <= Controller_out1[0]; + Rate_Transition1_out1[1] <= Controller_out1[1]; + Rate_Transition1_out1[2] <= Controller_out1[2]; + end + end + + + + // /PWM + PWM u_PWM (.CLK_IN(CLK_IN), + .reset(reset), + .enb(enb), + .c_0(Rate_Transition1_out1[0]), // uint16 + .c_1(Rate_Transition1_out1[1]), // uint16 + .c_2(Rate_Transition1_out1[2]), // uint16 + .pwm_0(PWM_out1_0), // boolean + .pwm_1(PWM_out1_1), // boolean + .pwm_2(PWM_out1_2) // boolean + ); + + assign PWM_out1[0] = PWM_out1_0; + assign PWM_out1[1] = PWM_out1_1; + assign PWM_out1[2] = PWM_out1_2; + + // /Delay5 + always @(posedge CLK_IN) + begin : Delay5_process + if (reset == 1'b1) begin + Delay5_out1[0] <= 1'b0; + Delay5_out1[1] <= 1'b0; + Delay5_out1[2] <= 1'b0; + end + else if (enb) begin + Delay5_out1[0] <= PWM_out1[0]; + Delay5_out1[1] <= PWM_out1[1]; + Delay5_out1[2] <= PWM_out1[2]; + end + end + + + + // /Demux + assign pwm_a = Delay5_out1[0]; + + assign pwm_b = Delay5_out1[1]; + + assign pwm_c = Delay5_out1[2]; + + assign Controller_out2[0] = Controller_out2_0; + assign Controller_out2[1] = Controller_out2_1; + assign Controller_out2[2] = Controller_out2_2; + + // /Data Type Conversion + assign Data_Type_Conversion_cast = Controller_out2[0]; + assign Data_Type_Conversion_out1[0] = Data_Type_Conversion_cast; + assign Data_Type_Conversion_cast_1 = Controller_out2[1]; + assign Data_Type_Conversion_out1[1] = Data_Type_Conversion_cast_1; + assign Data_Type_Conversion_cast_2 = Controller_out2[2]; + assign Data_Type_Conversion_out1[2] = Data_Type_Conversion_cast_2; + + + + // /Selector + assign mon_phase_voltage_a = Data_Type_Conversion_out1[0]; + + // /Selector1 + assign mon_phase_voltage_b = Data_Type_Conversion_out1[1]; + + assign Controller_out3[0] = Controller_out3_0; + assign Controller_out3[1] = Controller_out3_1; + + // /Data Type Conversion1 + assign Data_Type_Conversion1_cast = Controller_out3[0]; + assign Data_Type_Conversion1_out1[0] = Data_Type_Conversion1_cast; + assign Data_Type_Conversion1_cast_1 = Controller_out3[1]; + assign Data_Type_Conversion1_out1[1] = Data_Type_Conversion1_cast_1; + + + + // /Demux2 + assign mon_phase_current_a = Data_Type_Conversion1_out1[0]; + + assign mon_phase_current_b = Data_Type_Conversion1_out1[1]; + + // /Data Type Conversion2 + assign Data_Type_Conversion2_out1 = Controller_out4; + + + + assign mon_rotor_position = Data_Type_Conversion2_out1; + + // /Data Type Conversion3 + assign Data_Type_Conversion3_out1 = Controller_out5; + + + + assign mon_electrical_position = Data_Type_Conversion3_out1; + + // /Data Type Conversion4 + assign Data_Type_Conversion4_out1 = Controller_out6; + + + + assign mon_rotor_velocity = Data_Type_Conversion4_out1; + + assign Controller_out7[0] = Controller_out7_0; + assign Controller_out7[1] = Controller_out7_1; + + // /Data Type Conversion5 + assign Data_Type_Conversion5_cast = Controller_out7[0]; + assign Data_Type_Conversion5_out1[0] = Data_Type_Conversion5_cast; + assign Data_Type_Conversion5_cast_1 = Controller_out7[1]; + assign Data_Type_Conversion5_out1[1] = Data_Type_Conversion5_cast_1; + + + + // /Demux1 + assign mon_d_current = Data_Type_Conversion5_out1[0]; + + assign mon_q_current = Data_Type_Conversion5_out1[1]; + + assign axi_electrical_pos_err = Controller_out8; + + assign ce_out_0 = enb_1_1_1; + + assign ce_out_1 = enb_1_2000_1; + +endmodule // controllerPeripheralHdlAdi + diff --git a/library/controllerperipheralhdladi_pcore/controllerPeripheralHdlAdi_tc.v b/library/controllerperipheralhdladi_pcore/controllerPeripheralHdlAdi_tc.v new file mode 100644 index 000000000..caed9c642 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerPeripheralHdlAdi_tc.v @@ -0,0 +1,114 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerPeripheralHdlAdi_tc.v +// Created: 2014-08-28 10:13:59 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerPeripheralHdlAdi_tc +// Source Path: controllerPeripheralHdlAdi_tc +// Hierarchy Level: 1 +// +// Master clock enable input: clk_enable +// +// enb : identical to clk_enable +// enb_1_1_1 : identical to clk_enable +// enb_1_2000_0: 2000x slower than clk_enable with last phase +// enb_1_2000_1: 2000x slower than clk_enable with phase 1 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerPeripheralHdlAdi_tc + ( + CLK_IN, + reset, + clk_enable, + enb, + enb_1_1_1, + enb_1_2000_0, + enb_1_2000_1 + ); + + + input CLK_IN; + input reset; + input clk_enable; + output enb; + output enb_1_1_1; + output enb_1_2000_0; + output enb_1_2000_1; + + + reg [10:0] count2000; // ufix11 + wire phase_all; + reg phase_0; + wire phase_0_tmp; + reg phase_1; + wire phase_1_tmp; + + + always @ ( posedge CLK_IN) + begin: Counter2000 + if (reset == 1'b1) begin + count2000 <= 11'b00000000001; + end + else begin + if (clk_enable == 1'b1) begin + if (count2000 == 11'b11111001111) begin + count2000 <= 11'b00000000000; + end + else begin + count2000 <= count2000 + 1; + end + end + end + end // Counter2000 + + assign phase_all = clk_enable? 1 : 0; + + always @ ( posedge CLK_IN) + begin: temp_process1 + if (reset == 1'b1) begin + phase_0 <= 1'b0; + end + else begin + if (clk_enable == 1'b1) begin + phase_0 <= phase_0_tmp; + end + end + end // temp_process1 + + assign phase_0_tmp = (count2000 == 11'b11111001111 && clk_enable == 1'b1)? 1 : 0; + + always @ ( posedge CLK_IN) + begin: temp_process2 + if (reset == 1'b1) begin + phase_1 <= 1'b1; + end + else begin + if (clk_enable == 1'b1) begin + phase_1 <= phase_1_tmp; + end + end + end // temp_process2 + + assign phase_1_tmp = (count2000 == 11'b00000000000 && clk_enable == 1'b1)? 1 : 0; + + assign enb = phase_all & clk_enable; + + assign enb_1_1_1 = phase_all & clk_enable; + + assign enb_1_2000_0 = phase_0 & clk_enable; + + assign enb_1_2000_1 = phase_1 & clk_enable; + + +endmodule // controllerPeripheralHdlAdi_tc + diff --git a/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore.tcl b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore.tcl new file mode 100644 index 000000000..a8d337dd6 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore.tcl @@ -0,0 +1,116 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create controllerperipheralhdladi_pcore +adi_ip_files controllerperipheralhdladi_pcore [list \ +"velocityControlHdl_Clamp.v" \ +"velocityControlHdl_Convert_Data_Type1.v" \ +"velocityControlHdl_Maintain_Range.v" \ +"velocityControlHdl_Dynamic_Saturation.v" \ +"velocityControlHdl_PI_Sat.v" \ +"velocityControlHdl_Reset_Delay.v" \ +"velocityControlHdl_Control_Current.v" \ +"velocityControlHdl_Clamp_block.v" \ +"velocityControlHdl_Convert_Data_Type1_block.v" \ +"velocityControlHdl_Maintain_Range_block.v" \ +"velocityControlHdl_Dynamic_Saturation_block.v" \ +"velocityControlHdl_PI_Sat_block.v" \ +"velocityControlHdl_Reset_Delay_block.v" \ +"velocityControlHdl_Control_Current1.v" \ +"velocityControlHdl_Control_DQ_Currents.v" \ +"velocityControlHdl_Clamp_block1.v" \ +"velocityControlHdl_Convert_Data_Type.v" \ +"velocityControlHdl_Maintain_Range_block1.v" \ +"velocityControlHdl_Dynamic_Saturation_block1.v" \ +"velocityControlHdl_PI_Sat_block1.v" \ +"velocityControlHdl_Reset_Delay_block1.v" \ +"velocityControlHdl_Rotor_Velocity_Control.v" \ +"velocityControlHdl_Control_Velocity.v" \ +"velocityControlHdl_Complex_Multiply.v" \ +"velocityControlHdl_Convert_Data_Type_block.v" \ +"velocityControlHdl_MATLAB_Function.v" \ +"velocityControlHdl_Mark_Extract_Bits.v" \ +"velocityControlHdl_MATLAB_Function_block.v" \ +"velocityControlHdl_Mark_Extract_Bits1.v" \ +"velocityControlHdl_Sin_Cos1.v" \ +"velocityControlHdl_Double_Range.v" \ +"velocityControlHdl_MinMax.v" \ +"velocityControlHdl_MinMax1.v" \ +"velocityControlHdl_Space_Vector_Modulation.v" \ +"velocityControlHdl_Clarke_Transform.v" \ +"velocityControlHdl_Park_Transform.v" \ +"velocityControlHdl_Transform_ABC_to_dq.v" \ +"velocityControlHdl_Inverse_Clarke_Transform.v" \ +"velocityControlHdl_Convert_Data_Type_block1.v" \ +"velocityControlHdl_Convert_Data_Type1_block1.v" \ +"velocityControlHdl_Inverse_Park_Transform.v" \ +"velocityControlHdl_Transform_dq_to_ABC.v" \ +"velocityControlHdl_velocityControlHdl.v" \ +"controllerHdl_ADC_Peripheral_To_Phase_Current.v" \ +"controllerHdl_Wrap_NegPi_To_Pi.v" \ +"controllerHdl_Calculate_Rotor_Velocity.v" \ +"controllerHdl_Wrap_2pi.v" \ +"controllerHdl_Encoder_To_Rotor_Position.v" \ +"controllerHdl_MATLAB_Function.v" \ +"controllerHdl_Mark_Extract_Bits.v" \ +"controllerHdl_Mod_2pi_Scale_And_Bit_Slice.v" \ +"controllerHdl_Rotor_To_Electrical_Position.v" \ +"controllerHdl_Encoder_To_Position_And_Velocity.v" \ +"controllerHdl_Reset_Delay.v" \ +"controllerHdl_Wrap_2pi_Once.v" \ +"controllerHdl_Electrical_Velocity_To_Position.v" \ +"controllerHdl_Convert_Data_Type.v" \ +"controllerHdl_Double_Range.v" \ +"controllerHdl_Frequency_To_Volts.v" \ +"controllerHdl_Reset_Delay_block.v" \ +"controllerHdl_Detect_Change.v" \ +"controllerHdl_Set_Acceleration.v" \ +"controllerHdl_Rotor_Acceleration_To_Velocity.v" \ +"controllerHdl_Convert_Data_Type_block.v" \ +"controllerHdl_Rotor_To_Electical_Velocity.v" \ +"controllerHdl_Generate_Position_And_Voltage_Ramp.v" \ +"controllerHdl_Complex_Multiply.v" \ +"controllerHdl_Convert_Data_Type_block1.v" \ +"controllerHdl_MATLAB_Function_block.v" \ +"controllerHdl_Mark_Extract_Bits_block.v" \ +"controllerHdl_MATLAB_Function_block1.v" \ +"controllerHdl_Mark_Extract_Bits1.v" \ +"controllerHdl_Sin_Cos.v" \ +"controllerHdl_Inverse_Clarke_Transform.v" \ +"controllerHdl_Convert_Data_Type_block2.v" \ +"controllerHdl_Convert_Data_Type1.v" \ +"controllerHdl_Inverse_Park_Transform.v" \ +"controllerHdl_Transform_dq_to_ABC.v" \ +"controllerHdl_Open_Loop_Control.v" \ +"controllerHdl_StandBy.v" \ +"controllerHdl_MATLAB_Function_block2.v" \ +"controllerHdl_Field_Oriented_Control.v" \ +"controllerHdl_Phase_Voltages_To_Compare_Values.v" \ +"controllerHdl_MATLAB_Function_block3.v" \ +"controllerHdl_controllerHdl.v" \ +"Count_Up_Down.v" \ +"Debounce_A.v" \ +"Debounce_B.v" \ +"Debounce_Index.v" \ +"Detect_Change_To_One.v" \ +"Latch_Index_Pulse.v" \ +"Select_AB.v" \ +"Update_Count_From_AB.v" \ +"Encoder_Peripheral_Hardware_Specification.v" \ +"Chart.v" \ +"PWM.v" \ +"controllerPeripheralHdlAdi_tc.v" \ +"controllerPeripheralHdlAdi.v" \ +"controllerperipheralhdladi_pcore_dut.v" \ +"controllerperipheralhdladi_pcore_axi_lite_module.v" \ +"controllerperipheralhdladi_pcore_addr_decoder.v" \ +"controllerperipheralhdladi_pcore_axi_lite.v" \ +"controllerperipheralhdladi_pcore.v" ] + +adi_ip_properties controllerperipheralhdladi_pcore + +ipx::save_core [ipx::current_core] + + diff --git a/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore.v b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore.v new file mode 100644 index 000000000..5fef1efec --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore.v @@ -0,0 +1,242 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore.v +// Created: 2014-08-28 10:14:05 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// +// -- ------------------------------------------------------------- +// -- Rate and Clocking Details +// -- ------------------------------------------------------------- +// Model base rate: -1 +// Target subsystem base rate: -1 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerperipheralhdladi_pcore +// Source Path: controllerperipheralhdladi_pcore +// Hierarchy Level: 0 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerperipheralhdladi_pcore + ( + IPCORE_CLK, + IPCORE_RESETN, + adc_current1, + adc_current2, + encoder_a, + encoder_b, + encoder_index, + AXI_Lite_ACLK, + AXI_Lite_ARESETN, + AXI_Lite_AWADDR, + AXI_Lite_AWVALID, + AXI_Lite_WDATA, + AXI_Lite_WSTRB, + AXI_Lite_WVALID, + AXI_Lite_BREADY, + AXI_Lite_ARADDR, + AXI_Lite_ARVALID, + AXI_Lite_RREADY, + pwm_a, + pwm_b, + pwm_c, + mon_phase_voltage_a, + mon_phase_voltage_b, + mon_phase_current_a, + mon_phase_current_b, + mon_rotor_position, + mon_electrical_position, + mon_rotor_velocity, + mon_d_current, + mon_q_current, + AXI_Lite_AWREADY, + AXI_Lite_WREADY, + AXI_Lite_BRESP, + AXI_Lite_BVALID, + AXI_Lite_ARREADY, + AXI_Lite_RDATA, + AXI_Lite_RRESP, + AXI_Lite_RVALID + ); + + + input IPCORE_CLK; // ufix1 + input IPCORE_RESETN; // ufix1 + input [17:0] adc_current1; // ufix18 + input [17:0] adc_current2; // ufix18 + input encoder_a; // ufix1 + input encoder_b; // ufix1 + input encoder_index; // ufix1 + input AXI_Lite_ACLK; // ufix1 + input AXI_Lite_ARESETN; // ufix1 + input [31:0] AXI_Lite_AWADDR; // ufix32 + input AXI_Lite_AWVALID; // ufix1 + input [31:0] AXI_Lite_WDATA; // ufix32 + input [3:0] AXI_Lite_WSTRB; // ufix4 + input AXI_Lite_WVALID; // ufix1 + input AXI_Lite_BREADY; // ufix1 + input [31:0] AXI_Lite_ARADDR; // ufix32 + input AXI_Lite_ARVALID; // ufix1 + input AXI_Lite_RREADY; // ufix1 + output pwm_a; // ufix1 + output pwm_b; // ufix1 + output pwm_c; // ufix1 + output [31:0] mon_phase_voltage_a; // ufix32 + output [31:0] mon_phase_voltage_b; // ufix32 + output [31:0] mon_phase_current_a; // ufix32 + output [31:0] mon_phase_current_b; // ufix32 + output [31:0] mon_rotor_position; // ufix32 + output [31:0] mon_electrical_position; // ufix32 + output [31:0] mon_rotor_velocity; // ufix32 + output [31:0] mon_d_current; // ufix32 + output [31:0] mon_q_current; // ufix32 + output AXI_Lite_AWREADY; // ufix1 + output AXI_Lite_WREADY; // ufix1 + output [1:0] AXI_Lite_BRESP; // ufix2 + output AXI_Lite_BVALID; // ufix1 + output AXI_Lite_ARREADY; // ufix1 + output [31:0] AXI_Lite_RDATA; // ufix32 + output [1:0] AXI_Lite_RRESP; // ufix2 + output AXI_Lite_RVALID; // ufix1 + + + wire reset; + wire reset_cm; // ufix1 + wire reset_internal; // ufix1 + wire signed [18:0] axi_electrical_pos_err_sig; // sfix19_En14 + wire dut_enable; // ufix1 + wire [1:0] axi_controller_mode_sig; // ufix2 + wire signed [17:0] axi_command_sig; // sfix18_En8 + wire signed [17:0] axi_velocity_p_gain_sig; // sfix18_En16 + wire signed [17:0] axi_velocity_i_gain_sig; // sfix18_En15 + wire signed [17:0] axi_current_p_gain_sig; // sfix18_En10 + wire signed [17:0] axi_current_i_gain_sig; // sfix18_En2 + wire signed [17:0] axi_open_loop_bias_sig; // sfix18_En14 + wire signed [17:0] axi_open_loop_scalar_sig; // sfix18_En16 + wire signed [17:0] axi_encoder_zero_offset_sig; // sfix18_En14 + wire ce_out_0_sig; // ufix1 + wire ce_out_1_sig; // ufix1 + wire pwm_a_sig; // ufix1 + wire pwm_b_sig; // ufix1 + wire pwm_c_sig; // ufix1 + wire signed [31:0] mon_phase_voltage_a_sig; // sfix32 + wire signed [31:0] mon_phase_voltage_b_sig; // sfix32 + wire signed [31:0] mon_phase_current_a_sig; // sfix32 + wire signed [31:0] mon_phase_current_b_sig; // sfix32 + wire signed [31:0] mon_rotor_position_sig; // sfix32 + wire signed [31:0] mon_electrical_position_sig; // sfix32 + wire signed [31:0] mon_rotor_velocity_sig; // sfix32 + wire signed [31:0] mon_d_current_sig; // sfix32 + wire signed [31:0] mon_q_current_sig; // sfix32 + + + assign reset_cm = ~ IPCORE_RESETN; + + + + assign reset = reset_cm | reset_internal; + + + + controllerperipheralhdladi_pcore_axi_lite u_controllerperipheralhdladi_pcore_axi_lite_inst (.reset(reset), + .AXI_Lite_ACLK(AXI_Lite_ACLK), // ufix1 + .AXI_Lite_ARESETN(AXI_Lite_ARESETN), // ufix1 + .AXI_Lite_AWADDR(AXI_Lite_AWADDR), // ufix32 + .AXI_Lite_AWVALID(AXI_Lite_AWVALID), // ufix1 + .AXI_Lite_WDATA(AXI_Lite_WDATA), // ufix32 + .AXI_Lite_WSTRB(AXI_Lite_WSTRB), // ufix4 + .AXI_Lite_WVALID(AXI_Lite_WVALID), // ufix1 + .AXI_Lite_BREADY(AXI_Lite_BREADY), // ufix1 + .AXI_Lite_ARADDR(AXI_Lite_ARADDR), // ufix32 + .AXI_Lite_ARVALID(AXI_Lite_ARVALID), // ufix1 + .AXI_Lite_RREADY(AXI_Lite_RREADY), // ufix1 + .read_axi_electrical_pos_err(axi_electrical_pos_err_sig), // sfix19_En14 + .AXI_Lite_AWREADY(AXI_Lite_AWREADY), // ufix1 + .AXI_Lite_WREADY(AXI_Lite_WREADY), // ufix1 + .AXI_Lite_BRESP(AXI_Lite_BRESP), // ufix2 + .AXI_Lite_BVALID(AXI_Lite_BVALID), // ufix1 + .AXI_Lite_ARREADY(AXI_Lite_ARREADY), // ufix1 + .AXI_Lite_RDATA(AXI_Lite_RDATA), // ufix32 + .AXI_Lite_RRESP(AXI_Lite_RRESP), // ufix2 + .AXI_Lite_RVALID(AXI_Lite_RVALID), // ufix1 + .write_axi_enable(dut_enable), // ufix1 + .write_axi_controller_mode(axi_controller_mode_sig), // ufix2 + .write_axi_command(axi_command_sig), // sfix18_En8 + .write_axi_velocity_p_gain(axi_velocity_p_gain_sig), // sfix18_En16 + .write_axi_velocity_i_gain(axi_velocity_i_gain_sig), // sfix18_En15 + .write_axi_current_p_gain(axi_current_p_gain_sig), // sfix18_En10 + .write_axi_current_i_gain(axi_current_i_gain_sig), // sfix18_En2 + .write_axi_open_loop_bias(axi_open_loop_bias_sig), // sfix18_En14 + .write_axi_open_loop_scalar(axi_open_loop_scalar_sig), // sfix18_En16 + .write_axi_encoder_zero_offset(axi_encoder_zero_offset_sig), // sfix18_En14 + .reset_internal(reset_internal) // ufix1 + ); + + controllerperipheralhdladi_pcore_dut u_controllerperipheralhdladi_pcore_dut_inst (.CLK_IN(IPCORE_CLK), // ufix1 + .reset(reset), + .dut_enable(dut_enable), // ufix1 + .adc_current1(adc_current1), // sfix18_En17 + .adc_current2(adc_current2), // sfix18_En17 + .encoder_a(encoder_a), // ufix1 + .encoder_b(encoder_b), // ufix1 + .encoder_index(encoder_index), // ufix1 + .axi_controller_mode(axi_controller_mode_sig), // ufix2 + .axi_command(axi_command_sig), // sfix18_En8 + .axi_velocity_p_gain(axi_velocity_p_gain_sig), // sfix18_En16 + .axi_velocity_i_gain(axi_velocity_i_gain_sig), // sfix18_En15 + .axi_current_p_gain(axi_current_p_gain_sig), // sfix18_En10 + .axi_current_i_gain(axi_current_i_gain_sig), // sfix18_En2 + .axi_open_loop_bias(axi_open_loop_bias_sig), // sfix18_En14 + .axi_open_loop_scalar(axi_open_loop_scalar_sig), // sfix18_En16 + .axi_encoder_zero_offset(axi_encoder_zero_offset_sig), // sfix18_En14 + .ce_out_0(ce_out_0_sig), // ufix1 + .ce_out_1(ce_out_1_sig), // ufix1 + .pwm_a(pwm_a_sig), // ufix1 + .pwm_b(pwm_b_sig), // ufix1 + .pwm_c(pwm_c_sig), // ufix1 + .mon_phase_voltage_a(mon_phase_voltage_a_sig), // sfix32 + .mon_phase_voltage_b(mon_phase_voltage_b_sig), // sfix32 + .mon_phase_current_a(mon_phase_current_a_sig), // sfix32 + .mon_phase_current_b(mon_phase_current_b_sig), // sfix32 + .mon_rotor_position(mon_rotor_position_sig), // sfix32 + .mon_electrical_position(mon_electrical_position_sig), // sfix32 + .mon_rotor_velocity(mon_rotor_velocity_sig), // sfix32 + .mon_d_current(mon_d_current_sig), // sfix32 + .mon_q_current(mon_q_current_sig), // sfix32 + .axi_electrical_pos_err(axi_electrical_pos_err_sig) // sfix19_En14 + ); + + assign pwm_a = pwm_a_sig; + + assign pwm_b = pwm_b_sig; + + assign pwm_c = pwm_c_sig; + + assign mon_phase_voltage_a = mon_phase_voltage_a_sig; + + assign mon_phase_voltage_b = mon_phase_voltage_b_sig; + + assign mon_phase_current_a = mon_phase_current_a_sig; + + assign mon_phase_current_b = mon_phase_current_b_sig; + + assign mon_rotor_position = mon_rotor_position_sig; + + assign mon_electrical_position = mon_electrical_position_sig; + + assign mon_rotor_velocity = mon_rotor_velocity_sig; + + assign mon_d_current = mon_d_current_sig; + + assign mon_q_current = mon_q_current_sig; + +endmodule // controllerperipheralhdladi_pcore + diff --git a/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_addr_decoder.v b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_addr_decoder.v new file mode 100644 index 000000000..549ec37f9 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_addr_decoder.v @@ -0,0 +1,421 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore_addr_decoder.v +// Created: 2014-08-28 10:14:05 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerperipheralhdladi_pcore_addr_decoder +// Source Path: controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite/controllerperipheralhdladi_pcore_addr_decoder +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerperipheralhdladi_pcore_addr_decoder + ( + CLK_IN, + reset, + data_write, + addr_sel, + wr_enb, + rd_enb, + read_axi_electrical_pos_err, + data_read, + write_axi_enable, + write_axi_controller_mode, + write_axi_command, + write_axi_velocity_p_gain, + write_axi_velocity_i_gain, + write_axi_current_p_gain, + write_axi_current_i_gain, + write_axi_open_loop_bias, + write_axi_open_loop_scalar, + write_axi_encoder_zero_offset + ); + + + input CLK_IN; + input reset; + input [31:0] data_write; // ufix32 + input [13:0] addr_sel; // ufix14 + input wr_enb; // ufix1 + input rd_enb; // ufix1 + input signed [18:0] read_axi_electrical_pos_err; // sfix19_En14 + output [31:0] data_read; // ufix32 + output write_axi_enable; // ufix1 + output [1:0] write_axi_controller_mode; // ufix2 + output signed [17:0] write_axi_command; // sfix18_En8 + output signed [17:0] write_axi_velocity_p_gain; // sfix18_En16 + output signed [17:0] write_axi_velocity_i_gain; // sfix18_En15 + output signed [17:0] write_axi_current_p_gain; // sfix18_En10 + output signed [17:0] write_axi_current_i_gain; // sfix18_En2 + output signed [17:0] write_axi_open_loop_bias; // sfix18_En14 + output signed [17:0] write_axi_open_loop_scalar; // sfix18_En16 + output signed [17:0] write_axi_encoder_zero_offset; // sfix18_En14 + + + wire enb; + wire decode_sel_axi_electrical_pos_err; // ufix1 + wire const_1; // ufix1 + wire [31:0] const_z; // ufix32 + reg signed [18:0] read_reg_axi_electrical_pos_err; // sfix19_En14 + wire [31:0] data_in_axi_electrical_pos_err; // ufix32 + wire [31:0] decode_rd_axi_electrical_pos_err; // ufix32 + wire data_in_axi_enable; // ufix1 + wire decode_sel_axi_enable; // ufix1 + wire reg_enb_axi_enable; // ufix1 + reg write_reg_axi_enable; // ufix1 + wire [1:0] data_in_axi_controller_mode; // ufix2 + wire decode_sel_axi_controller_mode; // ufix1 + wire reg_enb_axi_controller_mode; // ufix1 + reg [1:0] write_reg_axi_controller_mode; // ufix2 + wire signed [17:0] data_in_axi_command; // sfix18_En8 + wire decode_sel_axi_command; // ufix1 + wire reg_enb_axi_command; // ufix1 + reg signed [17:0] write_reg_axi_command; // sfix18_En8 + wire signed [17:0] data_in_axi_velocity_p_gain; // sfix18_En16 + wire decode_sel_axi_velocity_p_gain; // ufix1 + wire reg_enb_axi_velocity_p_gain; // ufix1 + reg signed [17:0] write_reg_axi_velocity_p_gain; // sfix18_En16 + wire signed [17:0] data_in_axi_velocity_i_gain; // sfix18_En15 + wire decode_sel_axi_velocity_i_gain; // ufix1 + wire reg_enb_axi_velocity_i_gain; // ufix1 + reg signed [17:0] write_reg_axi_velocity_i_gain; // sfix18_En15 + wire signed [17:0] data_in_axi_current_p_gain; // sfix18_En10 + wire decode_sel_axi_current_p_gain; // ufix1 + wire reg_enb_axi_current_p_gain; // ufix1 + reg signed [17:0] write_reg_axi_current_p_gain; // sfix18_En10 + wire signed [17:0] data_in_axi_current_i_gain; // sfix18_En2 + wire decode_sel_axi_current_i_gain; // ufix1 + wire reg_enb_axi_current_i_gain; // ufix1 + reg signed [17:0] write_reg_axi_current_i_gain; // sfix18_En2 + wire signed [17:0] data_in_axi_open_loop_bias; // sfix18_En14 + wire decode_sel_axi_open_loop_bias; // ufix1 + wire reg_enb_axi_open_loop_bias; // ufix1 + reg signed [17:0] write_reg_axi_open_loop_bias; // sfix18_En14 + wire signed [17:0] data_in_axi_open_loop_scalar; // sfix18_En16 + wire decode_sel_axi_open_loop_scalar; // ufix1 + wire reg_enb_axi_open_loop_scalar; // ufix1 + reg signed [17:0] write_reg_axi_open_loop_scalar; // sfix18_En16 + wire signed [17:0] data_in_axi_encoder_zero_offset; // sfix18_En14 + wire decode_sel_axi_encoder_zero_offset; // ufix1 + wire reg_enb_axi_encoder_zero_offset; // ufix1 + reg signed [17:0] write_reg_axi_encoder_zero_offset; // sfix18_En14 + + + assign decode_sel_axi_electrical_pos_err = (addr_sel == 14'b00000001001001 ? 1'b1 : + 1'b0); + + + + assign const_1 = 1'b1; + + + + assign enb = const_1; + + assign const_z = 32'bz; + + + always @(posedge CLK_IN) + begin : reg_axi_electrical_pos_err_process + if (reset == 1'b1) begin + read_reg_axi_electrical_pos_err <= 19'sb0000000000000000000; + end + else if (enb) begin + read_reg_axi_electrical_pos_err <= read_axi_electrical_pos_err; + end + end + + + + assign data_in_axi_electrical_pos_err = {{13{read_reg_axi_electrical_pos_err[18]}}, read_reg_axi_electrical_pos_err}; + + + + assign decode_rd_axi_electrical_pos_err = (decode_sel_axi_electrical_pos_err == 1'b0 ? const_z : + data_in_axi_electrical_pos_err); + + + + assign data_read = decode_rd_axi_electrical_pos_err; + + assign data_in_axi_enable = data_write[0]; + + + + assign decode_sel_axi_enable = (addr_sel == 14'b00000000000001 ? 1'b1 : + 1'b0); + + + + assign reg_enb_axi_enable = decode_sel_axi_enable & wr_enb; + + + + always @(posedge CLK_IN) + begin : reg_axi_enable_process + if (reset == 1'b1) begin + write_reg_axi_enable <= 1'b1; + end + else if (enb && reg_enb_axi_enable) begin + write_reg_axi_enable <= data_in_axi_enable; + end + end + + + + assign write_axi_enable = write_reg_axi_enable; + + assign data_in_axi_controller_mode = data_write[1:0]; + + + + assign decode_sel_axi_controller_mode = (addr_sel == 14'b00000001000000 ? 1'b1 : + 1'b0); + + + + assign reg_enb_axi_controller_mode = decode_sel_axi_controller_mode & wr_enb; + + + + always @(posedge CLK_IN) + begin : reg_axi_controller_mode_process + if (reset == 1'b1) begin + write_reg_axi_controller_mode <= 2'b00; + end + else if (enb && reg_enb_axi_controller_mode) begin + write_reg_axi_controller_mode <= data_in_axi_controller_mode; + end + end + + + + assign write_axi_controller_mode = write_reg_axi_controller_mode; + + assign data_in_axi_command = $signed(data_write[17:0]); + + + + assign decode_sel_axi_command = (addr_sel == 14'b00000001000001 ? 1'b1 : + 1'b0); + + + + assign reg_enb_axi_command = decode_sel_axi_command & wr_enb; + + + + always @(posedge CLK_IN) + begin : reg_axi_command_process + if (reset == 1'b1) begin + write_reg_axi_command <= 18'sb000000000000000000; + end + else if (enb && reg_enb_axi_command) begin + write_reg_axi_command <= data_in_axi_command; + end + end + + + + assign write_axi_command = write_reg_axi_command; + + assign data_in_axi_velocity_p_gain = $signed(data_write[17:0]); + + + + assign decode_sel_axi_velocity_p_gain = (addr_sel == 14'b00000001000010 ? 1'b1 : + 1'b0); + + + + assign reg_enb_axi_velocity_p_gain = decode_sel_axi_velocity_p_gain & wr_enb; + + + + always @(posedge CLK_IN) + begin : reg_axi_velocity_p_gain_process + if (reset == 1'b1) begin + write_reg_axi_velocity_p_gain <= 18'sb000000000000000000; + end + else if (enb && reg_enb_axi_velocity_p_gain) begin + write_reg_axi_velocity_p_gain <= data_in_axi_velocity_p_gain; + end + end + + + + assign write_axi_velocity_p_gain = write_reg_axi_velocity_p_gain; + + assign data_in_axi_velocity_i_gain = $signed(data_write[17:0]); + + + + assign decode_sel_axi_velocity_i_gain = (addr_sel == 14'b00000001000011 ? 1'b1 : + 1'b0); + + + + assign reg_enb_axi_velocity_i_gain = decode_sel_axi_velocity_i_gain & wr_enb; + + + + always @(posedge CLK_IN) + begin : reg_axi_velocity_i_gain_process + if (reset == 1'b1) begin + write_reg_axi_velocity_i_gain <= 18'sb000000000000000000; + end + else if (enb && reg_enb_axi_velocity_i_gain) begin + write_reg_axi_velocity_i_gain <= data_in_axi_velocity_i_gain; + end + end + + + + assign write_axi_velocity_i_gain = write_reg_axi_velocity_i_gain; + + assign data_in_axi_current_p_gain = $signed(data_write[17:0]); + + + + assign decode_sel_axi_current_p_gain = (addr_sel == 14'b00000001000100 ? 1'b1 : + 1'b0); + + + + assign reg_enb_axi_current_p_gain = decode_sel_axi_current_p_gain & wr_enb; + + + + always @(posedge CLK_IN) + begin : reg_axi_current_p_gain_process + if (reset == 1'b1) begin + write_reg_axi_current_p_gain <= 18'sb000000000000000000; + end + else if (enb && reg_enb_axi_current_p_gain) begin + write_reg_axi_current_p_gain <= data_in_axi_current_p_gain; + end + end + + + + assign write_axi_current_p_gain = write_reg_axi_current_p_gain; + + assign data_in_axi_current_i_gain = $signed(data_write[17:0]); + + + + assign decode_sel_axi_current_i_gain = (addr_sel == 14'b00000001000101 ? 1'b1 : + 1'b0); + + + + assign reg_enb_axi_current_i_gain = decode_sel_axi_current_i_gain & wr_enb; + + + + always @(posedge CLK_IN) + begin : reg_axi_current_i_gain_process + if (reset == 1'b1) begin + write_reg_axi_current_i_gain <= 18'sb000000000000000000; + end + else if (enb && reg_enb_axi_current_i_gain) begin + write_reg_axi_current_i_gain <= data_in_axi_current_i_gain; + end + end + + + + assign write_axi_current_i_gain = write_reg_axi_current_i_gain; + + assign data_in_axi_open_loop_bias = $signed(data_write[17:0]); + + + + assign decode_sel_axi_open_loop_bias = (addr_sel == 14'b00000001000110 ? 1'b1 : + 1'b0); + + + + assign reg_enb_axi_open_loop_bias = decode_sel_axi_open_loop_bias & wr_enb; + + + + always @(posedge CLK_IN) + begin : reg_axi_open_loop_bias_process + if (reset == 1'b1) begin + write_reg_axi_open_loop_bias <= 18'sb000000000000000000; + end + else if (enb && reg_enb_axi_open_loop_bias) begin + write_reg_axi_open_loop_bias <= data_in_axi_open_loop_bias; + end + end + + + + assign write_axi_open_loop_bias = write_reg_axi_open_loop_bias; + + assign data_in_axi_open_loop_scalar = $signed(data_write[17:0]); + + + + assign decode_sel_axi_open_loop_scalar = (addr_sel == 14'b00000001000111 ? 1'b1 : + 1'b0); + + + + assign reg_enb_axi_open_loop_scalar = decode_sel_axi_open_loop_scalar & wr_enb; + + + + always @(posedge CLK_IN) + begin : reg_axi_open_loop_scalar_process + if (reset == 1'b1) begin + write_reg_axi_open_loop_scalar <= 18'sb000000000000000000; + end + else if (enb && reg_enb_axi_open_loop_scalar) begin + write_reg_axi_open_loop_scalar <= data_in_axi_open_loop_scalar; + end + end + + + + assign write_axi_open_loop_scalar = write_reg_axi_open_loop_scalar; + + assign data_in_axi_encoder_zero_offset = $signed(data_write[17:0]); + + + + assign decode_sel_axi_encoder_zero_offset = (addr_sel == 14'b00000001001000 ? 1'b1 : + 1'b0); + + + + assign reg_enb_axi_encoder_zero_offset = decode_sel_axi_encoder_zero_offset & wr_enb; + + + + always @(posedge CLK_IN) + begin : reg_axi_encoder_zero_offset_process + if (reset == 1'b1) begin + write_reg_axi_encoder_zero_offset <= 18'sb000000000000000000; + end + else if (enb && reg_enb_axi_encoder_zero_offset) begin + write_reg_axi_encoder_zero_offset <= data_in_axi_encoder_zero_offset; + end + end + + + + assign write_axi_encoder_zero_offset = write_reg_axi_encoder_zero_offset; + +endmodule // controllerperipheralhdladi_pcore_addr_decoder + diff --git a/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite.v b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite.v new file mode 100644 index 000000000..ee9f340f8 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite.v @@ -0,0 +1,180 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore_axi_lite.v +// Created: 2014-08-28 10:14:05 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerperipheralhdladi_pcore_axi_lite +// Source Path: controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite +// Hierarchy Level: 1 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerperipheralhdladi_pcore_axi_lite + ( + reset, + AXI_Lite_ACLK, + AXI_Lite_ARESETN, + AXI_Lite_AWADDR, + AXI_Lite_AWVALID, + AXI_Lite_WDATA, + AXI_Lite_WSTRB, + AXI_Lite_WVALID, + AXI_Lite_BREADY, + AXI_Lite_ARADDR, + AXI_Lite_ARVALID, + AXI_Lite_RREADY, + read_axi_electrical_pos_err, + AXI_Lite_AWREADY, + AXI_Lite_WREADY, + AXI_Lite_BRESP, + AXI_Lite_BVALID, + AXI_Lite_ARREADY, + AXI_Lite_RDATA, + AXI_Lite_RRESP, + AXI_Lite_RVALID, + write_axi_enable, + write_axi_controller_mode, + write_axi_command, + write_axi_velocity_p_gain, + write_axi_velocity_i_gain, + write_axi_current_p_gain, + write_axi_current_i_gain, + write_axi_open_loop_bias, + write_axi_open_loop_scalar, + write_axi_encoder_zero_offset, + reset_internal + ); + + + input reset; + input AXI_Lite_ACLK; // ufix1 + input AXI_Lite_ARESETN; // ufix1 + input [31:0] AXI_Lite_AWADDR; // ufix32 + input AXI_Lite_AWVALID; // ufix1 + input [31:0] AXI_Lite_WDATA; // ufix32 + input [3:0] AXI_Lite_WSTRB; // ufix4 + input AXI_Lite_WVALID; // ufix1 + input AXI_Lite_BREADY; // ufix1 + input [31:0] AXI_Lite_ARADDR; // ufix32 + input AXI_Lite_ARVALID; // ufix1 + input AXI_Lite_RREADY; // ufix1 + input signed [18:0] read_axi_electrical_pos_err; // sfix19_En14 + output AXI_Lite_AWREADY; // ufix1 + output AXI_Lite_WREADY; // ufix1 + output [1:0] AXI_Lite_BRESP; // ufix2 + output AXI_Lite_BVALID; // ufix1 + output AXI_Lite_ARREADY; // ufix1 + output [31:0] AXI_Lite_RDATA; // ufix32 + output [1:0] AXI_Lite_RRESP; // ufix2 + output AXI_Lite_RVALID; // ufix1 + output write_axi_enable; // ufix1 + output [1:0] write_axi_controller_mode; // ufix2 + output signed [17:0] write_axi_command; // sfix18_En8 + output signed [17:0] write_axi_velocity_p_gain; // sfix18_En16 + output signed [17:0] write_axi_velocity_i_gain; // sfix18_En15 + output signed [17:0] write_axi_current_p_gain; // sfix18_En10 + output signed [17:0] write_axi_current_i_gain; // sfix18_En2 + output signed [17:0] write_axi_open_loop_bias; // sfix18_En14 + output signed [17:0] write_axi_open_loop_scalar; // sfix18_En16 + output signed [17:0] write_axi_encoder_zero_offset; // sfix18_En14 + output reset_internal; // ufix1 + + + wire [31:0] top_data_write; // ufix32 + wire [13:0] top_addr_sel; // ufix14 + wire top_wr_enb; // ufix1 + wire top_rd_enb; // ufix1 + wire [31:0] top_data_read; // ufix32 + wire inst_axi_enable; // ufix1 + wire [1:0] inst_axi_controller_mode; // ufix2 + wire signed [17:0] inst_axi_command; // sfix18_En8 + wire signed [17:0] inst_axi_velocity_p_gain; // sfix18_En16 + wire signed [17:0] inst_axi_velocity_i_gain; // sfix18_En15 + wire signed [17:0] inst_axi_current_p_gain; // sfix18_En10 + wire signed [17:0] inst_axi_current_i_gain; // sfix18_En2 + wire signed [17:0] inst_axi_open_loop_bias; // sfix18_En14 + wire signed [17:0] inst_axi_open_loop_scalar; // sfix18_En16 + wire signed [17:0] inst_axi_encoder_zero_offset; // sfix18_En14 + wire top_reset_internal; // ufix1 + + + controllerperipheralhdladi_pcore_addr_decoder u_controllerperipheralhdladi_pcore_addr_decoder_inst (.CLK_IN(AXI_Lite_ACLK), // ufix1 + .reset(reset), + .data_write(top_data_write), // ufix32 + .addr_sel(top_addr_sel), // ufix14 + .wr_enb(top_wr_enb), // ufix1 + .rd_enb(top_rd_enb), // ufix1 + .read_axi_electrical_pos_err(read_axi_electrical_pos_err), // sfix19_En14 + .data_read(top_data_read), // ufix32 + .write_axi_enable(inst_axi_enable), // ufix1 + .write_axi_controller_mode(inst_axi_controller_mode), // ufix2 + .write_axi_command(inst_axi_command), // sfix18_En8 + .write_axi_velocity_p_gain(inst_axi_velocity_p_gain), // sfix18_En16 + .write_axi_velocity_i_gain(inst_axi_velocity_i_gain), // sfix18_En15 + .write_axi_current_p_gain(inst_axi_current_p_gain), // sfix18_En10 + .write_axi_current_i_gain(inst_axi_current_i_gain), // sfix18_En2 + .write_axi_open_loop_bias(inst_axi_open_loop_bias), // sfix18_En14 + .write_axi_open_loop_scalar(inst_axi_open_loop_scalar), // sfix18_En16 + .write_axi_encoder_zero_offset(inst_axi_encoder_zero_offset) // sfix18_En14 + ); + + controllerperipheralhdladi_pcore_axi_lite_module u_controllerperipheralhdladi_pcore_axi_lite_module_inst (.CLK_IN(AXI_Lite_ACLK), // ufix1 + .AXI_Lite_ARESETN(AXI_Lite_ARESETN), // ufix1 + .AXI_Lite_AWADDR(AXI_Lite_AWADDR), // ufix32 + .AXI_Lite_AWVALID(AXI_Lite_AWVALID), // ufix1 + .AXI_Lite_WDATA(AXI_Lite_WDATA), // ufix32 + .AXI_Lite_WSTRB(AXI_Lite_WSTRB), // ufix4 + .AXI_Lite_WVALID(AXI_Lite_WVALID), // ufix1 + .AXI_Lite_BREADY(AXI_Lite_BREADY), // ufix1 + .AXI_Lite_ARADDR(AXI_Lite_ARADDR), // ufix32 + .AXI_Lite_ARVALID(AXI_Lite_ARVALID), // ufix1 + .AXI_Lite_RREADY(AXI_Lite_RREADY), // ufix1 + .data_read(top_data_read), // ufix32 + .AXI_Lite_AWREADY(AXI_Lite_AWREADY), // ufix1 + .AXI_Lite_WREADY(AXI_Lite_WREADY), // ufix1 + .AXI_Lite_BRESP(AXI_Lite_BRESP), // ufix2 + .AXI_Lite_BVALID(AXI_Lite_BVALID), // ufix1 + .AXI_Lite_ARREADY(AXI_Lite_ARREADY), // ufix1 + .AXI_Lite_RDATA(AXI_Lite_RDATA), // ufix32 + .AXI_Lite_RRESP(AXI_Lite_RRESP), // ufix2 + .AXI_Lite_RVALID(AXI_Lite_RVALID), // ufix1 + .data_write(top_data_write), // ufix32 + .addr_sel(top_addr_sel), // ufix14 + .wr_enb(top_wr_enb), // ufix1 + .rd_enb(top_rd_enb), // ufix1 + .reset_internal(top_reset_internal) // ufix1 + ); + + assign write_axi_enable = inst_axi_enable; + + assign write_axi_controller_mode = inst_axi_controller_mode; + + assign write_axi_command = inst_axi_command; + + assign write_axi_velocity_p_gain = inst_axi_velocity_p_gain; + + assign write_axi_velocity_i_gain = inst_axi_velocity_i_gain; + + assign write_axi_current_p_gain = inst_axi_current_p_gain; + + assign write_axi_current_i_gain = inst_axi_current_i_gain; + + assign write_axi_open_loop_bias = inst_axi_open_loop_bias; + + assign write_axi_open_loop_scalar = inst_axi_open_loop_scalar; + + assign write_axi_encoder_zero_offset = inst_axi_encoder_zero_offset; + + assign reset_internal = top_reset_internal; + +endmodule // controllerperipheralhdladi_pcore_axi_lite + diff --git a/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite_module.v b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite_module.v new file mode 100644 index 000000000..41aadde25 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite_module.v @@ -0,0 +1,373 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore_axi_lite_module.v +// Created: 2014-08-28 10:14:05 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerperipheralhdladi_pcore_axi_lite_module +// Source Path: controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite/controllerperipheralhdladi_pcore_axi_lite_module +// Hierarchy Level: 2 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerperipheralhdladi_pcore_axi_lite_module + ( + CLK_IN, + AXI_Lite_ARESETN, + AXI_Lite_AWADDR, + AXI_Lite_AWVALID, + AXI_Lite_WDATA, + AXI_Lite_WSTRB, + AXI_Lite_WVALID, + AXI_Lite_BREADY, + AXI_Lite_ARADDR, + AXI_Lite_ARVALID, + AXI_Lite_RREADY, + data_read, + AXI_Lite_AWREADY, + AXI_Lite_WREADY, + AXI_Lite_BRESP, + AXI_Lite_BVALID, + AXI_Lite_ARREADY, + AXI_Lite_RDATA, + AXI_Lite_RRESP, + AXI_Lite_RVALID, + data_write, + addr_sel, + wr_enb, + rd_enb, + reset_internal + ); + + + input CLK_IN; + input AXI_Lite_ARESETN; // ufix1 + input [31:0] AXI_Lite_AWADDR; // ufix32 + input AXI_Lite_AWVALID; // ufix1 + input [31:0] AXI_Lite_WDATA; // ufix32 + input [3:0] AXI_Lite_WSTRB; // ufix4 + input AXI_Lite_WVALID; // ufix1 + input AXI_Lite_BREADY; // ufix1 + input [31:0] AXI_Lite_ARADDR; // ufix32 + input AXI_Lite_ARVALID; // ufix1 + input AXI_Lite_RREADY; // ufix1 + input [31:0] data_read; // ufix32 + output AXI_Lite_AWREADY; // ufix1 + output AXI_Lite_WREADY; // ufix1 + output [1:0] AXI_Lite_BRESP; // ufix2 + output AXI_Lite_BVALID; // ufix1 + output AXI_Lite_ARREADY; // ufix1 + output [31:0] AXI_Lite_RDATA; // ufix32 + output [1:0] AXI_Lite_RRESP; // ufix2 + output AXI_Lite_RVALID; // ufix1 + output [31:0] data_write; // ufix32 + output [13:0] addr_sel; // ufix14 + output wr_enb; // ufix1 + output rd_enb; // ufix1 + output reset_internal; // ufix1 + + + wire reset; + wire enb; + wire const_1; // ufix1 + reg [7:0] axi_lite_wstate; // uint8 + reg [7:0] axi_lite_rstate; // uint8 + reg [7:0] axi_lite_wstate_next; // uint8 + reg [7:0] axi_lite_rstate_next; // uint8 + reg AXI_Lite_AWREADY_1; // ufix1 + reg AXI_Lite_WREADY_1; // ufix1 + reg AXI_Lite_BVALID_1; // ufix1 + reg AXI_Lite_ARREADY_1; // ufix1 + reg AXI_Lite_RVALID_1; // ufix1 + reg aw_transfer; // ufix1 + reg w_transfer; // ufix1 + reg ar_transfer; // ufix1 + wire [1:0] const_0_2; // ufix2 + reg [31:0] AXI_Lite_RDATA_1; // ufix32 + reg [31:0] wdata; // ufix32 + reg [31:0] waddr; // ufix32 + wire [13:0] waddr_sel; // ufix14 + wire [13:0] raddr_sel; // ufix14 + reg wr_enb_1; // ufix1 + wire strobe_addr; // ufix1 + wire strobe_sel; // ufix1 + wire const_zero; // ufix1 + wire strobe_in; // ufix1 + wire strobe_sw; // ufix1 + reg soft_reset; // ufix1 + reg axi_lite_out0_0_1; + reg axi_lite_out1_0_1; + reg axi_lite_out3_0_1; + reg axi_lite_awvalid_1; + reg axi_lite_wvalid_1; + reg axi_lite_arvalid_1; + + + assign const_1 = 1'b1; + + + + assign enb = const_1; + + assign reset = ~ AXI_Lite_ARESETN; + + + + always @(posedge CLK_IN) + begin : axi_lite_process + if (reset == 1'b1) begin + axi_lite_wstate <= 8'd0; + axi_lite_rstate <= 8'd0; + end + else if (enb) begin + axi_lite_wstate <= axi_lite_wstate_next; + axi_lite_rstate <= axi_lite_rstate_next; + end + end + + always @(axi_lite_wstate, axi_lite_rstate, AXI_Lite_AWVALID, AXI_Lite_WVALID, + AXI_Lite_BREADY, AXI_Lite_ARVALID, AXI_Lite_RREADY) begin + axi_lite_wstate_next = axi_lite_wstate; + axi_lite_rstate_next = axi_lite_rstate; + if (AXI_Lite_AWVALID != 1'b0) begin + axi_lite_awvalid_1 = 1'b1; + end + else begin + axi_lite_awvalid_1 = 1'b0; + end + if (AXI_Lite_WVALID != 1'b0) begin + axi_lite_wvalid_1 = 1'b1; + end + else begin + axi_lite_wvalid_1 = 1'b0; + end + if (AXI_Lite_ARVALID != 1'b0) begin + axi_lite_arvalid_1 = 1'b1; + end + else begin + axi_lite_arvalid_1 = 1'b0; + end + + case ( axi_lite_wstate) + 8'd0 : + begin + axi_lite_out0_0_1 = 1'b1; + axi_lite_out1_0_1 = 1'b0; + AXI_Lite_BVALID_1 = 1'b0; + if (axi_lite_awvalid_1) begin + axi_lite_wstate_next = 8'd1; + end + else begin + axi_lite_wstate_next = 8'd0; + end + end + 8'd1 : + begin + axi_lite_out0_0_1 = 1'b0; + axi_lite_out1_0_1 = 1'b1; + AXI_Lite_BVALID_1 = 1'b0; + if (axi_lite_wvalid_1) begin + axi_lite_wstate_next = 8'd2; + end + else begin + axi_lite_wstate_next = 8'd1; + end + end + 8'd2 : + begin + axi_lite_out0_0_1 = 1'b0; + axi_lite_out1_0_1 = 1'b0; + AXI_Lite_BVALID_1 = 1'b1; + if (AXI_Lite_BREADY != 1'b0) begin + axi_lite_wstate_next = 8'd0; + end + else begin + axi_lite_wstate_next = 8'd2; + end + end + default : + begin + axi_lite_out0_0_1 = 1'b0; + axi_lite_out1_0_1 = 1'b0; + AXI_Lite_BVALID_1 = 1'b0; + axi_lite_wstate_next = 8'd0; + end + endcase + + + case ( axi_lite_rstate) + 8'd0 : + begin + axi_lite_out3_0_1 = 1'b1; + AXI_Lite_RVALID_1 = 1'b0; + if (axi_lite_arvalid_1) begin + axi_lite_rstate_next = 8'd1; + end + else begin + axi_lite_rstate_next = 8'd0; + end + end + 8'd1 : + begin + axi_lite_out3_0_1 = 1'b0; + AXI_Lite_RVALID_1 = 1'b1; + if (AXI_Lite_RREADY != 1'b0) begin + axi_lite_rstate_next = 8'd0; + end + else begin + axi_lite_rstate_next = 8'd1; + end + end + default : + begin + axi_lite_out3_0_1 = 1'b0; + AXI_Lite_RVALID_1 = 1'b0; + axi_lite_rstate_next = 8'd0; + end + endcase + + AXI_Lite_AWREADY_1 = axi_lite_out0_0_1; + AXI_Lite_WREADY_1 = axi_lite_out1_0_1; + AXI_Lite_ARREADY_1 = axi_lite_out3_0_1; + aw_transfer = axi_lite_awvalid_1 && axi_lite_out0_0_1; + w_transfer = axi_lite_wvalid_1 && axi_lite_out1_0_1; + ar_transfer = axi_lite_arvalid_1 && axi_lite_out3_0_1; + end + + + + assign const_0_2 = 2'b00; + + + + assign AXI_Lite_BRESP = const_0_2; + + always @(posedge CLK_IN) + begin : reg_rdata_process + if (reset == 1'b1) begin + AXI_Lite_RDATA_1 <= 32'b00000000000000000000000000000000; + end + else if (enb && ar_transfer) begin + AXI_Lite_RDATA_1 <= data_read; + end + end + + + + assign AXI_Lite_RRESP = const_0_2; + + always @(posedge CLK_IN) + begin : reg_wdata_process + if (reset == 1'b1) begin + wdata <= 32'b00000000000000000000000000000000; + end + else if (enb && w_transfer) begin + wdata <= AXI_Lite_WDATA; + end + end + + + + assign data_write = wdata; + + always @(posedge CLK_IN) + begin : reg_waddr_process + if (reset == 1'b1) begin + waddr <= 32'b00000000000000000000000000000000; + end + else if (enb && aw_transfer) begin + waddr <= AXI_Lite_AWADDR; + end + end + + + + assign waddr_sel = waddr[15:2]; + + + + assign raddr_sel = AXI_Lite_ARADDR[15:2]; + + + + assign addr_sel = (AXI_Lite_ARVALID == 1'b0 ? waddr_sel : + raddr_sel); + + + + always @(posedge CLK_IN) + begin : reg_wr_enb_process + if (reset == 1'b1) begin + wr_enb_1 <= 1'b0; + end + else if (enb) begin + wr_enb_1 <= w_transfer; + end + end + + + + assign rd_enb = ar_transfer; + + assign strobe_addr = (waddr_sel == 14'b00000000000000 ? 1'b1 : + 1'b0); + + + + assign strobe_sel = strobe_addr & wr_enb_1; + + + + assign const_zero = 1'b0; + + + + assign strobe_in = wdata[0]; + + + + assign strobe_sw = (strobe_sel == 1'b0 ? const_zero : + strobe_in); + + + + always @(posedge CLK_IN) + begin : reg_rsvd_process + if (reset == 1'b1) begin + soft_reset <= 1'b0; + end + else if (enb) begin + soft_reset <= strobe_sw; + end + end + + + + assign reset_internal = reset | soft_reset; + + + + assign AXI_Lite_AWREADY = AXI_Lite_AWREADY_1; + + assign AXI_Lite_WREADY = AXI_Lite_WREADY_1; + + assign AXI_Lite_BVALID = AXI_Lite_BVALID_1; + + assign AXI_Lite_ARREADY = AXI_Lite_ARREADY_1; + + assign AXI_Lite_RDATA = AXI_Lite_RDATA_1; + + assign AXI_Lite_RVALID = AXI_Lite_RVALID_1; + + assign wr_enb = wr_enb_1; + +endmodule // controllerperipheralhdladi_pcore_axi_lite_module + diff --git a/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_dut.v b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_dut.v new file mode 100644 index 000000000..44604076e --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_dut.v @@ -0,0 +1,177 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore_dut.v +// Created: 2014-08-28 10:14:05 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: controllerperipheralhdladi_pcore_dut +// Source Path: controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_dut +// Hierarchy Level: 1 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module controllerperipheralhdladi_pcore_dut + ( + CLK_IN, + reset, + dut_enable, + adc_current1, + adc_current2, + encoder_a, + encoder_b, + encoder_index, + axi_controller_mode, + axi_command, + axi_velocity_p_gain, + axi_velocity_i_gain, + axi_current_p_gain, + axi_current_i_gain, + axi_open_loop_bias, + axi_open_loop_scalar, + axi_encoder_zero_offset, + ce_out_0, + ce_out_1, + pwm_a, + pwm_b, + pwm_c, + mon_phase_voltage_a, + mon_phase_voltage_b, + mon_phase_current_a, + mon_phase_current_b, + mon_rotor_position, + mon_electrical_position, + mon_rotor_velocity, + mon_d_current, + mon_q_current, + axi_electrical_pos_err + ); + + + input CLK_IN; + input reset; + input dut_enable; // ufix1 + input signed [17:0] adc_current1; // sfix18_En17 + input signed [17:0] adc_current2; // sfix18_En17 + input encoder_a; // ufix1 + input encoder_b; // ufix1 + input encoder_index; // ufix1 + input [1:0] axi_controller_mode; // ufix2 + input signed [17:0] axi_command; // sfix18_En8 + input signed [17:0] axi_velocity_p_gain; // sfix18_En16 + input signed [17:0] axi_velocity_i_gain; // sfix18_En15 + input signed [17:0] axi_current_p_gain; // sfix18_En10 + input signed [17:0] axi_current_i_gain; // sfix18_En2 + input signed [17:0] axi_open_loop_bias; // sfix18_En14 + input signed [17:0] axi_open_loop_scalar; // sfix18_En16 + input signed [17:0] axi_encoder_zero_offset; // sfix18_En14 + output ce_out_0; // ufix1 + output ce_out_1; // ufix1 + output pwm_a; // ufix1 + output pwm_b; // ufix1 + output pwm_c; // ufix1 + output signed [31:0] mon_phase_voltage_a; // sfix32 + output signed [31:0] mon_phase_voltage_b; // sfix32 + output signed [31:0] mon_phase_current_a; // sfix32 + output signed [31:0] mon_phase_current_b; // sfix32 + output signed [31:0] mon_rotor_position; // sfix32 + output signed [31:0] mon_electrical_position; // sfix32 + output signed [31:0] mon_rotor_velocity; // sfix32 + output signed [31:0] mon_d_current; // sfix32 + output signed [31:0] mon_q_current; // sfix32 + output signed [18:0] axi_electrical_pos_err; // sfix19_En14 + + + wire enb; + wire ce_out_0_sig; // ufix1 + wire ce_out_1_sig; // ufix1 + wire pwm_a_sig; // ufix1 + wire pwm_b_sig; // ufix1 + wire pwm_c_sig; // ufix1 + wire signed [31:0] mon_phase_voltage_a_sig; // sfix32 + wire signed [31:0] mon_phase_voltage_b_sig; // sfix32 + wire signed [31:0] mon_phase_current_a_sig; // sfix32 + wire signed [31:0] mon_phase_current_b_sig; // sfix32 + wire signed [31:0] mon_rotor_position_sig; // sfix32 + wire signed [31:0] mon_electrical_position_sig; // sfix32 + wire signed [31:0] mon_rotor_velocity_sig; // sfix32 + wire signed [31:0] mon_d_current_sig; // sfix32 + wire signed [31:0] mon_q_current_sig; // sfix32 + wire signed [18:0] axi_electrical_pos_err_sig; // sfix19_En14 + + + assign enb = dut_enable; + + controllerPeripheralHdlAdi u_controllerPeripheralHdlAdi (.CLK_IN(CLK_IN), + .clk_enable(enb), + .reset(reset), + .adc_current1(adc_current1), // sfix18_En17 + .adc_current2(adc_current2), // sfix18_En17 + .encoder_a(encoder_a), // ufix1 + .encoder_b(encoder_b), // ufix1 + .encoder_index(encoder_index), // ufix1 + .axi_controller_mode(axi_controller_mode), // ufix2 + .axi_command(axi_command), // sfix18_En8 + .axi_velocity_p_gain(axi_velocity_p_gain), // sfix18_En16 + .axi_velocity_i_gain(axi_velocity_i_gain), // sfix18_En15 + .axi_current_p_gain(axi_current_p_gain), // sfix18_En10 + .axi_current_i_gain(axi_current_i_gain), // sfix18_En2 + .axi_open_loop_bias(axi_open_loop_bias), // sfix18_En14 + .axi_open_loop_scalar(axi_open_loop_scalar), // sfix18_En16 + .axi_encoder_zero_offset(axi_encoder_zero_offset), // sfix18_En14 + .ce_out_0(ce_out_0_sig), // ufix1 + .ce_out_1(ce_out_1_sig), // ufix1 + .pwm_a(pwm_a_sig), // ufix1 + .pwm_b(pwm_b_sig), // ufix1 + .pwm_c(pwm_c_sig), // ufix1 + .mon_phase_voltage_a(mon_phase_voltage_a_sig), // sfix32 + .mon_phase_voltage_b(mon_phase_voltage_b_sig), // sfix32 + .mon_phase_current_a(mon_phase_current_a_sig), // sfix32 + .mon_phase_current_b(mon_phase_current_b_sig), // sfix32 + .mon_rotor_position(mon_rotor_position_sig), // sfix32 + .mon_electrical_position(mon_electrical_position_sig), // sfix32 + .mon_rotor_velocity(mon_rotor_velocity_sig), // sfix32 + .mon_d_current(mon_d_current_sig), // sfix32 + .mon_q_current(mon_q_current_sig), // sfix32 + .axi_electrical_pos_err(axi_electrical_pos_err_sig) // sfix19_En14 + ); + + assign ce_out_0 = ce_out_0_sig; + + assign ce_out_1 = ce_out_1_sig; + + assign pwm_a = pwm_a_sig; + + assign pwm_b = pwm_b_sig; + + assign pwm_c = pwm_c_sig; + + assign mon_phase_voltage_a = mon_phase_voltage_a_sig; + + assign mon_phase_voltage_b = mon_phase_voltage_b_sig; + + assign mon_phase_current_a = mon_phase_current_a_sig; + + assign mon_phase_current_b = mon_phase_current_b_sig; + + assign mon_rotor_position = mon_rotor_position_sig; + + assign mon_electrical_position = mon_electrical_position_sig; + + assign mon_rotor_velocity = mon_rotor_velocity_sig; + + assign mon_d_current = mon_d_current_sig; + + assign mon_q_current = mon_q_current_sig; + + assign axi_electrical_pos_err = axi_electrical_pos_err_sig; + +endmodule // controllerperipheralhdladi_pcore_dut + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clamp.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clamp.v new file mode 100644 index 000000000..7fdcddeed --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clamp.v @@ -0,0 +1,67 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clamp.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Clamp +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Clamp +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Clamp + ( + preIntegrator, + preSat, + saturated, + Clamp + ); + + + input signed [35:0] preIntegrator; // sfix36_En29 + input signed [35:0] preSat; // sfix36_En23 + input saturated; + output Clamp; + + + wire Compare_To_Zero_out1; + wire Compare_To_Zero1_out1; + wire Compare_To_Zero_out1_1; + wire Logical_Operator_out1; + + + // /Compare To Zero + assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 : + 1'b0); + + + + // /Compare To Zero1 + assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 : + 1'b0); + + + + // /Logical Operator + assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1); + + + + // /AND + assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated; + + + + assign Clamp = Logical_Operator_out1; + +endmodule // velocityControlHdl_Clamp + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clamp_block.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clamp_block.v new file mode 100644 index 000000000..d087b1801 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clamp_block.v @@ -0,0 +1,67 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clamp_block.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Clamp_block +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Clamp +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Clamp_block + ( + preIntegrator, + preSat, + saturated, + Clamp + ); + + + input signed [35:0] preIntegrator; // sfix36_En29 + input signed [35:0] preSat; // sfix36_En23 + input saturated; + output Clamp; + + + wire Compare_To_Zero_out1; + wire Compare_To_Zero1_out1; + wire Compare_To_Zero_out1_1; + wire Logical_Operator_out1; + + + // /Compare To Zero + assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 : + 1'b0); + + + + // /Compare To Zero1 + assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 : + 1'b0); + + + + // /Logical Operator + assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1); + + + + // /AND + assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated; + + + + assign Clamp = Logical_Operator_out1; + +endmodule // velocityControlHdl_Clamp_block + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clamp_block1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clamp_block1.v new file mode 100644 index 000000000..62ff5739e --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clamp_block1.v @@ -0,0 +1,67 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clamp_block1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Clamp_block1 +// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Clamp +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Clamp_block1 + ( + preSat, + saturated, + preIntegrator, + Clamp + ); + + + input signed [35:0] preSat; // sfix36_En22 + input saturated; + input signed [35:0] preIntegrator; // sfix36_En35 + output Clamp; + + + wire Compare_To_Zero_out1; + wire Compare_To_Zero1_out1; + wire Compare_To_Zero_out1_1; + wire Logical_Operator_out1; + + + // /Compare To Zero + assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 : + 1'b0); + + + + // /Compare To Zero1 + assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 : + 1'b0); + + + + // /Logical Operator + assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1); + + + + // /AND + assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated; + + + + assign Clamp = Logical_Operator_out1; + +endmodule // velocityControlHdl_Clamp_block1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clarke_Transform.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clarke_Transform.v new file mode 100644 index 000000000..ec936af1a --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clarke_Transform.v @@ -0,0 +1,83 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clarke_Transform.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Clarke_Transform +// Source Path: velocityControlHdl/Transform_ABC_to_dq/Clarke_Transform +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Clarke_Transform + ( + phase_currents_0, + phase_currents_1, + alpha_current, + beta_current + ); + + + input signed [17:0] phase_currents_0; // sfix18_En15 + input signed [17:0] phase_currents_1; // sfix18_En15 + output signed [17:0] alpha_current; // sfix18_En13 + output signed [17:0] beta_current; // sfix18_En13 + + + wire signed [17:0] Alpha_Current_Data_Type_out1; // sfix18_En13 + wire signed [35:0] Alpha_Gain_With_Headrom_out1; // sfix36_En31 + wire signed [35:0] Beta_Gain_With_Headrom_out1; // sfix36_En31 + wire signed [35:0] Add_out1; // sfix36_En31 + wire signed [17:0] Beta_Current_Data_Type_out1; // sfix18_En13 + + // Converts balanced three-phase quantities into balanced two-phase quantities. + // The A and B phases are converted to the direct axis (alpha) component and the quadrature axis (beta) component. + // The alpha and beta components are still dependent on time and speed. + // + // Clarke Transform + + + // /Alpha_Current_Data_Type + // + // /A_phase_current + // + // /B_phase_current + assign Alpha_Current_Data_Type_out1 = {{2{phase_currents_0[17]}}, phase_currents_0[17:2]}; + + + + assign alpha_current = Alpha_Current_Data_Type_out1; + + // /Alpha_Gain_With_Headrom + assign Alpha_Gain_With_Headrom_out1 = 37837 * phase_currents_0; + + + + // /Beta_Gain_With_Headrom + assign Beta_Gain_With_Headrom_out1 = 75674 * phase_currents_1; + + + + // /Add + assign Add_out1 = Alpha_Gain_With_Headrom_out1 + Beta_Gain_With_Headrom_out1; + + + + // /Beta_Current_Data_Type + assign Beta_Current_Data_Type_out1 = Add_out1[35:18]; + + + + assign beta_current = Beta_Current_Data_Type_out1; + +endmodule // velocityControlHdl_Clarke_Transform + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Complex_Multiply.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Complex_Multiply.v new file mode 100644 index 000000000..1425f6c80 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Complex_Multiply.v @@ -0,0 +1,87 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Complex_Multiply.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Complex_Multiply +// Source Path: velocityControlHdl/Sin_Cos1/Complex_Multiply +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Complex_Multiply + ( + In1_re, + In1_im, + In2_re, + In2_im, + Re, + Im + ); + + + input signed [17:0] In1_re; // sfix18_En16 + input signed [17:0] In1_im; // sfix18_En16 + input signed [17:0] In2_re; // sfix18_En16 + input signed [17:0] In2_im; // sfix18_En16 + output signed [35:0] Re; // sfix36_En32 + output signed [35:0] Im; // sfix36_En32 + + + wire signed [35:0] Product_out1; // sfix36_En32 + wire signed [35:0] Product1_out1; // sfix36_En32 + wire signed [35:0] Add1_out1; // sfix36_En32 + wire signed [35:0] Product2_out1; // sfix36_En32 + wire signed [35:0] Product3_out1; // sfix36_En32 + wire signed [35:0] Add2_out1; // sfix36_En32 + + + // /Product + // + // /Complex to Real-Imag1 + // + // /Complex to Real-Imag2 + assign Product_out1 = In1_re * In2_re; + + + + // /Product1 + assign Product1_out1 = In1_im * In2_im; + + + + // /Add1 + assign Add1_out1 = Product_out1 - Product1_out1; + + + + assign Re = Add1_out1; + + // /Product2 + assign Product2_out1 = In1_re * In2_im; + + + + // /Product3 + assign Product3_out1 = In1_im * In2_re; + + + + // /Add2 + assign Add2_out1 = Product2_out1 + Product3_out1; + + + + assign Im = Add2_out1; + +endmodule // velocityControlHdl_Complex_Multiply + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Current.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Current.v new file mode 100644 index 000000000..a51bd9ee4 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Current.v @@ -0,0 +1,164 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_Current.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Control_Current +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Control_Current + ( + CLK_IN, + reset, + enb_1_2000_0, + Reest, + Err, + param_current_p_gain, + param_current_i_gain, + Out + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reest; + input signed [17:0] Err; // sfix18_En14 + input signed [17:0] param_current_p_gain; // sfix18_En10 + input signed [17:0] param_current_i_gain; // sfix18_En2 + output signed [17:0] Out; // sfix18_En12 + + + wire signed [35:0] Product2_out1; // sfix36_En24 + wire signed [35:0] Convert_Data_Type1_out1; // sfix36_En23 + wire signed [17:0] Constant2_out1; // sfix18_En31 + wire signed [35:0] Product_out1; // sfix36_En33 + wire signed [17:0] pre_integrator; // sfix18_En15 + wire signed [35:0] pre_integrator_1; // sfix36_En29 + wire signed [35:0] Constant_out1; // sfix36_En29 + wire signed [35:0] u; // sfix36_En23 + wire PI_Sat_out2; + wire Clamp_out1; + wire switch_compare_1; + wire signed [35:0] Switch_out1; // sfix36_En29 + wire signed [31:0] I_term; // sfix32_En26 + wire signed [36:0] Add_add_cast; // sfix37_En29 + wire signed [36:0] Add_add_cast_1; // sfix37_En29 + wire signed [36:0] Add_add_temp; // sfix37_En29 + wire signed [31:0] Add_out1; // sfix32_En26 + wire signed [39:0] Sum1_add_cast; // sfix40_En26 + wire signed [39:0] Sum1_add_cast_1; // sfix40_En26 + wire signed [39:0] Sum1_add_temp; // sfix40_En26 + wire signed [35:0] u_sat; // sfix36_En23 + wire signed [17:0] D_Data_Type_out1; // sfix18_En12 + + // Control Current + + + // /Product2 + assign Product2_out1 = param_current_p_gain * Err; + + + + // /Convert_Data_Type1 + velocityControlHdl_Convert_Data_Type1 u_Convert_Data_Type1 (.In1(Product2_out1), // sfix36_En24 + .Out1(Convert_Data_Type1_out1) // sfix36_En23 + ); + + // /Constant2 + assign Constant2_out1 = 18'sb010100111110001011; + + + + // /Product + assign Product_out1 = param_current_i_gain * Constant2_out1; + + + + // /Maintain_Range + velocityControlHdl_Maintain_Range u_Maintain_Range (.In1(Product_out1), // sfix36_En33 + .Out1(pre_integrator) // sfix18_En15 + ); + + // /Product1 + assign pre_integrator_1 = Err * pre_integrator; + + + + // /Constant + assign Constant_out1 = 36'sh000000000; + + + + // /Clamp + velocityControlHdl_Clamp u_Clamp (.preIntegrator(pre_integrator_1), // sfix36_En29 + .preSat(u), // sfix36_En23 + .saturated(PI_Sat_out2), + .Clamp(Clamp_out1) + ); + + assign switch_compare_1 = (Clamp_out1 > 1'b0 ? 1'b1 : + 1'b0); + + + + // /Switch + assign Switch_out1 = (switch_compare_1 == 1'b0 ? pre_integrator_1 : + Constant_out1); + + + + // /Add + assign Add_add_cast = Switch_out1; + assign Add_add_cast_1 = {{2{I_term[31]}}, {I_term, 3'b000}}; + assign Add_add_temp = Add_add_cast + Add_add_cast_1; + assign Add_out1 = ((Add_add_temp[36] == 1'b0) && (Add_add_temp[35:34] != 2'b00) ? 32'sb01111111111111111111111111111111 : + ((Add_add_temp[36] == 1'b1) && (Add_add_temp[35:34] != 2'b11) ? 32'sb10000000000000000000000000000000 : + $signed(Add_add_temp[34:3]))); + + + + // /Reset_Delay + velocityControlHdl_Reset_Delay u_Reset_Delay (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(Reest), + .In(Add_out1), // sfix32_En26 + .Out(I_term) // sfix32_En26 + ); + + // /Sum1 + assign Sum1_add_cast = {Convert_Data_Type1_out1[35], {Convert_Data_Type1_out1, 3'b000}}; + assign Sum1_add_cast_1 = I_term; + assign Sum1_add_temp = Sum1_add_cast + Sum1_add_cast_1; + assign u = Sum1_add_temp[38:3]; + + + + // /PI_Sat + velocityControlHdl_PI_Sat u_PI_Sat (.In1(u), // sfix36_En23 + .Out1(u_sat), // sfix36_En23 + .saturated(PI_Sat_out2) + ); + + // /D_Data_Type + assign D_Data_Type_out1 = u_sat[28:11]; + + + + assign Out = D_Data_Type_out1; + +endmodule // velocityControlHdl_Control_Current + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Current1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Current1.v new file mode 100644 index 000000000..f870a4b6f --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Current1.v @@ -0,0 +1,164 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_Current1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Control_Current1 +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1 +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Control_Current1 + ( + CLK_IN, + reset, + enb_1_2000_0, + Reest, + Err, + param_current_p_gain, + param_current_i_gain, + Out + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reest; + input signed [17:0] Err; // sfix18_En14 + input signed [17:0] param_current_p_gain; // sfix18_En10 + input signed [17:0] param_current_i_gain; // sfix18_En2 + output signed [17:0] Out; // sfix18_En12 + + + wire signed [35:0] Product2_out1; // sfix36_En24 + wire signed [35:0] Convert_Data_Type1_out1; // sfix36_En23 + wire signed [17:0] Constant2_out1; // sfix18_En31 + wire signed [35:0] Product_out1; // sfix36_En33 + wire signed [17:0] pre_integrator; // sfix18_En15 + wire signed [35:0] pre_integrator_1; // sfix36_En29 + wire signed [35:0] Constant_out1; // sfix36_En29 + wire signed [35:0] u; // sfix36_En23 + wire PI_Sat_out2; + wire Clamp_out1; + wire switch_compare_1; + wire signed [35:0] Switch_out1; // sfix36_En29 + wire signed [31:0] I_term; // sfix32_En26 + wire signed [36:0] Add_add_cast; // sfix37_En29 + wire signed [36:0] Add_add_cast_1; // sfix37_En29 + wire signed [36:0] Add_add_temp; // sfix37_En29 + wire signed [31:0] Add_out1; // sfix32_En26 + wire signed [39:0] Sum1_add_cast; // sfix40_En26 + wire signed [39:0] Sum1_add_cast_1; // sfix40_En26 + wire signed [39:0] Sum1_add_temp; // sfix40_En26 + wire signed [35:0] u_sat; // sfix36_En23 + wire signed [17:0] D_Data_Type_out1; // sfix18_En12 + + // Control Current + + + // /Product2 + assign Product2_out1 = param_current_p_gain * Err; + + + + // /Convert_Data_Type1 + velocityControlHdl_Convert_Data_Type1_block u_Convert_Data_Type1 (.In1(Product2_out1), // sfix36_En24 + .Out1(Convert_Data_Type1_out1) // sfix36_En23 + ); + + // /Constant2 + assign Constant2_out1 = 18'sb010100111110001011; + + + + // /Product + assign Product_out1 = param_current_i_gain * Constant2_out1; + + + + // /Maintain_Range + velocityControlHdl_Maintain_Range_block u_Maintain_Range (.In1(Product_out1), // sfix36_En33 + .Out1(pre_integrator) // sfix18_En15 + ); + + // /Product1 + assign pre_integrator_1 = Err * pre_integrator; + + + + // /Constant + assign Constant_out1 = 36'sh000000000; + + + + // /Clamp + velocityControlHdl_Clamp_block u_Clamp (.preIntegrator(pre_integrator_1), // sfix36_En29 + .preSat(u), // sfix36_En23 + .saturated(PI_Sat_out2), + .Clamp(Clamp_out1) + ); + + assign switch_compare_1 = (Clamp_out1 > 1'b0 ? 1'b1 : + 1'b0); + + + + // /Switch + assign Switch_out1 = (switch_compare_1 == 1'b0 ? pre_integrator_1 : + Constant_out1); + + + + // /Add + assign Add_add_cast = Switch_out1; + assign Add_add_cast_1 = {{2{I_term[31]}}, {I_term, 3'b000}}; + assign Add_add_temp = Add_add_cast + Add_add_cast_1; + assign Add_out1 = ((Add_add_temp[36] == 1'b0) && (Add_add_temp[35:34] != 2'b00) ? 32'sb01111111111111111111111111111111 : + ((Add_add_temp[36] == 1'b1) && (Add_add_temp[35:34] != 2'b11) ? 32'sb10000000000000000000000000000000 : + $signed(Add_add_temp[34:3]))); + + + + // /Reset_Delay + velocityControlHdl_Reset_Delay_block u_Reset_Delay (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(Reest), + .In(Add_out1), // sfix32_En26 + .Out(I_term) // sfix32_En26 + ); + + // /Sum1 + assign Sum1_add_cast = {Convert_Data_Type1_out1[35], {Convert_Data_Type1_out1, 3'b000}}; + assign Sum1_add_cast_1 = I_term; + assign Sum1_add_temp = Sum1_add_cast + Sum1_add_cast_1; + assign u = Sum1_add_temp[38:3]; + + + + // /PI_Sat + velocityControlHdl_PI_Sat_block u_PI_Sat (.In1(u), // sfix36_En23 + .Out1(u_sat), // sfix36_En23 + .saturated(PI_Sat_out2) + ); + + // /D_Data_Type + assign D_Data_Type_out1 = u_sat[28:11]; + + + + assign Out = D_Data_Type_out1; + +endmodule // velocityControlHdl_Control_Current1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_DQ_Currents.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_DQ_Currents.v new file mode 100644 index 000000000..0eb22ea98 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_DQ_Currents.v @@ -0,0 +1,121 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_DQ_Currents.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Control_DQ_Currents +// Source Path: velocityControlHdl/Control_DQ_Currents +// Hierarchy Level: 4 +// +// Simulink subsystem description for velocityControlHdl/Control_DQ_Currents: +// +// Linear Current Controllers +// +// PID Blocks used for Control Design of Current Loop controllers. +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Control_DQ_Currents + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + q_current_command, + d_current_measured, + q_current_measured, + param_current_p_gain, + param_current_i_gain, + d_voltage, + q_voltage + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [17:0] q_current_command; // sfix18_En15 + input signed [17:0] d_current_measured; // sfix18_En15 + input signed [17:0] q_current_measured; // sfix18_En15 + input signed [17:0] param_current_p_gain; // sfix18_En10 + input signed [17:0] param_current_i_gain; // sfix18_En2 + output signed [17:0] d_voltage; // sfix18_En12 + output signed [17:0] q_voltage; // sfix18_En12 + + + wire signed [17:0] d_current_command_1; // sfix18_En15 + wire signed [18:0] D_Error_sub_cast; // sfix19_En15 + wire signed [18:0] D_Error_sub_cast_1; // sfix19_En15 + wire signed [18:0] D_Error_sub_temp; // sfix19_En15 + wire signed [17:0] d_current_error; // sfix18_En14 + wire signed [17:0] direct_voltage; // sfix18_En12 + wire signed [18:0] Q_Error_sub_cast; // sfix19_En15 + wire signed [18:0] Q_Error_sub_cast_1; // sfix19_En15 + wire signed [18:0] Q_Error_sub_temp; // sfix19_En15 + wire signed [17:0] q_current_error; // sfix18_En14 + wire signed [17:0] quadrature_voltage; // sfix18_En12 + + // The controller regulates direct and quadrature currents. + // + // Current Controllers + + + // /d_current_command + assign d_current_command_1 = 18'sb000000000000000000; + + + + // /D_Error + assign D_Error_sub_cast = d_current_command_1; + assign D_Error_sub_cast_1 = d_current_measured; + assign D_Error_sub_temp = D_Error_sub_cast - D_Error_sub_cast_1; + assign d_current_error = D_Error_sub_temp[18:1]; + + + + // /Control_Current + velocityControlHdl_Control_Current u_Control_Current (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reest(Reset_1), + .Err(d_current_error), // sfix18_En14 + .param_current_p_gain(param_current_p_gain), // sfix18_En10 + .param_current_i_gain(param_current_i_gain), // sfix18_En2 + .Out(direct_voltage) // sfix18_En12 + ); + + assign d_voltage = direct_voltage; + + // /Q_Error + assign Q_Error_sub_cast = q_current_command; + assign Q_Error_sub_cast_1 = q_current_measured; + assign Q_Error_sub_temp = Q_Error_sub_cast - Q_Error_sub_cast_1; + assign q_current_error = Q_Error_sub_temp[18:1]; + + + + // /Control_Current1 + velocityControlHdl_Control_Current1 u_Control_Current1 (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reest(Reset_1), + .Err(q_current_error), // sfix18_En14 + .param_current_p_gain(param_current_p_gain), // sfix18_En10 + .param_current_i_gain(param_current_i_gain), // sfix18_En2 + .Out(quadrature_voltage) // sfix18_En12 + ); + + assign q_voltage = quadrature_voltage; + +endmodule // velocityControlHdl_Control_DQ_Currents + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Velocity.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Velocity.v new file mode 100644 index 000000000..7c8078da5 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Velocity.v @@ -0,0 +1,79 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_Velocity.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Control_Velocity +// Source Path: velocityControlHdl/Control_Velocity +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Control_Velocity + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + velocity_command, + velocity_measured, + param_velocity_p_gain, + param_velocity_i_gain, + q_command + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [17:0] velocity_command; // sfix18_En8 + input signed [17:0] velocity_measured; // sfix18_En8 + input signed [17:0] param_velocity_p_gain; // sfix18_En16 + input signed [17:0] param_velocity_i_gain; // sfix18_En15 + output signed [17:0] q_command; // sfix18_En15 + + + wire signed [18:0] Error_Sum_sub_cast; // sfix19_En8 + wire signed [18:0] Error_Sum_sub_cast_1; // sfix19_En8 + wire signed [18:0] Error_Sum_sub_temp; // sfix19_En8 + wire signed [17:0] velocity_error; // sfix18_En7 + + // Velocity Controller + // + // The controller regulates motor velocity using rotor velocity feedback compared to a commanded velocity. + // The output of the controller is the quadrature-winding current command which is directly proportional to the electromagnetic torque of the motor. + // Since the motor being controlled is a Permanent Magnet Synchronous Machine, the rotor flux linkage is fixed (determined by the magnets), + // hence the commanded direct-winding current is always zero. + + + // /Error Sum + assign Error_Sum_sub_cast = velocity_command; + assign Error_Sum_sub_cast_1 = velocity_measured; + assign Error_Sum_sub_temp = Error_Sum_sub_cast - Error_Sum_sub_cast_1; + assign velocity_error = Error_Sum_sub_temp[18:1]; + + + + // /Rotor_Velocity_Control + velocityControlHdl_Rotor_Velocity_Control u_Rotor_Velocity_Control (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(Reset_1), + .Err(velocity_error), // sfix18_En7 + .param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16 + .param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15 + .Out(q_command) // sfix18_En15 + ); + +endmodule // velocityControlHdl_Control_Velocity + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type.v new file mode 100644 index 000000000..439b802f1 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Convert_Data_Type +// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Convert_Data_Type +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Convert_Data_Type + ( + In1, + Out1 + ); + + + input signed [35:0] In1; // sfix36_En23 + output signed [35:0] Out1; // sfix36_En22 + + + wire signed [35:0] Data_Type_Conversion_out1; // sfix36_En22 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = {In1[35], In1[35:1]}; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // velocityControlHdl_Convert_Data_Type + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1.v new file mode 100644 index 000000000..f01b8f4e9 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Convert_Data_Type1 +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Convert_Data_Type1 +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Convert_Data_Type1 + ( + In1, + Out1 + ); + + + input signed [35:0] In1; // sfix36_En24 + output signed [35:0] Out1; // sfix36_En23 + + + wire signed [35:0] Data_Type_Conversion_out1; // sfix36_En23 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = {In1[35], In1[35:1]}; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // velocityControlHdl_Convert_Data_Type1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1_block.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1_block.v new file mode 100644 index 000000000..7e4207786 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1_block.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type1_block.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Convert_Data_Type1_block +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Convert_Data_Type1 +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Convert_Data_Type1_block + ( + In1, + Out1 + ); + + + input signed [35:0] In1; // sfix36_En24 + output signed [35:0] Out1; // sfix36_En23 + + + wire signed [35:0] Data_Type_Conversion_out1; // sfix36_En23 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = {In1[35], In1[35:1]}; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // velocityControlHdl_Convert_Data_Type1_block + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1_block1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1_block1.v new file mode 100644 index 000000000..9c262d996 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1_block1.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type1_block1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Convert_Data_Type1_block1 +// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Park_Transform/Convert_Data_Type1 +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Convert_Data_Type1_block1 + ( + In1, + Out1 + ); + + + input signed [35:0] In1; // sfix36_En28 + output signed [17:0] Out1; // sfix18_En10 + + + wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En10 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = In1[35:18]; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // velocityControlHdl_Convert_Data_Type1_block1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type_block.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type_block.v new file mode 100644 index 000000000..15403c165 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type_block.v @@ -0,0 +1,38 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type_block.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Convert_Data_Type_block +// Source Path: velocityControlHdl/Sin_Cos1/Convert_Data_Type +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Convert_Data_Type_block + ( + In1, + Out1 + ); + + + input signed [17:0] In1; // sfix18_En14 + output signed [17:0] Out1; // sfix18_En14 + + + + + // /Data Type Conversion + assign Out1 = In1; + +endmodule // velocityControlHdl_Convert_Data_Type_block + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type_block1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type_block1.v new file mode 100644 index 000000000..e8ec0128b --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type_block1.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type_block1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Convert_Data_Type_block1 +// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Park_Transform/Convert_Data_Type +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Convert_Data_Type_block1 + ( + In1, + Out1 + ); + + + input signed [35:0] In1; // sfix36_En28 + output signed [17:0] Out1; // sfix18_En10 + + + wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En10 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = In1[35:18]; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // velocityControlHdl_Convert_Data_Type_block1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Double_Range.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Double_Range.v new file mode 100644 index 000000000..7492869e8 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Double_Range.v @@ -0,0 +1,62 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Double_Range.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Double_Range +// Source Path: velocityControlHdl/Space_Vector_Modulation/Double_Range +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Double_Range + ( + In1_0, + In1_1, + In1_2, + Out1_0, + Out1_1, + Out1_2 + ); + + + input signed [17:0] In1_0; // sfix18_En13 + input signed [17:0] In1_1; // sfix18_En13 + input signed [17:0] In1_2; // sfix18_En13 + output signed [17:0] Out1_0; // sfix18_En12 + output signed [17:0] Out1_1; // sfix18_En12 + output signed [17:0] Out1_2; // sfix18_En12 + + + wire signed [17:0] In1 [0:2]; // sfix18_En13 [3] + wire signed [17:0] Data_Type_Conversion_out1 [0:2]; // sfix18_En12 [3] + + + assign In1[0] = In1_0; + assign In1[1] = In1_1; + assign In1[2] = In1_2; + + // /Data Type Conversion + assign Data_Type_Conversion_out1[0] = {In1[0][17], In1[0][17:1]}; + assign Data_Type_Conversion_out1[1] = {In1[1][17], In1[1][17:1]}; + assign Data_Type_Conversion_out1[2] = {In1[2][17], In1[2][17:1]}; + + + + assign Out1_0 = Data_Type_Conversion_out1[0]; + + assign Out1_1 = Data_Type_Conversion_out1[1]; + + assign Out1_2 = Data_Type_Conversion_out1[2]; + +endmodule // velocityControlHdl_Double_Range + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation.v new file mode 100644 index 000000000..5eb847291 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation.v @@ -0,0 +1,93 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Dynamic_Saturation.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Dynamic_Saturation +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/PI_Sat/Dynamic Saturation +// Hierarchy Level: 7 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Dynamic_Saturation + ( + up, + u, + lo, + y, + sat_mode + ); + + + input signed [17:0] up; // sfix18_En13 + input signed [35:0] u; // sfix36_En23 + input signed [17:0] lo; // sfix18_En13 + output signed [35:0] y; // sfix36_En23 + output sat_mode; + + + wire signed [35:0] LowerRelop1_1_cast; // sfix36_En23 + wire LowerRelop1_relop1; + wire signed [35:0] UpperRelop_1_cast; // sfix36_En23 + wire UpperRelop_relop1; + wire signed [35:0] lo_dtc; // sfix36_En23 + wire signed [35:0] Switch_out1; // sfix36_En23 + wire signed [35:0] up_dtc; // sfix36_En23 + wire signed [35:0] Switch2_out1; // sfix36_En23 + wire LowerRelop1_out1; + + + // /LowerRelop1 + assign LowerRelop1_1_cast = {{8{up[17]}}, {up, 10'b0000000000}}; + assign LowerRelop1_relop1 = (u > LowerRelop1_1_cast ? 1'b1 : + 1'b0); + + + + // /UpperRelop + assign UpperRelop_1_cast = {{8{lo[17]}}, {lo, 10'b0000000000}}; + assign UpperRelop_relop1 = (u < UpperRelop_1_cast ? 1'b1 : + 1'b0); + + + + assign lo_dtc = {{8{lo[17]}}, {lo, 10'b0000000000}}; + + + + // /Switch + assign Switch_out1 = (UpperRelop_relop1 == 1'b0 ? u : + lo_dtc); + + + + assign up_dtc = {{8{up[17]}}, {up, 10'b0000000000}}; + + + + // /Switch2 + assign Switch2_out1 = (LowerRelop1_relop1 == 1'b0 ? Switch_out1 : + up_dtc); + + + + assign y = Switch2_out1; + + // /Logical Operator + assign LowerRelop1_out1 = LowerRelop1_relop1 | UpperRelop_relop1; + + + + assign sat_mode = LowerRelop1_out1; + +endmodule // velocityControlHdl_Dynamic_Saturation + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation_block.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation_block.v new file mode 100644 index 000000000..401d2bb9d --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation_block.v @@ -0,0 +1,93 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Dynamic_Saturation_block.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Dynamic_Saturation_block +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/PI_Sat/Dynamic Saturation +// Hierarchy Level: 7 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Dynamic_Saturation_block + ( + up, + u, + lo, + y, + sat_mode + ); + + + input signed [17:0] up; // sfix18_En13 + input signed [35:0] u; // sfix36_En23 + input signed [17:0] lo; // sfix18_En13 + output signed [35:0] y; // sfix36_En23 + output sat_mode; + + + wire signed [35:0] LowerRelop1_1_cast; // sfix36_En23 + wire LowerRelop1_relop1; + wire signed [35:0] UpperRelop_1_cast; // sfix36_En23 + wire UpperRelop_relop1; + wire signed [35:0] lo_dtc; // sfix36_En23 + wire signed [35:0] Switch_out1; // sfix36_En23 + wire signed [35:0] up_dtc; // sfix36_En23 + wire signed [35:0] Switch2_out1; // sfix36_En23 + wire LowerRelop1_out1; + + + // /LowerRelop1 + assign LowerRelop1_1_cast = {{8{up[17]}}, {up, 10'b0000000000}}; + assign LowerRelop1_relop1 = (u > LowerRelop1_1_cast ? 1'b1 : + 1'b0); + + + + // /UpperRelop + assign UpperRelop_1_cast = {{8{lo[17]}}, {lo, 10'b0000000000}}; + assign UpperRelop_relop1 = (u < UpperRelop_1_cast ? 1'b1 : + 1'b0); + + + + assign lo_dtc = {{8{lo[17]}}, {lo, 10'b0000000000}}; + + + + // /Switch + assign Switch_out1 = (UpperRelop_relop1 == 1'b0 ? u : + lo_dtc); + + + + assign up_dtc = {{8{up[17]}}, {up, 10'b0000000000}}; + + + + // /Switch2 + assign Switch2_out1 = (LowerRelop1_relop1 == 1'b0 ? Switch_out1 : + up_dtc); + + + + assign y = Switch2_out1; + + // /Logical Operator + assign LowerRelop1_out1 = LowerRelop1_relop1 | UpperRelop_relop1; + + + + assign sat_mode = LowerRelop1_out1; + +endmodule // velocityControlHdl_Dynamic_Saturation_block + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation_block1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation_block1.v new file mode 100644 index 000000000..df37828a7 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation_block1.v @@ -0,0 +1,93 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Dynamic_Saturation_block1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Dynamic_Saturation_block1 +// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/PI_Sat/Dynamic Saturation +// Hierarchy Level: 7 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Dynamic_Saturation_block1 + ( + up, + u, + lo, + y, + sat_mode + ); + + + input signed [17:0] up; // sfix18_En15 + input signed [35:0] u; // sfix36_En22 + input signed [17:0] lo; // sfix18_En15 + output signed [35:0] y; // sfix36_En22 + output sat_mode; + + + wire signed [35:0] LowerRelop1_1_cast; // sfix36_En22 + wire LowerRelop1_relop1; + wire signed [35:0] UpperRelop_1_cast; // sfix36_En22 + wire UpperRelop_relop1; + wire signed [35:0] lo_dtc; // sfix36_En22 + wire signed [35:0] Switch_out1; // sfix36_En22 + wire signed [35:0] up_dtc; // sfix36_En22 + wire signed [35:0] Switch2_out1; // sfix36_En22 + wire LowerRelop1_out1; + + + // /LowerRelop1 + assign LowerRelop1_1_cast = {{11{up[17]}}, {up, 7'b0000000}}; + assign LowerRelop1_relop1 = (u > LowerRelop1_1_cast ? 1'b1 : + 1'b0); + + + + // /UpperRelop + assign UpperRelop_1_cast = {{11{lo[17]}}, {lo, 7'b0000000}}; + assign UpperRelop_relop1 = (u < UpperRelop_1_cast ? 1'b1 : + 1'b0); + + + + assign lo_dtc = {{11{lo[17]}}, {lo, 7'b0000000}}; + + + + // /Switch + assign Switch_out1 = (UpperRelop_relop1 == 1'b0 ? u : + lo_dtc); + + + + assign up_dtc = {{11{up[17]}}, {up, 7'b0000000}}; + + + + // /Switch2 + assign Switch2_out1 = (LowerRelop1_relop1 == 1'b0 ? Switch_out1 : + up_dtc); + + + + assign y = Switch2_out1; + + // /Logical Operator + assign LowerRelop1_out1 = LowerRelop1_relop1 | UpperRelop_relop1; + + + + assign sat_mode = LowerRelop1_out1; + +endmodule // velocityControlHdl_Dynamic_Saturation_block1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Inverse_Clarke_Transform.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Inverse_Clarke_Transform.v new file mode 100644 index 000000000..4771c8dc8 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Inverse_Clarke_Transform.v @@ -0,0 +1,110 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Inverse_Clarke_Transform.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Inverse_Clarke_Transform +// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Clarke_Transform +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Inverse_Clarke_Transform + ( + alpha_voltage, + beta_voltage, + phase_voltages_0, + phase_voltages_1, + phase_voltages_2 + ); + + + input signed [17:0] alpha_voltage; // sfix18_En10 + input signed [17:0] beta_voltage; // sfix18_En10 + output signed [17:0] phase_voltages_0; // sfix18_En13 + output signed [17:0] phase_voltages_1; // sfix18_En13 + output signed [17:0] phase_voltages_2; // sfix18_En13 + + + wire signed [35:0] voltage_phase_a; // sfix36_En26 + wire signed [35:0] Gain1_out1; // sfix36_En26 + wire signed [35:0] Gain_out1; // sfix36_En26 + wire signed [35:0] voltage_phase_b; // sfix36_En26 + wire signed [37:0] Add1_cast; // sfix38_En26 + wire signed [37:0] Add1_cast_1; // sfix38_En26 + wire signed [37:0] Add1_sub_cast; // sfix38_En26 + wire signed [37:0] Add1_sub_temp; // sfix38_En26 + wire signed [35:0] voltage_phase_c; // sfix36_En26 + wire signed [35:0] Mux_out1 [0:2]; // sfix36_En26 [3] + wire signed [17:0] Current_Data_Type_out1 [0:2]; // sfix18_En13 [3] + + // Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities + // The alpha and beta components are dependent on time and speed. + // + // Inverse Clarke Transform + + + // /Data Type Conversion + assign voltage_phase_a = {{2{alpha_voltage[17]}}, {alpha_voltage, 16'b0000000000000000}}; + + + + // /Gain1 + assign Gain1_out1 = 56756 * beta_voltage; + + + + // /Gain + assign Gain_out1 = {{3{alpha_voltage[17]}}, {alpha_voltage, 15'b000000000000000}}; + + + + // /Add + assign voltage_phase_b = Gain1_out1 - Gain_out1; + + + + // /Add1 + assign Add1_cast = Gain_out1; + assign Add1_cast_1 = - (Add1_cast); + assign Add1_sub_cast = Gain1_out1; + assign Add1_sub_temp = Add1_cast_1 - Add1_sub_cast; + assign voltage_phase_c = Add1_sub_temp[35:0]; + + + + // /Mux + assign Mux_out1[0] = voltage_phase_a; + assign Mux_out1[1] = voltage_phase_b; + assign Mux_out1[2] = voltage_phase_c; + + // /Current_Data_Type + assign Current_Data_Type_out1[0] = ((Mux_out1[0][35] == 1'b0) && (Mux_out1[0][34:30] != 5'b00000) ? 18'sb011111111111111111 : + ((Mux_out1[0][35] == 1'b1) && (Mux_out1[0][34:30] != 5'b11111) ? 18'sb100000000000000000 : + $signed(Mux_out1[0][30:13]))); + assign Current_Data_Type_out1[1] = ((Mux_out1[1][35] == 1'b0) && (Mux_out1[1][34:30] != 5'b00000) ? 18'sb011111111111111111 : + ((Mux_out1[1][35] == 1'b1) && (Mux_out1[1][34:30] != 5'b11111) ? 18'sb100000000000000000 : + $signed(Mux_out1[1][30:13]))); + assign Current_Data_Type_out1[2] = ((Mux_out1[2][35] == 1'b0) && (Mux_out1[2][34:30] != 5'b00000) ? 18'sb011111111111111111 : + ((Mux_out1[2][35] == 1'b1) && (Mux_out1[2][34:30] != 5'b11111) ? 18'sb100000000000000000 : + $signed(Mux_out1[2][30:13]))); + + + + assign phase_voltages_0 = Current_Data_Type_out1[0]; + + assign phase_voltages_1 = Current_Data_Type_out1[1]; + + assign phase_voltages_2 = Current_Data_Type_out1[2]; + +endmodule // velocityControlHdl_Inverse_Clarke_Transform + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Inverse_Park_Transform.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Inverse_Park_Transform.v new file mode 100644 index 000000000..fbd0c7623 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Inverse_Park_Transform.v @@ -0,0 +1,99 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Inverse_Park_Transform.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Inverse_Park_Transform +// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Park_Transform +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Inverse_Park_Transform + ( + direct_voltage, + quadrature_voltage, + sin_coefficient, + cos_coefficient, + alpha_voltage, + beta_voltage + ); + + + input signed [17:0] direct_voltage; // sfix18_En12 + input signed [17:0] quadrature_voltage; // sfix18_En12 + input signed [17:0] sin_coefficient; // sfix18_En16 + input signed [17:0] cos_coefficient; // sfix18_En16 + output signed [17:0] alpha_voltage; // sfix18_En10 + output signed [17:0] beta_voltage; // sfix18_En10 + + + wire signed [35:0] Product2_out1; // sfix36_En28 + wire signed [35:0] Product3_out1; // sfix36_En28 + wire signed [35:0] alpha_voltage_1; // sfix36_En28 + wire signed [17:0] Convert_Data_Type_out1; // sfix18_En10 + wire signed [35:0] Product_out1; // sfix36_En28 + wire signed [35:0] Product1_out1; // sfix36_En28 + wire signed [35:0] beta_voltage_1; // sfix36_En28 + wire signed [17:0] Convert_Data_Type1_out1; // sfix18_En10 + + // Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) + // + // Inverse Park Transform + + + // /Product2 + assign Product2_out1 = direct_voltage * cos_coefficient; + + + + // /Product3 + assign Product3_out1 = quadrature_voltage * sin_coefficient; + + + + // /Add1 + assign alpha_voltage_1 = Product2_out1 - Product3_out1; + + + + // /Convert_Data_Type + velocityControlHdl_Convert_Data_Type_block1 u_Convert_Data_Type (.In1(alpha_voltage_1), // sfix36_En28 + .Out1(Convert_Data_Type_out1) // sfix18_En10 + ); + + assign alpha_voltage = Convert_Data_Type_out1; + + // /Product + assign Product_out1 = direct_voltage * sin_coefficient; + + + + // /Product1 + assign Product1_out1 = quadrature_voltage * cos_coefficient; + + + + // /Add + assign beta_voltage_1 = Product_out1 + Product1_out1; + + + + // /Convert_Data_Type1 + velocityControlHdl_Convert_Data_Type1_block1 u_Convert_Data_Type1 (.In1(beta_voltage_1), // sfix36_En28 + .Out1(Convert_Data_Type1_out1) // sfix18_En10 + ); + + assign beta_voltage = Convert_Data_Type1_out1; + +endmodule // velocityControlHdl_Inverse_Park_Transform + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_MATLAB_Function.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_MATLAB_Function.v new file mode 100644 index 000000000..7518de32e --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_MATLAB_Function.v @@ -0,0 +1,46 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MATLAB_Function.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_MATLAB_Function +// Source Path: velocityControlHdl/Sin_Cos1/Mark_Extract_Bits/MATLAB Function +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_MATLAB_Function + ( + u, + y + ); + + + input [17:0] u; // ufix18 + output [8:0] y; // ufix9 + + + wire [8:0] y1; // ufix9_E9 + + + //MATLAB Function 'Sin_Cos/Mark_Extract_Bits/MATLAB Function': ':1' + // Non-tunable mask parameter + //':1:8' + //':1:10' + assign y1 = u[17:9]; + //':1:14' + assign y = y1; + + + +endmodule // velocityControlHdl_MATLAB_Function + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_MATLAB_Function_block.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_MATLAB_Function_block.v new file mode 100644 index 000000000..18c738db1 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_MATLAB_Function_block.v @@ -0,0 +1,44 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MATLAB_Function_block.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_MATLAB_Function_block +// Source Path: velocityControlHdl/Sin_Cos1/Mark_Extract_Bits1/MATLAB Function +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_MATLAB_Function_block + ( + u, + y + ); + + + input [17:0] u; // ufix18 + output [8:0] y; // ufix9 + + + + + //MATLAB Function 'Sin_Cos/Mark_Extract_Bits1/MATLAB Function': ':1' + // Non-tunable mask parameter + //':1:8' + //':1:10' + assign y = u[8:0]; + //':1:14' + + + +endmodule // velocityControlHdl_MATLAB_Function_block + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range.v new file mode 100644 index 000000000..896d17afe --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Maintain_Range.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Maintain_Range +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Maintain_Range +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Maintain_Range + ( + In1, + Out1 + ); + + + input signed [35:0] In1; // sfix36_En33 + output signed [17:0] Out1; // sfix18_En15 + + + wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En15 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = In1[35:18]; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // velocityControlHdl_Maintain_Range + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range_block.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range_block.v new file mode 100644 index 000000000..d7ecaca53 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range_block.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Maintain_Range_block.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Maintain_Range_block +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Maintain_Range +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Maintain_Range_block + ( + In1, + Out1 + ); + + + input signed [35:0] In1; // sfix36_En33 + output signed [17:0] Out1; // sfix18_En15 + + + wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En15 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = In1[35:18]; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // velocityControlHdl_Maintain_Range_block + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range_block1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range_block1.v new file mode 100644 index 000000000..93232c6dd --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range_block1.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Maintain_Range_block1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Maintain_Range_block1 +// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Maintain_Range +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Maintain_Range_block1 + ( + In1, + Out1 + ); + + + input signed [35:0] In1; // sfix36_En46 + output signed [17:0] Out1; // sfix18_En28 + + + wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En28 + + + // /Data Type Conversion + assign Data_Type_Conversion_out1 = In1[35:18]; + + + + assign Out1 = Data_Type_Conversion_out1; + +endmodule // velocityControlHdl_Maintain_Range_block1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Mark_Extract_Bits.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Mark_Extract_Bits.v new file mode 100644 index 000000000..39e337e80 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Mark_Extract_Bits.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Mark_Extract_Bits.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Mark_Extract_Bits +// Source Path: velocityControlHdl/Sin_Cos1/Mark_Extract_Bits +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Mark_Extract_Bits + ( + In1, + Out1 + ); + + + input [17:0] In1; // ufix18 + output [8:0] Out1; // ufix9 + + + wire [8:0] MATLAB_Function_out1; // ufix9 + + + // /MATLAB Function + velocityControlHdl_MATLAB_Function u_MATLAB_Function (.u(In1), // ufix18 + .y(MATLAB_Function_out1) // ufix9 + ); + + assign Out1 = MATLAB_Function_out1; + +endmodule // velocityControlHdl_Mark_Extract_Bits + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Mark_Extract_Bits1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Mark_Extract_Bits1.v new file mode 100644 index 000000000..5e1f59914 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Mark_Extract_Bits1.v @@ -0,0 +1,43 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Mark_Extract_Bits1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Mark_Extract_Bits1 +// Source Path: velocityControlHdl/Sin_Cos1/Mark_Extract_Bits1 +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Mark_Extract_Bits1 + ( + In1, + Out1 + ); + + + input [17:0] In1; // ufix18 + output [8:0] Out1; // ufix9 + + + wire [8:0] MATLAB_Function_out1; // ufix9 + + + // /MATLAB Function + velocityControlHdl_MATLAB_Function_block u_MATLAB_Function (.u(In1), // ufix18 + .y(MATLAB_Function_out1) // ufix9 + ); + + assign Out1 = MATLAB_Function_out1; + +endmodule // velocityControlHdl_Mark_Extract_Bits1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_MinMax.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_MinMax.v new file mode 100644 index 000000000..b6c9db3f8 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_MinMax.v @@ -0,0 +1,62 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MinMax.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_MinMax +// Source Path: velocityControlHdl/Space_Vector_Modulation/MinMax +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_MinMax + ( + in0, + in1, + in2, + out0 + ); + + + input signed [17:0] in0; // sfix18_En12 + input signed [17:0] in1; // sfix18_En12 + input signed [17:0] in2; // sfix18_En12 + output signed [17:0] out0; // sfix18_En12 + + + wire signed [17:0] MinMax_muxout [0:2]; // sfix18_En12 [3] + wire signed [17:0] MinMax_stage1_val [0:1]; // sfix18_En12 [2] + wire signed [17:0] MinMax_stage2_val; // sfix18_En12 + + + assign MinMax_muxout[0] = in0; + assign MinMax_muxout[1] = in1; + assign MinMax_muxout[2] = in2; + + // ---- Tree min implementation ---- + // ---- Tree min stage 1 ---- + assign MinMax_stage1_val[0] = (MinMax_muxout[0] <= MinMax_muxout[1] ? MinMax_muxout[0] : + MinMax_muxout[1]); + assign MinMax_stage1_val[1] = MinMax_muxout[2]; + + + + // ---- Tree min stage 2 ---- + assign MinMax_stage2_val = (MinMax_stage1_val[0] <= MinMax_stage1_val[1] ? MinMax_stage1_val[0] : + MinMax_stage1_val[1]); + + + + assign out0 = MinMax_stage2_val; + +endmodule // velocityControlHdl_MinMax + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_MinMax1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_MinMax1.v new file mode 100644 index 000000000..564dc4194 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_MinMax1.v @@ -0,0 +1,62 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MinMax1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_MinMax1 +// Source Path: velocityControlHdl/Space_Vector_Modulation/MinMax1 +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_MinMax1 + ( + in0, + in1, + in2, + out0 + ); + + + input signed [17:0] in0; // sfix18_En12 + input signed [17:0] in1; // sfix18_En12 + input signed [17:0] in2; // sfix18_En12 + output signed [17:0] out0; // sfix18_En12 + + + wire signed [17:0] MinMax1_muxout [0:2]; // sfix18_En12 [3] + wire signed [17:0] MinMax1_stage1_val [0:1]; // sfix18_En12 [2] + wire signed [17:0] MinMax1_stage2_val; // sfix18_En12 + + + assign MinMax1_muxout[0] = in0; + assign MinMax1_muxout[1] = in1; + assign MinMax1_muxout[2] = in2; + + // ---- Tree max implementation ---- + // ---- Tree max stage 1 ---- + assign MinMax1_stage1_val[0] = (MinMax1_muxout[0] >= MinMax1_muxout[1] ? MinMax1_muxout[0] : + MinMax1_muxout[1]); + assign MinMax1_stage1_val[1] = MinMax1_muxout[2]; + + + + // ---- Tree max stage 2 ---- + assign MinMax1_stage2_val = (MinMax1_stage1_val[0] >= MinMax1_stage1_val[1] ? MinMax1_stage1_val[0] : + MinMax1_stage1_val[1]); + + + + assign out0 = MinMax1_stage2_val; + +endmodule // velocityControlHdl_MinMax1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_PI_Sat.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_PI_Sat.v new file mode 100644 index 000000000..88d7ba68b --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_PI_Sat.v @@ -0,0 +1,67 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_PI_Sat.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_PI_Sat +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/PI_Sat +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_PI_Sat + ( + In1, + Out1, + saturated + ); + + + input signed [35:0] In1; // sfix36_En23 + output signed [35:0] Out1; // sfix36_En23 + output saturated; + + + wire signed [17:0] PI_Sat_out1; // sfix18_En13 + wire signed [18:0] Unary_Minus_cast; // sfix19_En13 + wire signed [18:0] Unary_Minus_cast_1; // sfix19_En13 + wire signed [17:0] Unary_Minus_out1; // sfix18_En13 + wire signed [35:0] Dynamic_Saturation_out1; // sfix36_En23 + wire Dynamic_Saturation_out2; + + + // /PI_Sat + assign PI_Sat_out1 = 18'sb010101100110011010; + + + + // /Unary Minus + assign Unary_Minus_cast = PI_Sat_out1; + assign Unary_Minus_cast_1 = - (Unary_Minus_cast); + assign Unary_Minus_out1 = Unary_Minus_cast_1[17:0]; + + + + // /Dynamic Saturation + velocityControlHdl_Dynamic_Saturation u_Dynamic_Saturation (.up(PI_Sat_out1), // sfix18_En13 + .u(In1), // sfix36_En23 + .lo(Unary_Minus_out1), // sfix18_En13 + .y(Dynamic_Saturation_out1), // sfix36_En23 + .sat_mode(Dynamic_Saturation_out2) + ); + + assign Out1 = Dynamic_Saturation_out1; + + assign saturated = Dynamic_Saturation_out2; + +endmodule // velocityControlHdl_PI_Sat + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_PI_Sat_block.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_PI_Sat_block.v new file mode 100644 index 000000000..cf98c96b0 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_PI_Sat_block.v @@ -0,0 +1,67 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_PI_Sat_block.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_PI_Sat_block +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/PI_Sat +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_PI_Sat_block + ( + In1, + Out1, + saturated + ); + + + input signed [35:0] In1; // sfix36_En23 + output signed [35:0] Out1; // sfix36_En23 + output saturated; + + + wire signed [17:0] PI_Sat_out1; // sfix18_En13 + wire signed [18:0] Unary_Minus_cast; // sfix19_En13 + wire signed [18:0] Unary_Minus_cast_1; // sfix19_En13 + wire signed [17:0] Unary_Minus_out1; // sfix18_En13 + wire signed [35:0] Dynamic_Saturation_out1; // sfix36_En23 + wire Dynamic_Saturation_out2; + + + // /PI_Sat + assign PI_Sat_out1 = 18'sb010101100110011010; + + + + // /Unary Minus + assign Unary_Minus_cast = PI_Sat_out1; + assign Unary_Minus_cast_1 = - (Unary_Minus_cast); + assign Unary_Minus_out1 = Unary_Minus_cast_1[17:0]; + + + + // /Dynamic Saturation + velocityControlHdl_Dynamic_Saturation_block u_Dynamic_Saturation (.up(PI_Sat_out1), // sfix18_En13 + .u(In1), // sfix36_En23 + .lo(Unary_Minus_out1), // sfix18_En13 + .y(Dynamic_Saturation_out1), // sfix36_En23 + .sat_mode(Dynamic_Saturation_out2) + ); + + assign Out1 = Dynamic_Saturation_out1; + + assign saturated = Dynamic_Saturation_out2; + +endmodule // velocityControlHdl_PI_Sat_block + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_PI_Sat_block1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_PI_Sat_block1.v new file mode 100644 index 000000000..196e09c8f --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_PI_Sat_block1.v @@ -0,0 +1,67 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_PI_Sat_block1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_PI_Sat_block1 +// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/PI_Sat +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_PI_Sat_block1 + ( + In1, + Out1, + saturated + ); + + + input signed [35:0] In1; // sfix36_En22 + output signed [35:0] Out1; // sfix36_En22 + output saturated; + + + wire signed [17:0] PI_Sat_out1; // sfix18_En15 + wire signed [18:0] Unary_Minus_cast; // sfix19_En15 + wire signed [18:0] Unary_Minus_cast_1; // sfix19_En15 + wire signed [17:0] Unary_Minus_out1; // sfix18_En15 + wire signed [35:0] Dynamic_Saturation_out1; // sfix36_En22 + wire Dynamic_Saturation_out2; + + + // /PI_Sat + assign PI_Sat_out1 = 18'sb010101100110011010; + + + + // /Unary Minus + assign Unary_Minus_cast = PI_Sat_out1; + assign Unary_Minus_cast_1 = - (Unary_Minus_cast); + assign Unary_Minus_out1 = Unary_Minus_cast_1[17:0]; + + + + // /Dynamic Saturation + velocityControlHdl_Dynamic_Saturation_block1 u_Dynamic_Saturation (.up(PI_Sat_out1), // sfix18_En15 + .u(In1), // sfix36_En22 + .lo(Unary_Minus_out1), // sfix18_En15 + .y(Dynamic_Saturation_out1), // sfix36_En22 + .sat_mode(Dynamic_Saturation_out2) + ); + + assign Out1 = Dynamic_Saturation_out1; + + assign saturated = Dynamic_Saturation_out2; + +endmodule // velocityControlHdl_PI_Sat_block1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Park_Transform.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Park_Transform.v new file mode 100644 index 000000000..b4831b4f7 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Park_Transform.v @@ -0,0 +1,103 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Park_Transform.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Park_Transform +// Source Path: velocityControlHdl/Transform_ABC_to_dq/Park_Transform +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Park_Transform + ( + sin_coefficient, + cos_coefficient, + alpha_current, + beta_current, + direct_current, + quadrature_current + ); + + + input signed [17:0] sin_coefficient; // sfix18_En16 + input signed [17:0] cos_coefficient; // sfix18_En16 + input signed [17:0] alpha_current; // sfix18_En13 + input signed [17:0] beta_current; // sfix18_En13 + output signed [17:0] direct_current; // sfix18_En15 + output signed [17:0] quadrature_current; // sfix18_En15 + + + wire signed [35:0] Product2_out1; // sfix36_En29 + wire signed [35:0] Product3_out1; // sfix36_En29 + wire signed [35:0] Add1_out1; // sfix36_En29 + wire signed [17:0] D_Data_Type_out1; // sfix18_En15 + wire signed [35:0] Product1_out1; // sfix36_En29 + wire signed [35:0] Product_out1; // sfix36_En29 + wire signed [35:0] Add_out1; // sfix36_En29 + wire signed [17:0] Q_Data_Type_out1; // sfix18_En15 + + // Converts balanced two-phase orthogonal stationary system to an orthogonal rotating reference frame. + // + // Park Transform + + + // /Product2 + assign Product2_out1 = alpha_current * cos_coefficient; + + + + // /Product3 + assign Product3_out1 = beta_current * sin_coefficient; + + + + // /Add1 + assign Add1_out1 = Product2_out1 + Product3_out1; + + + + // /D_Data_Type + assign D_Data_Type_out1 = ((Add1_out1[35] == 1'b0) && (Add1_out1[34:31] != 4'b0000) ? 18'sb011111111111111111 : + ((Add1_out1[35] == 1'b1) && (Add1_out1[34:31] != 4'b1111) ? 18'sb100000000000000000 : + $signed(Add1_out1[31:14]))); + + + + assign direct_current = D_Data_Type_out1; + + // /Product1 + assign Product1_out1 = beta_current * cos_coefficient; + + + + // /Product + assign Product_out1 = alpha_current * sin_coefficient; + + + + // /Add + assign Add_out1 = Product1_out1 - Product_out1; + + + + // /Q_Data_Type + assign Q_Data_Type_out1 = ((Add_out1[35] == 1'b0) && (Add_out1[34:31] != 4'b0000) ? 18'sb011111111111111111 : + ((Add_out1[35] == 1'b1) && (Add_out1[34:31] != 4'b1111) ? 18'sb100000000000000000 : + $signed(Add_out1[31:14]))); + + + + assign quadrature_current = Q_Data_Type_out1; + +endmodule // velocityControlHdl_Park_Transform + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay.v new file mode 100644 index 000000000..726f036f6 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay.v @@ -0,0 +1,85 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Reset_Delay.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Reset_Delay +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Reset_Delay +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Reset_Delay + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + In, + Out + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [31:0] In; // sfix32_En26 + output signed [31:0] Out; // sfix32_En26 + + + wire signed [31:0] Constant1_out1; // sfix32_En26 + wire signed [31:0] Reset_Switch1_out1; // sfix32_En26 + reg signed [31:0] In_Delay_out1; // sfix32_En26 + wire signed [31:0] Constant_out1; // sfix32_En26 + wire signed [31:0] Reset_Switch_out1; // sfix32_En26 + + + // /Constant1 + assign Constant1_out1 = 32'sb00000000000000000000000000000000; + + + + // /Reset_Switch1 + assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In : + Constant1_out1); + + + + // /In_Delay + always @(posedge CLK_IN) + begin : In_Delay_process + if (reset == 1'b1) begin + In_Delay_out1 <= 32'sb00000000000000000000000000000000; + end + else if (enb_1_2000_0) begin + In_Delay_out1 <= Reset_Switch1_out1; + end + end + + + + // /Constant + assign Constant_out1 = 32'sb00000000000000000000000000000000; + + + + // /Reset_Switch + assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 : + Constant_out1); + + + + assign Out = Reset_Switch_out1; + +endmodule // velocityControlHdl_Reset_Delay + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay_block.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay_block.v new file mode 100644 index 000000000..a704150a1 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay_block.v @@ -0,0 +1,85 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Reset_Delay_block.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Reset_Delay_block +// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Reset_Delay +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Reset_Delay_block + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + In, + Out + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [31:0] In; // sfix32_En26 + output signed [31:0] Out; // sfix32_En26 + + + wire signed [31:0] Constant1_out1; // sfix32_En26 + wire signed [31:0] Reset_Switch1_out1; // sfix32_En26 + reg signed [31:0] In_Delay_out1; // sfix32_En26 + wire signed [31:0] Constant_out1; // sfix32_En26 + wire signed [31:0] Reset_Switch_out1; // sfix32_En26 + + + // /Constant1 + assign Constant1_out1 = 32'sb00000000000000000000000000000000; + + + + // /Reset_Switch1 + assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In : + Constant1_out1); + + + + // /In_Delay + always @(posedge CLK_IN) + begin : In_Delay_process + if (reset == 1'b1) begin + In_Delay_out1 <= 32'sb00000000000000000000000000000000; + end + else if (enb_1_2000_0) begin + In_Delay_out1 <= Reset_Switch1_out1; + end + end + + + + // /Constant + assign Constant_out1 = 32'sb00000000000000000000000000000000; + + + + // /Reset_Switch + assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 : + Constant_out1); + + + + assign Out = Reset_Switch_out1; + +endmodule // velocityControlHdl_Reset_Delay_block + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay_block1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay_block1.v new file mode 100644 index 000000000..4eddbef84 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay_block1.v @@ -0,0 +1,85 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Reset_Delay_block1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Reset_Delay_block1 +// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Reset_Delay +// Hierarchy Level: 6 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Reset_Delay_block1 + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + In, + Out + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [31:0] In; // sfix32_En28 + output signed [31:0] Out; // sfix32_En28 + + + wire signed [31:0] Constant1_out1; // sfix32_En28 + wire signed [31:0] Reset_Switch1_out1; // sfix32_En28 + reg signed [31:0] In_Delay_out1; // sfix32_En28 + wire signed [31:0] Constant_out1; // sfix32_En28 + wire signed [31:0] Reset_Switch_out1; // sfix32_En28 + + + // /Constant1 + assign Constant1_out1 = 32'sb00000000000000000000000000000000; + + + + // /Reset_Switch1 + assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In : + Constant1_out1); + + + + // /In_Delay + always @(posedge CLK_IN) + begin : In_Delay_process + if (reset == 1'b1) begin + In_Delay_out1 <= 32'sb00000000000000000000000000000000; + end + else if (enb_1_2000_0) begin + In_Delay_out1 <= Reset_Switch1_out1; + end + end + + + + // /Constant + assign Constant_out1 = 32'sb00000000000000000000000000000000; + + + + // /Reset_Switch + assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 : + Constant_out1); + + + + assign Out = Reset_Switch_out1; + +endmodule // velocityControlHdl_Reset_Delay_block1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Rotor_Velocity_Control.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Rotor_Velocity_Control.v new file mode 100644 index 000000000..c2e85e140 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Rotor_Velocity_Control.v @@ -0,0 +1,164 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Rotor_Velocity_Control.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Rotor_Velocity_Control +// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control +// Hierarchy Level: 5 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Rotor_Velocity_Control + ( + CLK_IN, + reset, + enb_1_2000_0, + Reset_1, + Err, + param_velocity_p_gain, + param_velocity_i_gain, + Out + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input Reset_1; + input signed [17:0] Err; // sfix18_En7 + input signed [17:0] param_velocity_p_gain; // sfix18_En16 + input signed [17:0] param_velocity_i_gain; // sfix18_En15 + output signed [17:0] Out; // sfix18_En15 + + + wire signed [35:0] P_term; // sfix36_En23 + wire signed [35:0] Convert_Data_Type_out1; // sfix36_En22 + wire signed [17:0] Constant2_out1; // sfix18_En31 + wire signed [35:0] Product_out1; // sfix36_En46 + wire signed [17:0] Maintain_Range_out1; // sfix18_En28 + wire signed [35:0] Product1_out1; // sfix36_En35 + wire signed [35:0] Constant_out1; // sfix36_En35 + wire signed [35:0] Sum_out1; // sfix36_En22 + wire PI_Sat_out2; + wire Clamp_out1; + wire switch_compare_1; + wire signed [35:0] Switch_out1; // sfix36_En35 + wire signed [31:0] I_term; // sfix32_En28 + wire signed [39:0] Add_add_cast; // sfix40_En35 + wire signed [39:0] Add_add_cast_1; // sfix40_En35 + wire signed [39:0] Add_add_temp; // sfix40_En35 + wire signed [31:0] Add_out1; // sfix32_En28 + wire signed [42:0] Sum_add_cast; // sfix43_En28 + wire signed [42:0] Sum_add_cast_1; // sfix43_En28 + wire signed [42:0] Sum_add_temp; // sfix43_En28 + wire signed [35:0] PI_Sat_out1; // sfix36_En22 + wire signed [17:0] Data_Type_Conversion1_out1; // sfix18_En15 + + // Rotor Velocity Control + + + // /Product2 + assign P_term = param_velocity_p_gain * Err; + + + + // /Convert_Data_Type + velocityControlHdl_Convert_Data_Type u_Convert_Data_Type (.In1(P_term), // sfix36_En23 + .Out1(Convert_Data_Type_out1) // sfix36_En22 + ); + + // /Constant2 + assign Constant2_out1 = 18'sb010100111110001011; + + + + // /Product + assign Product_out1 = param_velocity_i_gain * Constant2_out1; + + + + // /Maintain_Range + velocityControlHdl_Maintain_Range_block1 u_Maintain_Range (.In1(Product_out1), // sfix36_En46 + .Out1(Maintain_Range_out1) // sfix18_En28 + ); + + // /Product1 + assign Product1_out1 = Err * Maintain_Range_out1; + + + + // /Constant + assign Constant_out1 = 36'sh000000000; + + + + // /Clamp + velocityControlHdl_Clamp_block1 u_Clamp (.preSat(Sum_out1), // sfix36_En22 + .saturated(PI_Sat_out2), + .preIntegrator(Product1_out1), // sfix36_En35 + .Clamp(Clamp_out1) + ); + + assign switch_compare_1 = (Clamp_out1 > 1'b0 ? 1'b1 : + 1'b0); + + + + // /Switch + assign Switch_out1 = (switch_compare_1 == 1'b0 ? Product1_out1 : + Constant_out1); + + + + // /Add + assign Add_add_cast = Switch_out1; + assign Add_add_cast_1 = {I_term[31], {I_term, 7'b0000000}}; + assign Add_add_temp = Add_add_cast + Add_add_cast_1; + assign Add_out1 = ((Add_add_temp[39] == 1'b0) && (Add_add_temp[38] != 1'b0) ? 32'sb01111111111111111111111111111111 : + ((Add_add_temp[39] == 1'b1) && (Add_add_temp[38] != 1'b1) ? 32'sb10000000000000000000000000000000 : + $signed(Add_add_temp[38:7]))); + + + + // /Reset_Delay + velocityControlHdl_Reset_Delay_block1 u_Reset_Delay (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(Reset_1), + .In(Add_out1), // sfix32_En28 + .Out(I_term) // sfix32_En28 + ); + + // /Sum + assign Sum_add_cast = {Convert_Data_Type_out1[35], {Convert_Data_Type_out1, 6'b000000}}; + assign Sum_add_cast_1 = I_term; + assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1; + assign Sum_out1 = Sum_add_temp[41:6]; + + + + // /PI_Sat + velocityControlHdl_PI_Sat_block1 u_PI_Sat (.In1(Sum_out1), // sfix36_En22 + .Out1(PI_Sat_out1), // sfix36_En22 + .saturated(PI_Sat_out2) + ); + + // /Data Type Conversion1 + assign Data_Type_Conversion1_out1 = PI_Sat_out1[24:7]; + + + + assign Out = Data_Type_Conversion1_out1; + +endmodule // velocityControlHdl_Rotor_Velocity_Control + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Sin_Cos1.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Sin_Cos1.v new file mode 100644 index 000000000..fe1e1cbf3 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Sin_Cos1.v @@ -0,0 +1,4226 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Sin_Cos1.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Sin_Cos1 +// Source Path: velocityControlHdl/Sin_Cos1 +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Sin_Cos1 + ( + x, + sin, + cos + ); + + + input signed [17:0] x; // sfix18_En14 + output signed [17:0] sin; // sfix18_En16 + output signed [17:0] cos; // sfix18_En16 + + parameter signed [17:0] t1_re_0 = 65536; // sfix18 + parameter signed [17:0] t1_re_1 = 65531; // sfix18 + parameter signed [17:0] t1_re_2 = 65516; // sfix18 + parameter signed [17:0] t1_re_3 = 65492; // sfix18 + parameter signed [17:0] t1_re_4 = 65457; // sfix18 + parameter signed [17:0] t1_re_5 = 65413; // sfix18 + parameter signed [17:0] t1_re_6 = 65358; // sfix18 + parameter signed [17:0] t1_re_7 = 65294; // sfix18 + parameter signed [17:0] t1_re_8 = 65220; // sfix18 + parameter signed [17:0] t1_re_9 = 65137; // sfix18 + parameter signed [17:0] t1_re_10 = 65043; // sfix18 + parameter signed [17:0] t1_re_11 = 64940; // sfix18 + parameter signed [17:0] t1_re_12 = 64827; // sfix18 + parameter signed [17:0] t1_re_13 = 64704; // sfix18 + parameter signed [17:0] t1_re_14 = 64571; // sfix18 + parameter signed [17:0] t1_re_15 = 64429; // sfix18 + parameter signed [17:0] t1_re_16 = 64277; // sfix18 + parameter signed [17:0] t1_re_17 = 64115; // sfix18 + parameter signed [17:0] t1_re_18 = 63944; // sfix18 + parameter signed [17:0] t1_re_19 = 63763; // sfix18 + parameter signed [17:0] t1_re_20 = 63572; // sfix18 + parameter signed [17:0] t1_re_21 = 63372; // sfix18 + parameter signed [17:0] t1_re_22 = 63162; // sfix18 + parameter signed [17:0] t1_re_23 = 62943; // sfix18 + parameter signed [17:0] t1_re_24 = 62714; // sfix18 + parameter signed [17:0] t1_re_25 = 62476; // sfix18 + parameter signed [17:0] t1_re_26 = 62228; // sfix18 + parameter signed [17:0] t1_re_27 = 61971; // sfix18 + parameter signed [17:0] t1_re_28 = 61705; // sfix18 + parameter signed [17:0] t1_re_29 = 61429; // sfix18 + parameter signed [17:0] t1_re_30 = 61145; // sfix18 + parameter signed [17:0] t1_re_31 = 60851; // sfix18 + parameter signed [17:0] t1_re_32 = 60547; // sfix18 + parameter signed [17:0] t1_re_33 = 60235; // sfix18 + parameter signed [17:0] t1_re_34 = 59914; // sfix18 + parameter signed [17:0] t1_re_35 = 59583; // sfix18 + parameter signed [17:0] t1_re_36 = 59244; // sfix18 + parameter signed [17:0] t1_re_37 = 58896; // sfix18 + parameter signed [17:0] t1_re_38 = 58538; // sfix18 + parameter signed [17:0] t1_re_39 = 58172; // sfix18 + parameter signed [17:0] t1_re_40 = 57798; // sfix18 + parameter signed [17:0] t1_re_41 = 57414; // sfix18 + parameter signed [17:0] t1_re_42 = 57022; // sfix18 + parameter signed [17:0] t1_re_43 = 56621; // sfix18 + parameter signed [17:0] t1_re_44 = 56212; // sfix18 + parameter signed [17:0] t1_re_45 = 55794; // sfix18 + parameter signed [17:0] t1_re_46 = 55368; // sfix18 + parameter signed [17:0] t1_re_47 = 54934; // sfix18 + parameter signed [17:0] t1_re_48 = 54491; // sfix18 + parameter signed [17:0] t1_re_49 = 54040; // sfix18 + parameter signed [17:0] t1_re_50 = 53581; // sfix18 + parameter signed [17:0] t1_re_51 = 53114; // sfix18 + parameter signed [17:0] t1_re_52 = 52639; // sfix18 + parameter signed [17:0] t1_re_53 = 52156; // sfix18 + parameter signed [17:0] t1_re_54 = 51665; // sfix18 + parameter signed [17:0] t1_re_55 = 51166; // sfix18 + parameter signed [17:0] t1_re_56 = 50660; // sfix18 + parameter signed [17:0] t1_re_57 = 50146; // sfix18 + parameter signed [17:0] t1_re_58 = 49624; // sfix18 + parameter signed [17:0] t1_re_59 = 49095; // sfix18 + parameter signed [17:0] t1_re_60 = 48559; // sfix18 + parameter signed [17:0] t1_re_61 = 48015; // sfix18 + parameter signed [17:0] t1_re_62 = 47464; // sfix18 + parameter signed [17:0] t1_re_63 = 46906; // sfix18 + parameter signed [17:0] t1_re_64 = 46341; // sfix18 + parameter signed [17:0] t1_re_65 = 45769; // sfix18 + parameter signed [17:0] t1_re_66 = 45190; // sfix18 + parameter signed [17:0] t1_re_67 = 44604; // sfix18 + parameter signed [17:0] t1_re_68 = 44011; // sfix18 + parameter signed [17:0] t1_re_69 = 43412; // sfix18 + parameter signed [17:0] t1_re_70 = 42806; // sfix18 + parameter signed [17:0] t1_re_71 = 42194; // sfix18 + parameter signed [17:0] t1_re_72 = 41576; // sfix18 + parameter signed [17:0] t1_re_73 = 40951; // sfix18 + parameter signed [17:0] t1_re_74 = 40320; // sfix18 + parameter signed [17:0] t1_re_75 = 39683; // sfix18 + parameter signed [17:0] t1_re_76 = 39040; // sfix18 + parameter signed [17:0] t1_re_77 = 38391; // sfix18 + parameter signed [17:0] t1_re_78 = 37736; // sfix18 + parameter signed [17:0] t1_re_79 = 37076; // sfix18 + parameter signed [17:0] t1_re_80 = 36410; // sfix18 + parameter signed [17:0] t1_re_81 = 35738; // sfix18 + parameter signed [17:0] t1_re_82 = 35062; // sfix18 + parameter signed [17:0] t1_re_83 = 34380; // sfix18 + parameter signed [17:0] t1_re_84 = 33692; // sfix18 + parameter signed [17:0] t1_re_85 = 33000; // sfix18 + parameter signed [17:0] t1_re_86 = 32303; // sfix18 + parameter signed [17:0] t1_re_87 = 31600; // sfix18 + parameter signed [17:0] t1_re_88 = 30893; // sfix18 + parameter signed [17:0] t1_re_89 = 30182; // sfix18 + parameter signed [17:0] t1_re_90 = 29466; // sfix18 + parameter signed [17:0] t1_re_91 = 28745; // sfix18 + parameter signed [17:0] t1_re_92 = 28020; // sfix18 + parameter signed [17:0] t1_re_93 = 27291; // sfix18 + parameter signed [17:0] t1_re_94 = 26558; // sfix18 + parameter signed [17:0] t1_re_95 = 25821; // sfix18 + parameter signed [17:0] t1_re_96 = 25080; // sfix18 + parameter signed [17:0] t1_re_97 = 24335; // sfix18 + parameter signed [17:0] t1_re_98 = 23586; // sfix18 + parameter signed [17:0] t1_re_99 = 22834; // sfix18 + parameter signed [17:0] t1_re_100 = 22078; // sfix18 + parameter signed [17:0] t1_re_101 = 21320; // sfix18 + parameter signed [17:0] t1_re_102 = 20557; // sfix18 + parameter signed [17:0] t1_re_103 = 19792; // sfix18 + parameter signed [17:0] t1_re_104 = 19024; // sfix18 + parameter signed [17:0] t1_re_105 = 18253; // sfix18 + parameter signed [17:0] t1_re_106 = 17479; // sfix18 + parameter signed [17:0] t1_re_107 = 16703; // sfix18 + parameter signed [17:0] t1_re_108 = 15924; // sfix18 + parameter signed [17:0] t1_re_109 = 15143; // sfix18 + parameter signed [17:0] t1_re_110 = 14359; // sfix18 + parameter signed [17:0] t1_re_111 = 13573; // sfix18 + parameter signed [17:0] t1_re_112 = 12785; // sfix18 + parameter signed [17:0] t1_re_113 = 11996; // sfix18 + parameter signed [17:0] t1_re_114 = 11204; // sfix18 + parameter signed [17:0] t1_re_115 = 10411; // sfix18 + parameter signed [17:0] t1_re_116 = 9616; // sfix18 + parameter signed [17:0] t1_re_117 = 8820; // sfix18 + parameter signed [17:0] t1_re_118 = 8022; // sfix18 + parameter signed [17:0] t1_re_119 = 7224; // sfix18 + parameter signed [17:0] t1_re_120 = 6424; // sfix18 + parameter signed [17:0] t1_re_121 = 5623; // sfix18 + parameter signed [17:0] t1_re_122 = 4821; // sfix18 + parameter signed [17:0] t1_re_123 = 4019; // sfix18 + parameter signed [17:0] t1_re_124 = 3216; // sfix18 + parameter signed [17:0] t1_re_125 = 2412; // sfix18 + parameter signed [17:0] t1_re_126 = 1608; // sfix18 + parameter signed [17:0] t1_re_127 = 804; // sfix18 + parameter signed [17:0] t1_re_128 = 0; // sfix18 + parameter signed [17:0] t1_re_129 = -804; // sfix18 + parameter signed [17:0] t1_re_130 = -1608; // sfix18 + parameter signed [17:0] t1_re_131 = -2412; // sfix18 + parameter signed [17:0] t1_re_132 = -3216; // sfix18 + parameter signed [17:0] t1_re_133 = -4019; // sfix18 + parameter signed [17:0] t1_re_134 = -4821; // sfix18 + parameter signed [17:0] t1_re_135 = -5623; // sfix18 + parameter signed [17:0] t1_re_136 = -6424; // sfix18 + parameter signed [17:0] t1_re_137 = -7224; // sfix18 + parameter signed [17:0] t1_re_138 = -8022; // sfix18 + parameter signed [17:0] t1_re_139 = -8820; // sfix18 + parameter signed [17:0] t1_re_140 = -9616; // sfix18 + parameter signed [17:0] t1_re_141 = -10411; // sfix18 + parameter signed [17:0] t1_re_142 = -11204; // sfix18 + parameter signed [17:0] t1_re_143 = -11996; // sfix18 + parameter signed [17:0] t1_re_144 = -12785; // sfix18 + parameter signed [17:0] t1_re_145 = -13573; // sfix18 + parameter signed [17:0] t1_re_146 = -14359; // sfix18 + parameter signed [17:0] t1_re_147 = -15143; // sfix18 + parameter signed [17:0] t1_re_148 = -15924; // sfix18 + parameter signed [17:0] t1_re_149 = -16703; // sfix18 + parameter signed [17:0] t1_re_150 = -17479; // sfix18 + parameter signed [17:0] t1_re_151 = -18253; // sfix18 + parameter signed [17:0] t1_re_152 = -19024; // sfix18 + parameter signed [17:0] t1_re_153 = -19792; // sfix18 + parameter signed [17:0] t1_re_154 = -20557; // sfix18 + parameter signed [17:0] t1_re_155 = -21320; // sfix18 + parameter signed [17:0] t1_re_156 = -22078; // sfix18 + parameter signed [17:0] t1_re_157 = -22834; // sfix18 + parameter signed [17:0] t1_re_158 = -23586; // sfix18 + parameter signed [17:0] t1_re_159 = -24335; // sfix18 + parameter signed [17:0] t1_re_160 = -25080; // sfix18 + parameter signed [17:0] t1_re_161 = -25821; // sfix18 + parameter signed [17:0] t1_re_162 = -26558; // sfix18 + parameter signed [17:0] t1_re_163 = -27291; // sfix18 + parameter signed [17:0] t1_re_164 = -28020; // sfix18 + parameter signed [17:0] t1_re_165 = -28745; // sfix18 + parameter signed [17:0] t1_re_166 = -29466; // sfix18 + parameter signed [17:0] t1_re_167 = -30182; // sfix18 + parameter signed [17:0] t1_re_168 = -30893; // sfix18 + parameter signed [17:0] t1_re_169 = -31600; // sfix18 + parameter signed [17:0] t1_re_170 = -32303; // sfix18 + parameter signed [17:0] t1_re_171 = -33000; // sfix18 + parameter signed [17:0] t1_re_172 = -33692; // sfix18 + parameter signed [17:0] t1_re_173 = -34380; // sfix18 + parameter signed [17:0] t1_re_174 = -35062; // sfix18 + parameter signed [17:0] t1_re_175 = -35738; // sfix18 + parameter signed [17:0] t1_re_176 = -36410; // sfix18 + parameter signed [17:0] t1_re_177 = -37076; // sfix18 + parameter signed [17:0] t1_re_178 = -37736; // sfix18 + parameter signed [17:0] t1_re_179 = -38391; // sfix18 + parameter signed [17:0] t1_re_180 = -39040; // sfix18 + parameter signed [17:0] t1_re_181 = -39683; // sfix18 + parameter signed [17:0] t1_re_182 = -40320; // sfix18 + parameter signed [17:0] t1_re_183 = -40951; // sfix18 + parameter signed [17:0] t1_re_184 = -41576; // sfix18 + parameter signed [17:0] t1_re_185 = -42194; // sfix18 + parameter signed [17:0] t1_re_186 = -42806; // sfix18 + parameter signed [17:0] t1_re_187 = -43412; // sfix18 + parameter signed [17:0] t1_re_188 = -44011; // sfix18 + parameter signed [17:0] t1_re_189 = -44604; // sfix18 + parameter signed [17:0] t1_re_190 = -45190; // sfix18 + parameter signed [17:0] t1_re_191 = -45769; // sfix18 + parameter signed [17:0] t1_re_192 = -46341; // sfix18 + parameter signed [17:0] t1_re_193 = -46906; // sfix18 + parameter signed [17:0] t1_re_194 = -47464; // sfix18 + parameter signed [17:0] t1_re_195 = -48015; // sfix18 + parameter signed [17:0] t1_re_196 = -48559; // sfix18 + parameter signed [17:0] t1_re_197 = -49095; // sfix18 + parameter signed [17:0] t1_re_198 = -49624; // sfix18 + parameter signed [17:0] t1_re_199 = -50146; // sfix18 + parameter signed [17:0] t1_re_200 = -50660; // sfix18 + parameter signed [17:0] t1_re_201 = -51166; // sfix18 + parameter signed [17:0] t1_re_202 = -51665; // sfix18 + parameter signed [17:0] t1_re_203 = -52156; // sfix18 + parameter signed [17:0] t1_re_204 = -52639; // sfix18 + parameter signed [17:0] t1_re_205 = -53114; // sfix18 + parameter signed [17:0] t1_re_206 = -53581; // sfix18 + parameter signed [17:0] t1_re_207 = -54040; // sfix18 + parameter signed [17:0] t1_re_208 = -54491; // sfix18 + parameter signed [17:0] t1_re_209 = -54934; // sfix18 + parameter signed [17:0] t1_re_210 = -55368; // sfix18 + parameter signed [17:0] t1_re_211 = -55794; // sfix18 + parameter signed [17:0] t1_re_212 = -56212; // sfix18 + parameter signed [17:0] t1_re_213 = -56621; // sfix18 + parameter signed [17:0] t1_re_214 = -57022; // sfix18 + parameter signed [17:0] t1_re_215 = -57414; // sfix18 + parameter signed [17:0] t1_re_216 = -57798; // sfix18 + parameter signed [17:0] t1_re_217 = -58172; // sfix18 + parameter signed [17:0] t1_re_218 = -58538; // sfix18 + parameter signed [17:0] t1_re_219 = -58896; // sfix18 + parameter signed [17:0] t1_re_220 = -59244; // sfix18 + parameter signed [17:0] t1_re_221 = -59583; // sfix18 + parameter signed [17:0] t1_re_222 = -59914; // sfix18 + parameter signed [17:0] t1_re_223 = -60235; // sfix18 + parameter signed [17:0] t1_re_224 = -60547; // sfix18 + parameter signed [17:0] t1_re_225 = -60851; // sfix18 + parameter signed [17:0] t1_re_226 = -61145; // sfix18 + parameter signed [17:0] t1_re_227 = -61429; // sfix18 + parameter signed [17:0] t1_re_228 = -61705; // sfix18 + parameter signed [17:0] t1_re_229 = -61971; // sfix18 + parameter signed [17:0] t1_re_230 = -62228; // sfix18 + parameter signed [17:0] t1_re_231 = -62476; // sfix18 + parameter signed [17:0] t1_re_232 = -62714; // sfix18 + parameter signed [17:0] t1_re_233 = -62943; // sfix18 + parameter signed [17:0] t1_re_234 = -63162; // sfix18 + parameter signed [17:0] t1_re_235 = -63372; // sfix18 + parameter signed [17:0] t1_re_236 = -63572; // sfix18 + parameter signed [17:0] t1_re_237 = -63763; // sfix18 + parameter signed [17:0] t1_re_238 = -63944; // sfix18 + parameter signed [17:0] t1_re_239 = -64115; // sfix18 + parameter signed [17:0] t1_re_240 = -64277; // sfix18 + parameter signed [17:0] t1_re_241 = -64429; // sfix18 + parameter signed [17:0] t1_re_242 = -64571; // sfix18 + parameter signed [17:0] t1_re_243 = -64704; // sfix18 + parameter signed [17:0] t1_re_244 = -64827; // sfix18 + parameter signed [17:0] t1_re_245 = -64940; // sfix18 + parameter signed [17:0] t1_re_246 = -65043; // sfix18 + parameter signed [17:0] t1_re_247 = -65137; // sfix18 + parameter signed [17:0] t1_re_248 = -65220; // sfix18 + parameter signed [17:0] t1_re_249 = -65294; // sfix18 + parameter signed [17:0] t1_re_250 = -65358; // sfix18 + parameter signed [17:0] t1_re_251 = -65413; // sfix18 + parameter signed [17:0] t1_re_252 = -65457; // sfix18 + parameter signed [17:0] t1_re_253 = -65492; // sfix18 + parameter signed [17:0] t1_re_254 = -65516; // sfix18 + parameter signed [17:0] t1_re_255 = -65531; // sfix18 + parameter signed [17:0] t1_re_256 = -65536; // sfix18 + parameter signed [17:0] t1_re_257 = -65531; // sfix18 + parameter signed [17:0] t1_re_258 = -65516; // sfix18 + parameter signed [17:0] t1_re_259 = -65492; // sfix18 + parameter signed [17:0] t1_re_260 = -65457; // sfix18 + parameter signed [17:0] t1_re_261 = -65413; // sfix18 + parameter signed [17:0] t1_re_262 = -65358; // sfix18 + parameter signed [17:0] t1_re_263 = -65294; // sfix18 + parameter signed [17:0] t1_re_264 = -65220; // sfix18 + parameter signed [17:0] t1_re_265 = -65137; // sfix18 + parameter signed [17:0] t1_re_266 = -65043; // sfix18 + parameter signed [17:0] t1_re_267 = -64940; // sfix18 + parameter signed [17:0] t1_re_268 = -64827; // sfix18 + parameter signed [17:0] t1_re_269 = -64704; // sfix18 + parameter signed [17:0] t1_re_270 = -64571; // sfix18 + parameter signed [17:0] t1_re_271 = -64429; // sfix18 + parameter signed [17:0] t1_re_272 = -64277; // sfix18 + parameter signed [17:0] t1_re_273 = -64115; // sfix18 + parameter signed [17:0] t1_re_274 = -63944; // sfix18 + parameter signed [17:0] t1_re_275 = -63763; // sfix18 + parameter signed [17:0] t1_re_276 = -63572; // sfix18 + parameter signed [17:0] t1_re_277 = -63372; // sfix18 + parameter signed [17:0] t1_re_278 = -63162; // sfix18 + parameter signed [17:0] t1_re_279 = -62943; // sfix18 + parameter signed [17:0] t1_re_280 = -62714; // sfix18 + parameter signed [17:0] t1_re_281 = -62476; // sfix18 + parameter signed [17:0] t1_re_282 = -62228; // sfix18 + parameter signed [17:0] t1_re_283 = -61971; // sfix18 + parameter signed [17:0] t1_re_284 = -61705; // sfix18 + parameter signed [17:0] t1_re_285 = -61429; // sfix18 + parameter signed [17:0] t1_re_286 = -61145; // sfix18 + parameter signed [17:0] t1_re_287 = -60851; // sfix18 + parameter signed [17:0] t1_re_288 = -60547; // sfix18 + parameter signed [17:0] t1_re_289 = -60235; // sfix18 + parameter signed [17:0] t1_re_290 = -59914; // sfix18 + parameter signed [17:0] t1_re_291 = -59583; // sfix18 + parameter signed [17:0] t1_re_292 = -59244; // sfix18 + parameter signed [17:0] t1_re_293 = -58896; // sfix18 + parameter signed [17:0] t1_re_294 = -58538; // sfix18 + parameter signed [17:0] t1_re_295 = -58172; // sfix18 + parameter signed [17:0] t1_re_296 = -57798; // sfix18 + parameter signed [17:0] t1_re_297 = -57414; // sfix18 + parameter signed [17:0] t1_re_298 = -57022; // sfix18 + parameter signed [17:0] t1_re_299 = -56621; // sfix18 + parameter signed [17:0] t1_re_300 = -56212; // sfix18 + parameter signed [17:0] t1_re_301 = -55794; // sfix18 + parameter signed [17:0] t1_re_302 = -55368; // sfix18 + parameter signed [17:0] t1_re_303 = -54934; // sfix18 + parameter signed [17:0] t1_re_304 = -54491; // sfix18 + parameter signed [17:0] t1_re_305 = -54040; // sfix18 + parameter signed [17:0] t1_re_306 = -53581; // sfix18 + parameter signed [17:0] t1_re_307 = -53114; // sfix18 + parameter signed [17:0] t1_re_308 = -52639; // sfix18 + parameter signed [17:0] t1_re_309 = -52156; // sfix18 + parameter signed [17:0] t1_re_310 = -51665; // sfix18 + parameter signed [17:0] t1_re_311 = -51166; // sfix18 + parameter signed [17:0] t1_re_312 = -50660; // sfix18 + parameter signed [17:0] t1_re_313 = -50146; // sfix18 + parameter signed [17:0] t1_re_314 = -49624; // sfix18 + parameter signed [17:0] t1_re_315 = -49095; // sfix18 + parameter signed [17:0] t1_re_316 = -48559; // sfix18 + parameter signed [17:0] t1_re_317 = -48015; // sfix18 + parameter signed [17:0] t1_re_318 = -47464; // sfix18 + parameter signed [17:0] t1_re_319 = -46906; // sfix18 + parameter signed [17:0] t1_re_320 = -46341; // sfix18 + parameter signed [17:0] t1_re_321 = -45769; // sfix18 + parameter signed [17:0] t1_re_322 = -45190; // sfix18 + parameter signed [17:0] t1_re_323 = -44604; // sfix18 + parameter signed [17:0] t1_re_324 = -44011; // sfix18 + parameter signed [17:0] t1_re_325 = -43412; // sfix18 + parameter signed [17:0] t1_re_326 = -42806; // sfix18 + parameter signed [17:0] t1_re_327 = -42194; // sfix18 + parameter signed [17:0] t1_re_328 = -41576; // sfix18 + parameter signed [17:0] t1_re_329 = -40951; // sfix18 + parameter signed [17:0] t1_re_330 = -40320; // sfix18 + parameter signed [17:0] t1_re_331 = -39683; // sfix18 + parameter signed [17:0] t1_re_332 = -39040; // sfix18 + parameter signed [17:0] t1_re_333 = -38391; // sfix18 + parameter signed [17:0] t1_re_334 = -37736; // sfix18 + parameter signed [17:0] t1_re_335 = -37076; // sfix18 + parameter signed [17:0] t1_re_336 = -36410; // sfix18 + parameter signed [17:0] t1_re_337 = -35738; // sfix18 + parameter signed [17:0] t1_re_338 = -35062; // sfix18 + parameter signed [17:0] t1_re_339 = -34380; // sfix18 + parameter signed [17:0] t1_re_340 = -33692; // sfix18 + parameter signed [17:0] t1_re_341 = -33000; // sfix18 + parameter signed [17:0] t1_re_342 = -32303; // sfix18 + parameter signed [17:0] t1_re_343 = -31600; // sfix18 + parameter signed [17:0] t1_re_344 = -30893; // sfix18 + parameter signed [17:0] t1_re_345 = -30182; // sfix18 + parameter signed [17:0] t1_re_346 = -29466; // sfix18 + parameter signed [17:0] t1_re_347 = -28745; // sfix18 + parameter signed [17:0] t1_re_348 = -28020; // sfix18 + parameter signed [17:0] t1_re_349 = -27291; // sfix18 + parameter signed [17:0] t1_re_350 = -26558; // sfix18 + parameter signed [17:0] t1_re_351 = -25821; // sfix18 + parameter signed [17:0] t1_re_352 = -25080; // sfix18 + parameter signed [17:0] t1_re_353 = -24335; // sfix18 + parameter signed [17:0] t1_re_354 = -23586; // sfix18 + parameter signed [17:0] t1_re_355 = -22834; // sfix18 + parameter signed [17:0] t1_re_356 = -22078; // sfix18 + parameter signed [17:0] t1_re_357 = -21320; // sfix18 + parameter signed [17:0] t1_re_358 = -20557; // sfix18 + parameter signed [17:0] t1_re_359 = -19792; // sfix18 + parameter signed [17:0] t1_re_360 = -19024; // sfix18 + parameter signed [17:0] t1_re_361 = -18253; // sfix18 + parameter signed [17:0] t1_re_362 = -17479; // sfix18 + parameter signed [17:0] t1_re_363 = -16703; // sfix18 + parameter signed [17:0] t1_re_364 = -15924; // sfix18 + parameter signed [17:0] t1_re_365 = -15143; // sfix18 + parameter signed [17:0] t1_re_366 = -14359; // sfix18 + parameter signed [17:0] t1_re_367 = -13573; // sfix18 + parameter signed [17:0] t1_re_368 = -12785; // sfix18 + parameter signed [17:0] t1_re_369 = -11996; // sfix18 + parameter signed [17:0] t1_re_370 = -11204; // sfix18 + parameter signed [17:0] t1_re_371 = -10411; // sfix18 + parameter signed [17:0] t1_re_372 = -9616; // sfix18 + parameter signed [17:0] t1_re_373 = -8820; // sfix18 + parameter signed [17:0] t1_re_374 = -8022; // sfix18 + parameter signed [17:0] t1_re_375 = -7224; // sfix18 + parameter signed [17:0] t1_re_376 = -6424; // sfix18 + parameter signed [17:0] t1_re_377 = -5623; // sfix18 + parameter signed [17:0] t1_re_378 = -4821; // sfix18 + parameter signed [17:0] t1_re_379 = -4019; // sfix18 + parameter signed [17:0] t1_re_380 = -3216; // sfix18 + parameter signed [17:0] t1_re_381 = -2412; // sfix18 + parameter signed [17:0] t1_re_382 = -1608; // sfix18 + parameter signed [17:0] t1_re_383 = -804; // sfix18 + parameter signed [17:0] t1_re_384 = 0; // sfix18 + parameter signed [17:0] t1_re_385 = 804; // sfix18 + parameter signed [17:0] t1_re_386 = 1608; // sfix18 + parameter signed [17:0] t1_re_387 = 2412; // sfix18 + parameter signed [17:0] t1_re_388 = 3216; // sfix18 + parameter signed [17:0] t1_re_389 = 4019; // sfix18 + parameter signed [17:0] t1_re_390 = 4821; // sfix18 + parameter signed [17:0] t1_re_391 = 5623; // sfix18 + parameter signed [17:0] t1_re_392 = 6424; // sfix18 + parameter signed [17:0] t1_re_393 = 7224; // sfix18 + parameter signed [17:0] t1_re_394 = 8022; // sfix18 + parameter signed [17:0] t1_re_395 = 8820; // sfix18 + parameter signed [17:0] t1_re_396 = 9616; // sfix18 + parameter signed [17:0] t1_re_397 = 10411; // sfix18 + parameter signed [17:0] t1_re_398 = 11204; // sfix18 + parameter signed [17:0] t1_re_399 = 11996; // sfix18 + parameter signed [17:0] t1_re_400 = 12785; // sfix18 + parameter signed [17:0] t1_re_401 = 13573; // sfix18 + parameter signed [17:0] t1_re_402 = 14359; // sfix18 + parameter signed [17:0] t1_re_403 = 15143; // sfix18 + parameter signed [17:0] t1_re_404 = 15924; // sfix18 + parameter signed [17:0] t1_re_405 = 16703; // sfix18 + parameter signed [17:0] t1_re_406 = 17479; // sfix18 + parameter signed [17:0] t1_re_407 = 18253; // sfix18 + parameter signed [17:0] t1_re_408 = 19024; // sfix18 + parameter signed [17:0] t1_re_409 = 19792; // sfix18 + parameter signed [17:0] t1_re_410 = 20557; // sfix18 + parameter signed [17:0] t1_re_411 = 21320; // sfix18 + parameter signed [17:0] t1_re_412 = 22078; // sfix18 + parameter signed [17:0] t1_re_413 = 22834; // sfix18 + parameter signed [17:0] t1_re_414 = 23586; // sfix18 + parameter signed [17:0] t1_re_415 = 24335; // sfix18 + parameter signed [17:0] t1_re_416 = 25080; // sfix18 + parameter signed [17:0] t1_re_417 = 25821; // sfix18 + parameter signed [17:0] t1_re_418 = 26558; // sfix18 + parameter signed [17:0] t1_re_419 = 27291; // sfix18 + parameter signed [17:0] t1_re_420 = 28020; // sfix18 + parameter signed [17:0] t1_re_421 = 28745; // sfix18 + parameter signed [17:0] t1_re_422 = 29466; // sfix18 + parameter signed [17:0] t1_re_423 = 30182; // sfix18 + parameter signed [17:0] t1_re_424 = 30893; // sfix18 + parameter signed [17:0] t1_re_425 = 31600; // sfix18 + parameter signed [17:0] t1_re_426 = 32303; // sfix18 + parameter signed [17:0] t1_re_427 = 33000; // sfix18 + parameter signed [17:0] t1_re_428 = 33692; // sfix18 + parameter signed [17:0] t1_re_429 = 34380; // sfix18 + parameter signed [17:0] t1_re_430 = 35062; // sfix18 + parameter signed [17:0] t1_re_431 = 35738; // sfix18 + parameter signed [17:0] t1_re_432 = 36410; // sfix18 + parameter signed [17:0] t1_re_433 = 37076; // sfix18 + parameter signed [17:0] t1_re_434 = 37736; // sfix18 + parameter signed [17:0] t1_re_435 = 38391; // sfix18 + parameter signed [17:0] t1_re_436 = 39040; // sfix18 + parameter signed [17:0] t1_re_437 = 39683; // sfix18 + parameter signed [17:0] t1_re_438 = 40320; // sfix18 + parameter signed [17:0] t1_re_439 = 40951; // sfix18 + parameter signed [17:0] t1_re_440 = 41576; // sfix18 + parameter signed [17:0] t1_re_441 = 42194; // sfix18 + parameter signed [17:0] t1_re_442 = 42806; // sfix18 + parameter signed [17:0] t1_re_443 = 43412; // sfix18 + parameter signed [17:0] t1_re_444 = 44011; // sfix18 + parameter signed [17:0] t1_re_445 = 44604; // sfix18 + parameter signed [17:0] t1_re_446 = 45190; // sfix18 + parameter signed [17:0] t1_re_447 = 45769; // sfix18 + parameter signed [17:0] t1_re_448 = 46341; // sfix18 + parameter signed [17:0] t1_re_449 = 46906; // sfix18 + parameter signed [17:0] t1_re_450 = 47464; // sfix18 + parameter signed [17:0] t1_re_451 = 48015; // sfix18 + parameter signed [17:0] t1_re_452 = 48559; // sfix18 + parameter signed [17:0] t1_re_453 = 49095; // sfix18 + parameter signed [17:0] t1_re_454 = 49624; // sfix18 + parameter signed [17:0] t1_re_455 = 50146; // sfix18 + parameter signed [17:0] t1_re_456 = 50660; // sfix18 + parameter signed [17:0] t1_re_457 = 51166; // sfix18 + parameter signed [17:0] t1_re_458 = 51665; // sfix18 + parameter signed [17:0] t1_re_459 = 52156; // sfix18 + parameter signed [17:0] t1_re_460 = 52639; // sfix18 + parameter signed [17:0] t1_re_461 = 53114; // sfix18 + parameter signed [17:0] t1_re_462 = 53581; // sfix18 + parameter signed [17:0] t1_re_463 = 54040; // sfix18 + parameter signed [17:0] t1_re_464 = 54491; // sfix18 + parameter signed [17:0] t1_re_465 = 54934; // sfix18 + parameter signed [17:0] t1_re_466 = 55368; // sfix18 + parameter signed [17:0] t1_re_467 = 55794; // sfix18 + parameter signed [17:0] t1_re_468 = 56212; // sfix18 + parameter signed [17:0] t1_re_469 = 56621; // sfix18 + parameter signed [17:0] t1_re_470 = 57022; // sfix18 + parameter signed [17:0] t1_re_471 = 57414; // sfix18 + parameter signed [17:0] t1_re_472 = 57798; // sfix18 + parameter signed [17:0] t1_re_473 = 58172; // sfix18 + parameter signed [17:0] t1_re_474 = 58538; // sfix18 + parameter signed [17:0] t1_re_475 = 58896; // sfix18 + parameter signed [17:0] t1_re_476 = 59244; // sfix18 + parameter signed [17:0] t1_re_477 = 59583; // sfix18 + parameter signed [17:0] t1_re_478 = 59914; // sfix18 + parameter signed [17:0] t1_re_479 = 60235; // sfix18 + parameter signed [17:0] t1_re_480 = 60547; // sfix18 + parameter signed [17:0] t1_re_481 = 60851; // sfix18 + parameter signed [17:0] t1_re_482 = 61145; // sfix18 + parameter signed [17:0] t1_re_483 = 61429; // sfix18 + parameter signed [17:0] t1_re_484 = 61705; // sfix18 + parameter signed [17:0] t1_re_485 = 61971; // sfix18 + parameter signed [17:0] t1_re_486 = 62228; // sfix18 + parameter signed [17:0] t1_re_487 = 62476; // sfix18 + parameter signed [17:0] t1_re_488 = 62714; // sfix18 + parameter signed [17:0] t1_re_489 = 62943; // sfix18 + parameter signed [17:0] t1_re_490 = 63162; // sfix18 + parameter signed [17:0] t1_re_491 = 63372; // sfix18 + parameter signed [17:0] t1_re_492 = 63572; // sfix18 + parameter signed [17:0] t1_re_493 = 63763; // sfix18 + parameter signed [17:0] t1_re_494 = 63944; // sfix18 + parameter signed [17:0] t1_re_495 = 64115; // sfix18 + parameter signed [17:0] t1_re_496 = 64277; // sfix18 + parameter signed [17:0] t1_re_497 = 64429; // sfix18 + parameter signed [17:0] t1_re_498 = 64571; // sfix18 + parameter signed [17:0] t1_re_499 = 64704; // sfix18 + parameter signed [17:0] t1_re_500 = 64827; // sfix18 + parameter signed [17:0] t1_re_501 = 64940; // sfix18 + parameter signed [17:0] t1_re_502 = 65043; // sfix18 + parameter signed [17:0] t1_re_503 = 65137; // sfix18 + parameter signed [17:0] t1_re_504 = 65220; // sfix18 + parameter signed [17:0] t1_re_505 = 65294; // sfix18 + parameter signed [17:0] t1_re_506 = 65358; // sfix18 + parameter signed [17:0] t1_re_507 = 65413; // sfix18 + parameter signed [17:0] t1_re_508 = 65457; // sfix18 + parameter signed [17:0] t1_re_509 = 65492; // sfix18 + parameter signed [17:0] t1_re_510 = 65516; // sfix18 + parameter signed [17:0] t1_re_511 = 65531; // sfix18 + parameter signed [17:0] t1_im_0 = 0; // sfix18 + parameter signed [17:0] t1_im_1 = 804; // sfix18 + parameter signed [17:0] t1_im_2 = 1608; // sfix18 + parameter signed [17:0] t1_im_3 = 2412; // sfix18 + parameter signed [17:0] t1_im_4 = 3216; // sfix18 + parameter signed [17:0] t1_im_5 = 4019; // sfix18 + parameter signed [17:0] t1_im_6 = 4821; // sfix18 + parameter signed [17:0] t1_im_7 = 5623; // sfix18 + parameter signed [17:0] t1_im_8 = 6424; // sfix18 + parameter signed [17:0] t1_im_9 = 7224; // sfix18 + parameter signed [17:0] t1_im_10 = 8022; // sfix18 + parameter signed [17:0] t1_im_11 = 8820; // sfix18 + parameter signed [17:0] t1_im_12 = 9616; // sfix18 + parameter signed [17:0] t1_im_13 = 10411; // sfix18 + parameter signed [17:0] t1_im_14 = 11204; // sfix18 + parameter signed [17:0] t1_im_15 = 11996; // sfix18 + parameter signed [17:0] t1_im_16 = 12785; // sfix18 + parameter signed [17:0] t1_im_17 = 13573; // sfix18 + parameter signed [17:0] t1_im_18 = 14359; // sfix18 + parameter signed [17:0] t1_im_19 = 15143; // sfix18 + parameter signed [17:0] t1_im_20 = 15924; // sfix18 + parameter signed [17:0] t1_im_21 = 16703; // sfix18 + parameter signed [17:0] t1_im_22 = 17479; // sfix18 + parameter signed [17:0] t1_im_23 = 18253; // sfix18 + parameter signed [17:0] t1_im_24 = 19024; // sfix18 + parameter signed [17:0] t1_im_25 = 19792; // sfix18 + parameter signed [17:0] t1_im_26 = 20557; // sfix18 + parameter signed [17:0] t1_im_27 = 21320; // sfix18 + parameter signed [17:0] t1_im_28 = 22078; // sfix18 + parameter signed [17:0] t1_im_29 = 22834; // sfix18 + parameter signed [17:0] t1_im_30 = 23586; // sfix18 + parameter signed [17:0] t1_im_31 = 24335; // sfix18 + parameter signed [17:0] t1_im_32 = 25080; // sfix18 + parameter signed [17:0] t1_im_33 = 25821; // sfix18 + parameter signed [17:0] t1_im_34 = 26558; // sfix18 + parameter signed [17:0] t1_im_35 = 27291; // sfix18 + parameter signed [17:0] t1_im_36 = 28020; // sfix18 + parameter signed [17:0] t1_im_37 = 28745; // sfix18 + parameter signed [17:0] t1_im_38 = 29466; // sfix18 + parameter signed [17:0] t1_im_39 = 30182; // sfix18 + parameter signed [17:0] t1_im_40 = 30893; // sfix18 + parameter signed [17:0] t1_im_41 = 31600; // sfix18 + parameter signed [17:0] t1_im_42 = 32303; // sfix18 + parameter signed [17:0] t1_im_43 = 33000; // sfix18 + parameter signed [17:0] t1_im_44 = 33692; // sfix18 + parameter signed [17:0] t1_im_45 = 34380; // sfix18 + parameter signed [17:0] t1_im_46 = 35062; // sfix18 + parameter signed [17:0] t1_im_47 = 35738; // sfix18 + parameter signed [17:0] t1_im_48 = 36410; // sfix18 + parameter signed [17:0] t1_im_49 = 37076; // sfix18 + parameter signed [17:0] t1_im_50 = 37736; // sfix18 + parameter signed [17:0] t1_im_51 = 38391; // sfix18 + parameter signed [17:0] t1_im_52 = 39040; // sfix18 + parameter signed [17:0] t1_im_53 = 39683; // sfix18 + parameter signed [17:0] t1_im_54 = 40320; // sfix18 + parameter signed [17:0] t1_im_55 = 40951; // sfix18 + parameter signed [17:0] t1_im_56 = 41576; // sfix18 + parameter signed [17:0] t1_im_57 = 42194; // sfix18 + parameter signed [17:0] t1_im_58 = 42806; // sfix18 + parameter signed [17:0] t1_im_59 = 43412; // sfix18 + parameter signed [17:0] t1_im_60 = 44011; // sfix18 + parameter signed [17:0] t1_im_61 = 44604; // sfix18 + parameter signed [17:0] t1_im_62 = 45190; // sfix18 + parameter signed [17:0] t1_im_63 = 45769; // sfix18 + parameter signed [17:0] t1_im_64 = 46341; // sfix18 + parameter signed [17:0] t1_im_65 = 46906; // sfix18 + parameter signed [17:0] t1_im_66 = 47464; // sfix18 + parameter signed [17:0] t1_im_67 = 48015; // sfix18 + parameter signed [17:0] t1_im_68 = 48559; // sfix18 + parameter signed [17:0] t1_im_69 = 49095; // sfix18 + parameter signed [17:0] t1_im_70 = 49624; // sfix18 + parameter signed [17:0] t1_im_71 = 50146; // sfix18 + parameter signed [17:0] t1_im_72 = 50660; // sfix18 + parameter signed [17:0] t1_im_73 = 51166; // sfix18 + parameter signed [17:0] t1_im_74 = 51665; // sfix18 + parameter signed [17:0] t1_im_75 = 52156; // sfix18 + parameter signed [17:0] t1_im_76 = 52639; // sfix18 + parameter signed [17:0] t1_im_77 = 53114; // sfix18 + parameter signed [17:0] t1_im_78 = 53581; // sfix18 + parameter signed [17:0] t1_im_79 = 54040; // sfix18 + parameter signed [17:0] t1_im_80 = 54491; // sfix18 + parameter signed [17:0] t1_im_81 = 54934; // sfix18 + parameter signed [17:0] t1_im_82 = 55368; // sfix18 + parameter signed [17:0] t1_im_83 = 55794; // sfix18 + parameter signed [17:0] t1_im_84 = 56212; // sfix18 + parameter signed [17:0] t1_im_85 = 56621; // sfix18 + parameter signed [17:0] t1_im_86 = 57022; // sfix18 + parameter signed [17:0] t1_im_87 = 57414; // sfix18 + parameter signed [17:0] t1_im_88 = 57798; // sfix18 + parameter signed [17:0] t1_im_89 = 58172; // sfix18 + parameter signed [17:0] t1_im_90 = 58538; // sfix18 + parameter signed [17:0] t1_im_91 = 58896; // sfix18 + parameter signed [17:0] t1_im_92 = 59244; // sfix18 + parameter signed [17:0] t1_im_93 = 59583; // sfix18 + parameter signed [17:0] t1_im_94 = 59914; // sfix18 + parameter signed [17:0] t1_im_95 = 60235; // sfix18 + parameter signed [17:0] t1_im_96 = 60547; // sfix18 + parameter signed [17:0] t1_im_97 = 60851; // sfix18 + parameter signed [17:0] t1_im_98 = 61145; // sfix18 + parameter signed [17:0] t1_im_99 = 61429; // sfix18 + parameter signed [17:0] t1_im_100 = 61705; // sfix18 + parameter signed [17:0] t1_im_101 = 61971; // sfix18 + parameter signed [17:0] t1_im_102 = 62228; // sfix18 + parameter signed [17:0] t1_im_103 = 62476; // sfix18 + parameter signed [17:0] t1_im_104 = 62714; // sfix18 + parameter signed [17:0] t1_im_105 = 62943; // sfix18 + parameter signed [17:0] t1_im_106 = 63162; // sfix18 + parameter signed [17:0] t1_im_107 = 63372; // sfix18 + parameter signed [17:0] t1_im_108 = 63572; // sfix18 + parameter signed [17:0] t1_im_109 = 63763; // sfix18 + parameter signed [17:0] t1_im_110 = 63944; // sfix18 + parameter signed [17:0] t1_im_111 = 64115; // sfix18 + parameter signed [17:0] t1_im_112 = 64277; // sfix18 + parameter signed [17:0] t1_im_113 = 64429; // sfix18 + parameter signed [17:0] t1_im_114 = 64571; // sfix18 + parameter signed [17:0] t1_im_115 = 64704; // sfix18 + parameter signed [17:0] t1_im_116 = 64827; // sfix18 + parameter signed [17:0] t1_im_117 = 64940; // sfix18 + parameter signed [17:0] t1_im_118 = 65043; // sfix18 + parameter signed [17:0] t1_im_119 = 65137; // sfix18 + parameter signed [17:0] t1_im_120 = 65220; // sfix18 + parameter signed [17:0] t1_im_121 = 65294; // sfix18 + parameter signed [17:0] t1_im_122 = 65358; // sfix18 + parameter signed [17:0] t1_im_123 = 65413; // sfix18 + parameter signed [17:0] t1_im_124 = 65457; // sfix18 + parameter signed [17:0] t1_im_125 = 65492; // sfix18 + parameter signed [17:0] t1_im_126 = 65516; // sfix18 + parameter signed [17:0] t1_im_127 = 65531; // sfix18 + parameter signed [17:0] t1_im_128 = 65536; // sfix18 + parameter signed [17:0] t1_im_129 = 65531; // sfix18 + parameter signed [17:0] t1_im_130 = 65516; // sfix18 + parameter signed [17:0] t1_im_131 = 65492; // sfix18 + parameter signed [17:0] t1_im_132 = 65457; // sfix18 + parameter signed [17:0] t1_im_133 = 65413; // sfix18 + parameter signed [17:0] t1_im_134 = 65358; // sfix18 + parameter signed [17:0] t1_im_135 = 65294; // sfix18 + parameter signed [17:0] t1_im_136 = 65220; // sfix18 + parameter signed [17:0] t1_im_137 = 65137; // sfix18 + parameter signed [17:0] t1_im_138 = 65043; // sfix18 + parameter signed [17:0] t1_im_139 = 64940; // sfix18 + parameter signed [17:0] t1_im_140 = 64827; // sfix18 + parameter signed [17:0] t1_im_141 = 64704; // sfix18 + parameter signed [17:0] t1_im_142 = 64571; // sfix18 + parameter signed [17:0] t1_im_143 = 64429; // sfix18 + parameter signed [17:0] t1_im_144 = 64277; // sfix18 + parameter signed [17:0] t1_im_145 = 64115; // sfix18 + parameter signed [17:0] t1_im_146 = 63944; // sfix18 + parameter signed [17:0] t1_im_147 = 63763; // sfix18 + parameter signed [17:0] t1_im_148 = 63572; // sfix18 + parameter signed [17:0] t1_im_149 = 63372; // sfix18 + parameter signed [17:0] t1_im_150 = 63162; // sfix18 + parameter signed [17:0] t1_im_151 = 62943; // sfix18 + parameter signed [17:0] t1_im_152 = 62714; // sfix18 + parameter signed [17:0] t1_im_153 = 62476; // sfix18 + parameter signed [17:0] t1_im_154 = 62228; // sfix18 + parameter signed [17:0] t1_im_155 = 61971; // sfix18 + parameter signed [17:0] t1_im_156 = 61705; // sfix18 + parameter signed [17:0] t1_im_157 = 61429; // sfix18 + parameter signed [17:0] t1_im_158 = 61145; // sfix18 + parameter signed [17:0] t1_im_159 = 60851; // sfix18 + parameter signed [17:0] t1_im_160 = 60547; // sfix18 + parameter signed [17:0] t1_im_161 = 60235; // sfix18 + parameter signed [17:0] t1_im_162 = 59914; // sfix18 + parameter signed [17:0] t1_im_163 = 59583; // sfix18 + parameter signed [17:0] t1_im_164 = 59244; // sfix18 + parameter signed [17:0] t1_im_165 = 58896; // sfix18 + parameter signed [17:0] t1_im_166 = 58538; // sfix18 + parameter signed [17:0] t1_im_167 = 58172; // sfix18 + parameter signed [17:0] t1_im_168 = 57798; // sfix18 + parameter signed [17:0] t1_im_169 = 57414; // sfix18 + parameter signed [17:0] t1_im_170 = 57022; // sfix18 + parameter signed [17:0] t1_im_171 = 56621; // sfix18 + parameter signed [17:0] t1_im_172 = 56212; // sfix18 + parameter signed [17:0] t1_im_173 = 55794; // sfix18 + parameter signed [17:0] t1_im_174 = 55368; // sfix18 + parameter signed [17:0] t1_im_175 = 54934; // sfix18 + parameter signed [17:0] t1_im_176 = 54491; // sfix18 + parameter signed [17:0] t1_im_177 = 54040; // sfix18 + parameter signed [17:0] t1_im_178 = 53581; // sfix18 + parameter signed [17:0] t1_im_179 = 53114; // sfix18 + parameter signed [17:0] t1_im_180 = 52639; // sfix18 + parameter signed [17:0] t1_im_181 = 52156; // sfix18 + parameter signed [17:0] t1_im_182 = 51665; // sfix18 + parameter signed [17:0] t1_im_183 = 51166; // sfix18 + parameter signed [17:0] t1_im_184 = 50660; // sfix18 + parameter signed [17:0] t1_im_185 = 50146; // sfix18 + parameter signed [17:0] t1_im_186 = 49624; // sfix18 + parameter signed [17:0] t1_im_187 = 49095; // sfix18 + parameter signed [17:0] t1_im_188 = 48559; // sfix18 + parameter signed [17:0] t1_im_189 = 48015; // sfix18 + parameter signed [17:0] t1_im_190 = 47464; // sfix18 + parameter signed [17:0] t1_im_191 = 46906; // sfix18 + parameter signed [17:0] t1_im_192 = 46341; // sfix18 + parameter signed [17:0] t1_im_193 = 45769; // sfix18 + parameter signed [17:0] t1_im_194 = 45190; // sfix18 + parameter signed [17:0] t1_im_195 = 44604; // sfix18 + parameter signed [17:0] t1_im_196 = 44011; // sfix18 + parameter signed [17:0] t1_im_197 = 43412; // sfix18 + parameter signed [17:0] t1_im_198 = 42806; // sfix18 + parameter signed [17:0] t1_im_199 = 42194; // sfix18 + parameter signed [17:0] t1_im_200 = 41576; // sfix18 + parameter signed [17:0] t1_im_201 = 40951; // sfix18 + parameter signed [17:0] t1_im_202 = 40320; // sfix18 + parameter signed [17:0] t1_im_203 = 39683; // sfix18 + parameter signed [17:0] t1_im_204 = 39040; // sfix18 + parameter signed [17:0] t1_im_205 = 38391; // sfix18 + parameter signed [17:0] t1_im_206 = 37736; // sfix18 + parameter signed [17:0] t1_im_207 = 37076; // sfix18 + parameter signed [17:0] t1_im_208 = 36410; // sfix18 + parameter signed [17:0] t1_im_209 = 35738; // sfix18 + parameter signed [17:0] t1_im_210 = 35062; // sfix18 + parameter signed [17:0] t1_im_211 = 34380; // sfix18 + parameter signed [17:0] t1_im_212 = 33692; // sfix18 + parameter signed [17:0] t1_im_213 = 33000; // sfix18 + parameter signed [17:0] t1_im_214 = 32303; // sfix18 + parameter signed [17:0] t1_im_215 = 31600; // sfix18 + parameter signed [17:0] t1_im_216 = 30893; // sfix18 + parameter signed [17:0] t1_im_217 = 30182; // sfix18 + parameter signed [17:0] t1_im_218 = 29466; // sfix18 + parameter signed [17:0] t1_im_219 = 28745; // sfix18 + parameter signed [17:0] t1_im_220 = 28020; // sfix18 + parameter signed [17:0] t1_im_221 = 27291; // sfix18 + parameter signed [17:0] t1_im_222 = 26558; // sfix18 + parameter signed [17:0] t1_im_223 = 25821; // sfix18 + parameter signed [17:0] t1_im_224 = 25080; // sfix18 + parameter signed [17:0] t1_im_225 = 24335; // sfix18 + parameter signed [17:0] t1_im_226 = 23586; // sfix18 + parameter signed [17:0] t1_im_227 = 22834; // sfix18 + parameter signed [17:0] t1_im_228 = 22078; // sfix18 + parameter signed [17:0] t1_im_229 = 21320; // sfix18 + parameter signed [17:0] t1_im_230 = 20557; // sfix18 + parameter signed [17:0] t1_im_231 = 19792; // sfix18 + parameter signed [17:0] t1_im_232 = 19024; // sfix18 + parameter signed [17:0] t1_im_233 = 18253; // sfix18 + parameter signed [17:0] t1_im_234 = 17479; // sfix18 + parameter signed [17:0] t1_im_235 = 16703; // sfix18 + parameter signed [17:0] t1_im_236 = 15924; // sfix18 + parameter signed [17:0] t1_im_237 = 15143; // sfix18 + parameter signed [17:0] t1_im_238 = 14359; // sfix18 + parameter signed [17:0] t1_im_239 = 13573; // sfix18 + parameter signed [17:0] t1_im_240 = 12785; // sfix18 + parameter signed [17:0] t1_im_241 = 11996; // sfix18 + parameter signed [17:0] t1_im_242 = 11204; // sfix18 + parameter signed [17:0] t1_im_243 = 10411; // sfix18 + parameter signed [17:0] t1_im_244 = 9616; // sfix18 + parameter signed [17:0] t1_im_245 = 8820; // sfix18 + parameter signed [17:0] t1_im_246 = 8022; // sfix18 + parameter signed [17:0] t1_im_247 = 7224; // sfix18 + parameter signed [17:0] t1_im_248 = 6424; // sfix18 + parameter signed [17:0] t1_im_249 = 5623; // sfix18 + parameter signed [17:0] t1_im_250 = 4821; // sfix18 + parameter signed [17:0] t1_im_251 = 4019; // sfix18 + parameter signed [17:0] t1_im_252 = 3216; // sfix18 + parameter signed [17:0] t1_im_253 = 2412; // sfix18 + parameter signed [17:0] t1_im_254 = 1608; // sfix18 + parameter signed [17:0] t1_im_255 = 804; // sfix18 + parameter signed [17:0] t1_im_256 = 0; // sfix18 + parameter signed [17:0] t1_im_257 = -804; // sfix18 + parameter signed [17:0] t1_im_258 = -1608; // sfix18 + parameter signed [17:0] t1_im_259 = -2412; // sfix18 + parameter signed [17:0] t1_im_260 = -3216; // sfix18 + parameter signed [17:0] t1_im_261 = -4019; // sfix18 + parameter signed [17:0] t1_im_262 = -4821; // sfix18 + parameter signed [17:0] t1_im_263 = -5623; // sfix18 + parameter signed [17:0] t1_im_264 = -6424; // sfix18 + parameter signed [17:0] t1_im_265 = -7224; // sfix18 + parameter signed [17:0] t1_im_266 = -8022; // sfix18 + parameter signed [17:0] t1_im_267 = -8820; // sfix18 + parameter signed [17:0] t1_im_268 = -9616; // sfix18 + parameter signed [17:0] t1_im_269 = -10411; // sfix18 + parameter signed [17:0] t1_im_270 = -11204; // sfix18 + parameter signed [17:0] t1_im_271 = -11996; // sfix18 + parameter signed [17:0] t1_im_272 = -12785; // sfix18 + parameter signed [17:0] t1_im_273 = -13573; // sfix18 + parameter signed [17:0] t1_im_274 = -14359; // sfix18 + parameter signed [17:0] t1_im_275 = -15143; // sfix18 + parameter signed [17:0] t1_im_276 = -15924; // sfix18 + parameter signed [17:0] t1_im_277 = -16703; // sfix18 + parameter signed [17:0] t1_im_278 = -17479; // sfix18 + parameter signed [17:0] t1_im_279 = -18253; // sfix18 + parameter signed [17:0] t1_im_280 = -19024; // sfix18 + parameter signed [17:0] t1_im_281 = -19792; // sfix18 + parameter signed [17:0] t1_im_282 = -20557; // sfix18 + parameter signed [17:0] t1_im_283 = -21320; // sfix18 + parameter signed [17:0] t1_im_284 = -22078; // sfix18 + parameter signed [17:0] t1_im_285 = -22834; // sfix18 + parameter signed [17:0] t1_im_286 = -23586; // sfix18 + parameter signed [17:0] t1_im_287 = -24335; // sfix18 + parameter signed [17:0] t1_im_288 = -25080; // sfix18 + parameter signed [17:0] t1_im_289 = -25821; // sfix18 + parameter signed [17:0] t1_im_290 = -26558; // sfix18 + parameter signed [17:0] t1_im_291 = -27291; // sfix18 + parameter signed [17:0] t1_im_292 = -28020; // sfix18 + parameter signed [17:0] t1_im_293 = -28745; // sfix18 + parameter signed [17:0] t1_im_294 = -29466; // sfix18 + parameter signed [17:0] t1_im_295 = -30182; // sfix18 + parameter signed [17:0] t1_im_296 = -30893; // sfix18 + parameter signed [17:0] t1_im_297 = -31600; // sfix18 + parameter signed [17:0] t1_im_298 = -32303; // sfix18 + parameter signed [17:0] t1_im_299 = -33000; // sfix18 + parameter signed [17:0] t1_im_300 = -33692; // sfix18 + parameter signed [17:0] t1_im_301 = -34380; // sfix18 + parameter signed [17:0] t1_im_302 = -35062; // sfix18 + parameter signed [17:0] t1_im_303 = -35738; // sfix18 + parameter signed [17:0] t1_im_304 = -36410; // sfix18 + parameter signed [17:0] t1_im_305 = -37076; // sfix18 + parameter signed [17:0] t1_im_306 = -37736; // sfix18 + parameter signed [17:0] t1_im_307 = -38391; // sfix18 + parameter signed [17:0] t1_im_308 = -39040; // sfix18 + parameter signed [17:0] t1_im_309 = -39683; // sfix18 + parameter signed [17:0] t1_im_310 = -40320; // sfix18 + parameter signed [17:0] t1_im_311 = -40951; // sfix18 + parameter signed [17:0] t1_im_312 = -41576; // sfix18 + parameter signed [17:0] t1_im_313 = -42194; // sfix18 + parameter signed [17:0] t1_im_314 = -42806; // sfix18 + parameter signed [17:0] t1_im_315 = -43412; // sfix18 + parameter signed [17:0] t1_im_316 = -44011; // sfix18 + parameter signed [17:0] t1_im_317 = -44604; // sfix18 + parameter signed [17:0] t1_im_318 = -45190; // sfix18 + parameter signed [17:0] t1_im_319 = -45769; // sfix18 + parameter signed [17:0] t1_im_320 = -46341; // sfix18 + parameter signed [17:0] t1_im_321 = -46906; // sfix18 + parameter signed [17:0] t1_im_322 = -47464; // sfix18 + parameter signed [17:0] t1_im_323 = -48015; // sfix18 + parameter signed [17:0] t1_im_324 = -48559; // sfix18 + parameter signed [17:0] t1_im_325 = -49095; // sfix18 + parameter signed [17:0] t1_im_326 = -49624; // sfix18 + parameter signed [17:0] t1_im_327 = -50146; // sfix18 + parameter signed [17:0] t1_im_328 = -50660; // sfix18 + parameter signed [17:0] t1_im_329 = -51166; // sfix18 + parameter signed [17:0] t1_im_330 = -51665; // sfix18 + parameter signed [17:0] t1_im_331 = -52156; // sfix18 + parameter signed [17:0] t1_im_332 = -52639; // sfix18 + parameter signed [17:0] t1_im_333 = -53114; // sfix18 + parameter signed [17:0] t1_im_334 = -53581; // sfix18 + parameter signed [17:0] t1_im_335 = -54040; // sfix18 + parameter signed [17:0] t1_im_336 = -54491; // sfix18 + parameter signed [17:0] t1_im_337 = -54934; // sfix18 + parameter signed [17:0] t1_im_338 = -55368; // sfix18 + parameter signed [17:0] t1_im_339 = -55794; // sfix18 + parameter signed [17:0] t1_im_340 = -56212; // sfix18 + parameter signed [17:0] t1_im_341 = -56621; // sfix18 + parameter signed [17:0] t1_im_342 = -57022; // sfix18 + parameter signed [17:0] t1_im_343 = -57414; // sfix18 + parameter signed [17:0] t1_im_344 = -57798; // sfix18 + parameter signed [17:0] t1_im_345 = -58172; // sfix18 + parameter signed [17:0] t1_im_346 = -58538; // sfix18 + parameter signed [17:0] t1_im_347 = -58896; // sfix18 + parameter signed [17:0] t1_im_348 = -59244; // sfix18 + parameter signed [17:0] t1_im_349 = -59583; // sfix18 + parameter signed [17:0] t1_im_350 = -59914; // sfix18 + parameter signed [17:0] t1_im_351 = -60235; // sfix18 + parameter signed [17:0] t1_im_352 = -60547; // sfix18 + parameter signed [17:0] t1_im_353 = -60851; // sfix18 + parameter signed [17:0] t1_im_354 = -61145; // sfix18 + parameter signed [17:0] t1_im_355 = -61429; // sfix18 + parameter signed [17:0] t1_im_356 = -61705; // sfix18 + parameter signed [17:0] t1_im_357 = -61971; // sfix18 + parameter signed [17:0] t1_im_358 = -62228; // sfix18 + parameter signed [17:0] t1_im_359 = -62476; // sfix18 + parameter signed [17:0] t1_im_360 = -62714; // sfix18 + parameter signed [17:0] t1_im_361 = -62943; // sfix18 + parameter signed [17:0] t1_im_362 = -63162; // sfix18 + parameter signed [17:0] t1_im_363 = -63372; // sfix18 + parameter signed [17:0] t1_im_364 = -63572; // sfix18 + parameter signed [17:0] t1_im_365 = -63763; // sfix18 + parameter signed [17:0] t1_im_366 = -63944; // sfix18 + parameter signed [17:0] t1_im_367 = -64115; // sfix18 + parameter signed [17:0] t1_im_368 = -64277; // sfix18 + parameter signed [17:0] t1_im_369 = -64429; // sfix18 + parameter signed [17:0] t1_im_370 = -64571; // sfix18 + parameter signed [17:0] t1_im_371 = -64704; // sfix18 + parameter signed [17:0] t1_im_372 = -64827; // sfix18 + parameter signed [17:0] t1_im_373 = -64940; // sfix18 + parameter signed [17:0] t1_im_374 = -65043; // sfix18 + parameter signed [17:0] t1_im_375 = -65137; // sfix18 + parameter signed [17:0] t1_im_376 = -65220; // sfix18 + parameter signed [17:0] t1_im_377 = -65294; // sfix18 + parameter signed [17:0] t1_im_378 = -65358; // sfix18 + parameter signed [17:0] t1_im_379 = -65413; // sfix18 + parameter signed [17:0] t1_im_380 = -65457; // sfix18 + parameter signed [17:0] t1_im_381 = -65492; // sfix18 + parameter signed [17:0] t1_im_382 = -65516; // sfix18 + parameter signed [17:0] t1_im_383 = -65531; // sfix18 + parameter signed [17:0] t1_im_384 = -65536; // sfix18 + parameter signed [17:0] t1_im_385 = -65531; // sfix18 + parameter signed [17:0] t1_im_386 = -65516; // sfix18 + parameter signed [17:0] t1_im_387 = -65492; // sfix18 + parameter signed [17:0] t1_im_388 = -65457; // sfix18 + parameter signed [17:0] t1_im_389 = -65413; // sfix18 + parameter signed [17:0] t1_im_390 = -65358; // sfix18 + parameter signed [17:0] t1_im_391 = -65294; // sfix18 + parameter signed [17:0] t1_im_392 = -65220; // sfix18 + parameter signed [17:0] t1_im_393 = -65137; // sfix18 + parameter signed [17:0] t1_im_394 = -65043; // sfix18 + parameter signed [17:0] t1_im_395 = -64940; // sfix18 + parameter signed [17:0] t1_im_396 = -64827; // sfix18 + parameter signed [17:0] t1_im_397 = -64704; // sfix18 + parameter signed [17:0] t1_im_398 = -64571; // sfix18 + parameter signed [17:0] t1_im_399 = -64429; // sfix18 + parameter signed [17:0] t1_im_400 = -64277; // sfix18 + parameter signed [17:0] t1_im_401 = -64115; // sfix18 + parameter signed [17:0] t1_im_402 = -63944; // sfix18 + parameter signed [17:0] t1_im_403 = -63763; // sfix18 + parameter signed [17:0] t1_im_404 = -63572; // sfix18 + parameter signed [17:0] t1_im_405 = -63372; // sfix18 + parameter signed [17:0] t1_im_406 = -63162; // sfix18 + parameter signed [17:0] t1_im_407 = -62943; // sfix18 + parameter signed [17:0] t1_im_408 = -62714; // sfix18 + parameter signed [17:0] t1_im_409 = -62476; // sfix18 + parameter signed [17:0] t1_im_410 = -62228; // sfix18 + parameter signed [17:0] t1_im_411 = -61971; // sfix18 + parameter signed [17:0] t1_im_412 = -61705; // sfix18 + parameter signed [17:0] t1_im_413 = -61429; // sfix18 + parameter signed [17:0] t1_im_414 = -61145; // sfix18 + parameter signed [17:0] t1_im_415 = -60851; // sfix18 + parameter signed [17:0] t1_im_416 = -60547; // sfix18 + parameter signed [17:0] t1_im_417 = -60235; // sfix18 + parameter signed [17:0] t1_im_418 = -59914; // sfix18 + parameter signed [17:0] t1_im_419 = -59583; // sfix18 + parameter signed [17:0] t1_im_420 = -59244; // sfix18 + parameter signed [17:0] t1_im_421 = -58896; // sfix18 + parameter signed [17:0] t1_im_422 = -58538; // sfix18 + parameter signed [17:0] t1_im_423 = -58172; // sfix18 + parameter signed [17:0] t1_im_424 = -57798; // sfix18 + parameter signed [17:0] t1_im_425 = -57414; // sfix18 + parameter signed [17:0] t1_im_426 = -57022; // sfix18 + parameter signed [17:0] t1_im_427 = -56621; // sfix18 + parameter signed [17:0] t1_im_428 = -56212; // sfix18 + parameter signed [17:0] t1_im_429 = -55794; // sfix18 + parameter signed [17:0] t1_im_430 = -55368; // sfix18 + parameter signed [17:0] t1_im_431 = -54934; // sfix18 + parameter signed [17:0] t1_im_432 = -54491; // sfix18 + parameter signed [17:0] t1_im_433 = -54040; // sfix18 + parameter signed [17:0] t1_im_434 = -53581; // sfix18 + parameter signed [17:0] t1_im_435 = -53114; // sfix18 + parameter signed [17:0] t1_im_436 = -52639; // sfix18 + parameter signed [17:0] t1_im_437 = -52156; // sfix18 + parameter signed [17:0] t1_im_438 = -51665; // sfix18 + parameter signed [17:0] t1_im_439 = -51166; // sfix18 + parameter signed [17:0] t1_im_440 = -50660; // sfix18 + parameter signed [17:0] t1_im_441 = -50146; // sfix18 + parameter signed [17:0] t1_im_442 = -49624; // sfix18 + parameter signed [17:0] t1_im_443 = -49095; // sfix18 + parameter signed [17:0] t1_im_444 = -48559; // sfix18 + parameter signed [17:0] t1_im_445 = -48015; // sfix18 + parameter signed [17:0] t1_im_446 = -47464; // sfix18 + parameter signed [17:0] t1_im_447 = -46906; // sfix18 + parameter signed [17:0] t1_im_448 = -46341; // sfix18 + parameter signed [17:0] t1_im_449 = -45769; // sfix18 + parameter signed [17:0] t1_im_450 = -45190; // sfix18 + parameter signed [17:0] t1_im_451 = -44604; // sfix18 + parameter signed [17:0] t1_im_452 = -44011; // sfix18 + parameter signed [17:0] t1_im_453 = -43412; // sfix18 + parameter signed [17:0] t1_im_454 = -42806; // sfix18 + parameter signed [17:0] t1_im_455 = -42194; // sfix18 + parameter signed [17:0] t1_im_456 = -41576; // sfix18 + parameter signed [17:0] t1_im_457 = -40951; // sfix18 + parameter signed [17:0] t1_im_458 = -40320; // sfix18 + parameter signed [17:0] t1_im_459 = -39683; // sfix18 + parameter signed [17:0] t1_im_460 = -39040; // sfix18 + parameter signed [17:0] t1_im_461 = -38391; // sfix18 + parameter signed [17:0] t1_im_462 = -37736; // sfix18 + parameter signed [17:0] t1_im_463 = -37076; // sfix18 + parameter signed [17:0] t1_im_464 = -36410; // sfix18 + parameter signed [17:0] t1_im_465 = -35738; // sfix18 + parameter signed [17:0] t1_im_466 = -35062; // sfix18 + parameter signed [17:0] t1_im_467 = -34380; // sfix18 + parameter signed [17:0] t1_im_468 = -33692; // sfix18 + parameter signed [17:0] t1_im_469 = -33000; // sfix18 + parameter signed [17:0] t1_im_470 = -32303; // sfix18 + parameter signed [17:0] t1_im_471 = -31600; // sfix18 + parameter signed [17:0] t1_im_472 = -30893; // sfix18 + parameter signed [17:0] t1_im_473 = -30182; // sfix18 + parameter signed [17:0] t1_im_474 = -29466; // sfix18 + parameter signed [17:0] t1_im_475 = -28745; // sfix18 + parameter signed [17:0] t1_im_476 = -28020; // sfix18 + parameter signed [17:0] t1_im_477 = -27291; // sfix18 + parameter signed [17:0] t1_im_478 = -26558; // sfix18 + parameter signed [17:0] t1_im_479 = -25821; // sfix18 + parameter signed [17:0] t1_im_480 = -25080; // sfix18 + parameter signed [17:0] t1_im_481 = -24335; // sfix18 + parameter signed [17:0] t1_im_482 = -23586; // sfix18 + parameter signed [17:0] t1_im_483 = -22834; // sfix18 + parameter signed [17:0] t1_im_484 = -22078; // sfix18 + parameter signed [17:0] t1_im_485 = -21320; // sfix18 + parameter signed [17:0] t1_im_486 = -20557; // sfix18 + parameter signed [17:0] t1_im_487 = -19792; // sfix18 + parameter signed [17:0] t1_im_488 = -19024; // sfix18 + parameter signed [17:0] t1_im_489 = -18253; // sfix18 + parameter signed [17:0] t1_im_490 = -17479; // sfix18 + parameter signed [17:0] t1_im_491 = -16703; // sfix18 + parameter signed [17:0] t1_im_492 = -15924; // sfix18 + parameter signed [17:0] t1_im_493 = -15143; // sfix18 + parameter signed [17:0] t1_im_494 = -14359; // sfix18 + parameter signed [17:0] t1_im_495 = -13573; // sfix18 + parameter signed [17:0] t1_im_496 = -12785; // sfix18 + parameter signed [17:0] t1_im_497 = -11996; // sfix18 + parameter signed [17:0] t1_im_498 = -11204; // sfix18 + parameter signed [17:0] t1_im_499 = -10411; // sfix18 + parameter signed [17:0] t1_im_500 = -9616; // sfix18 + parameter signed [17:0] t1_im_501 = -8820; // sfix18 + parameter signed [17:0] t1_im_502 = -8022; // sfix18 + parameter signed [17:0] t1_im_503 = -7224; // sfix18 + parameter signed [17:0] t1_im_504 = -6424; // sfix18 + parameter signed [17:0] t1_im_505 = -5623; // sfix18 + parameter signed [17:0] t1_im_506 = -4821; // sfix18 + parameter signed [17:0] t1_im_507 = -4019; // sfix18 + parameter signed [17:0] t1_im_508 = -3216; // sfix18 + parameter signed [17:0] t1_im_509 = -2412; // sfix18 + parameter signed [17:0] t1_im_510 = -1608; // sfix18 + parameter signed [17:0] t1_im_511 = -804; // sfix18 + parameter signed [17:0] t1_re_0_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_1_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_2_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_3_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_4_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_5_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_6_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_7_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_8_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_9_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_10_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_11_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_12_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_13_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_14_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_15_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_16_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_17_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_18_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_19_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_20_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_21_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_22_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_23_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_24_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_25_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_26_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_27_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_28_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_29_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_30_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_31_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_32_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_33_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_34_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_35_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_36_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_37_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_38_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_39_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_40_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_41_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_42_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_43_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_44_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_45_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_46_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_47_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_48_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_49_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_50_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_51_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_52_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_53_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_54_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_55_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_56_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_57_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_58_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_59_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_60_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_61_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_62_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_63_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_64_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_65_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_66_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_67_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_68_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_69_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_70_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_71_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_72_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_73_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_74_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_75_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_76_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_77_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_78_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_79_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_80_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_81_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_82_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_83_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_84_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_85_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_86_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_87_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_88_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_89_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_90_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_91_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_92_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_93_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_94_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_95_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_96_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_97_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_98_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_99_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_100_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_101_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_102_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_103_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_104_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_105_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_106_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_107_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_108_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_109_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_110_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_111_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_112_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_113_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_114_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_115_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_116_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_117_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_118_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_119_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_120_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_121_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_122_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_123_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_124_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_125_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_126_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_127_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_128_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_129_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_130_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_131_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_132_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_133_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_134_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_135_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_136_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_137_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_138_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_139_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_140_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_141_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_142_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_143_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_144_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_145_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_146_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_147_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_148_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_149_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_150_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_151_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_152_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_153_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_154_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_155_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_156_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_157_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_158_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_159_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_160_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_161_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_162_2 = 65536; // sfix18 + parameter signed [17:0] t1_re_163_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_164_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_165_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_166_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_167_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_168_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_169_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_170_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_171_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_172_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_173_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_174_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_175_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_176_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_177_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_178_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_179_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_180_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_181_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_182_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_183_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_184_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_185_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_186_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_187_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_188_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_189_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_190_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_191_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_192_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_193_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_194_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_195_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_196_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_197_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_198_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_199_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_200_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_201_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_202_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_203_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_204_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_205_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_206_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_207_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_208_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_209_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_210_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_211_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_212_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_213_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_214_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_215_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_216_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_217_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_218_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_219_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_220_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_221_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_222_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_223_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_224_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_225_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_226_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_227_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_228_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_229_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_230_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_231_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_232_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_233_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_234_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_235_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_236_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_237_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_238_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_239_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_240_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_241_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_242_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_243_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_244_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_245_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_246_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_247_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_248_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_249_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_250_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_251_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_252_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_253_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_254_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_255_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_256_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_257_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_258_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_259_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_260_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_261_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_262_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_263_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_264_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_265_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_266_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_267_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_268_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_269_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_270_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_271_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_272_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_273_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_274_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_275_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_276_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_277_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_278_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_279_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_280_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_281_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_282_2 = 65535; // sfix18 + parameter signed [17:0] t1_re_283_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_284_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_285_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_286_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_287_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_288_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_289_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_290_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_291_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_292_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_293_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_294_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_295_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_296_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_297_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_298_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_299_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_300_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_301_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_302_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_303_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_304_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_305_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_306_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_307_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_308_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_309_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_310_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_311_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_312_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_313_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_314_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_315_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_316_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_317_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_318_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_319_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_320_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_321_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_322_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_323_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_324_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_325_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_326_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_327_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_328_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_329_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_330_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_331_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_332_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_333_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_334_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_335_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_336_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_337_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_338_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_339_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_340_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_341_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_342_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_343_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_344_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_345_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_346_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_347_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_348_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_349_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_350_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_351_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_352_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_353_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_354_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_355_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_356_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_357_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_358_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_359_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_360_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_361_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_362_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_363_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_364_2 = 65534; // sfix18 + parameter signed [17:0] t1_re_365_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_366_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_367_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_368_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_369_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_370_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_371_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_372_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_373_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_374_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_375_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_376_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_377_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_378_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_379_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_380_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_381_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_382_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_383_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_384_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_385_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_386_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_387_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_388_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_389_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_390_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_391_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_392_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_393_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_394_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_395_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_396_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_397_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_398_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_399_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_400_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_401_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_402_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_403_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_404_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_405_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_406_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_407_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_408_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_409_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_410_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_411_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_412_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_413_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_414_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_415_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_416_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_417_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_418_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_419_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_420_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_421_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_422_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_423_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_424_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_425_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_426_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_427_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_428_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_429_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_430_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_431_2 = 65533; // sfix18 + parameter signed [17:0] t1_re_432_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_433_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_434_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_435_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_436_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_437_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_438_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_439_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_440_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_441_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_442_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_443_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_444_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_445_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_446_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_447_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_448_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_449_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_450_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_451_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_452_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_453_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_454_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_455_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_456_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_457_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_458_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_459_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_460_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_461_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_462_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_463_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_464_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_465_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_466_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_467_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_468_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_469_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_470_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_471_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_472_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_473_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_474_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_475_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_476_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_477_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_478_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_479_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_480_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_481_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_482_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_483_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_484_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_485_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_486_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_487_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_488_2 = 65532; // sfix18 + parameter signed [17:0] t1_re_489_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_490_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_491_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_492_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_493_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_494_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_495_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_496_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_497_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_498_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_499_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_500_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_501_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_502_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_503_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_504_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_505_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_506_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_507_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_508_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_509_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_510_2 = 65531; // sfix18 + parameter signed [17:0] t1_re_511_2 = 65531; // sfix18 + parameter signed [17:0] t1_im_0_2 = 0; // sfix18 + parameter signed [17:0] t1_im_1_2 = 2; // sfix18 + parameter signed [17:0] t1_im_2_2 = 3; // sfix18 + parameter signed [17:0] t1_im_3_2 = 5; // sfix18 + parameter signed [17:0] t1_im_4_2 = 6; // sfix18 + parameter signed [17:0] t1_im_5_2 = 8; // sfix18 + parameter signed [17:0] t1_im_6_2 = 9; // sfix18 + parameter signed [17:0] t1_im_7_2 = 11; // sfix18 + parameter signed [17:0] t1_im_8_2 = 13; // sfix18 + parameter signed [17:0] t1_im_9_2 = 14; // sfix18 + parameter signed [17:0] t1_im_10_2 = 16; // sfix18 + parameter signed [17:0] t1_im_11_2 = 17; // sfix18 + parameter signed [17:0] t1_im_12_2 = 19; // sfix18 + parameter signed [17:0] t1_im_13_2 = 20; // sfix18 + parameter signed [17:0] t1_im_14_2 = 22; // sfix18 + parameter signed [17:0] t1_im_15_2 = 24; // sfix18 + parameter signed [17:0] t1_im_16_2 = 25; // sfix18 + parameter signed [17:0] t1_im_17_2 = 27; // sfix18 + parameter signed [17:0] t1_im_18_2 = 28; // sfix18 + parameter signed [17:0] t1_im_19_2 = 30; // sfix18 + parameter signed [17:0] t1_im_20_2 = 31; // sfix18 + parameter signed [17:0] t1_im_21_2 = 33; // sfix18 + parameter signed [17:0] t1_im_22_2 = 35; // sfix18 + parameter signed [17:0] t1_im_23_2 = 36; // sfix18 + parameter signed [17:0] t1_im_24_2 = 38; // sfix18 + parameter signed [17:0] t1_im_25_2 = 39; // sfix18 + parameter signed [17:0] t1_im_26_2 = 41; // sfix18 + parameter signed [17:0] t1_im_27_2 = 42; // sfix18 + parameter signed [17:0] t1_im_28_2 = 44; // sfix18 + parameter signed [17:0] t1_im_29_2 = 46; // sfix18 + parameter signed [17:0] t1_im_30_2 = 47; // sfix18 + parameter signed [17:0] t1_im_31_2 = 49; // sfix18 + parameter signed [17:0] t1_im_32_2 = 50; // sfix18 + parameter signed [17:0] t1_im_33_2 = 52; // sfix18 + parameter signed [17:0] t1_im_34_2 = 53; // sfix18 + parameter signed [17:0] t1_im_35_2 = 55; // sfix18 + parameter signed [17:0] t1_im_36_2 = 57; // sfix18 + parameter signed [17:0] t1_im_37_2 = 58; // sfix18 + parameter signed [17:0] t1_im_38_2 = 60; // sfix18 + parameter signed [17:0] t1_im_39_2 = 61; // sfix18 + parameter signed [17:0] t1_im_40_2 = 63; // sfix18 + parameter signed [17:0] t1_im_41_2 = 64; // sfix18 + parameter signed [17:0] t1_im_42_2 = 66; // sfix18 + parameter signed [17:0] t1_im_43_2 = 68; // sfix18 + parameter signed [17:0] t1_im_44_2 = 69; // sfix18 + parameter signed [17:0] t1_im_45_2 = 71; // sfix18 + parameter signed [17:0] t1_im_46_2 = 72; // sfix18 + parameter signed [17:0] t1_im_47_2 = 74; // sfix18 + parameter signed [17:0] t1_im_48_2 = 75; // sfix18 + parameter signed [17:0] t1_im_49_2 = 77; // sfix18 + parameter signed [17:0] t1_im_50_2 = 79; // sfix18 + parameter signed [17:0] t1_im_51_2 = 80; // sfix18 + parameter signed [17:0] t1_im_52_2 = 82; // sfix18 + parameter signed [17:0] t1_im_53_2 = 83; // sfix18 + parameter signed [17:0] t1_im_54_2 = 85; // sfix18 + parameter signed [17:0] t1_im_55_2 = 86; // sfix18 + parameter signed [17:0] t1_im_56_2 = 88; // sfix18 + parameter signed [17:0] t1_im_57_2 = 90; // sfix18 + parameter signed [17:0] t1_im_58_2 = 91; // sfix18 + parameter signed [17:0] t1_im_59_2 = 93; // sfix18 + parameter signed [17:0] t1_im_60_2 = 94; // sfix18 + parameter signed [17:0] t1_im_61_2 = 96; // sfix18 + parameter signed [17:0] t1_im_62_2 = 97; // sfix18 + parameter signed [17:0] t1_im_63_2 = 99; // sfix18 + parameter signed [17:0] t1_im_64_2 = 101; // sfix18 + parameter signed [17:0] t1_im_65_2 = 102; // sfix18 + parameter signed [17:0] t1_im_66_2 = 104; // sfix18 + parameter signed [17:0] t1_im_67_2 = 105; // sfix18 + parameter signed [17:0] t1_im_68_2 = 107; // sfix18 + parameter signed [17:0] t1_im_69_2 = 108; // sfix18 + parameter signed [17:0] t1_im_70_2 = 110; // sfix18 + parameter signed [17:0] t1_im_71_2 = 112; // sfix18 + parameter signed [17:0] t1_im_72_2 = 113; // sfix18 + parameter signed [17:0] t1_im_73_2 = 115; // sfix18 + parameter signed [17:0] t1_im_74_2 = 116; // sfix18 + parameter signed [17:0] t1_im_75_2 = 118; // sfix18 + parameter signed [17:0] t1_im_76_2 = 119; // sfix18 + parameter signed [17:0] t1_im_77_2 = 121; // sfix18 + parameter signed [17:0] t1_im_78_2 = 123; // sfix18 + parameter signed [17:0] t1_im_79_2 = 124; // sfix18 + parameter signed [17:0] t1_im_80_2 = 126; // sfix18 + parameter signed [17:0] t1_im_81_2 = 127; // sfix18 + parameter signed [17:0] t1_im_82_2 = 129; // sfix18 + parameter signed [17:0] t1_im_83_2 = 130; // sfix18 + parameter signed [17:0] t1_im_84_2 = 132; // sfix18 + parameter signed [17:0] t1_im_85_2 = 134; // sfix18 + parameter signed [17:0] t1_im_86_2 = 135; // sfix18 + parameter signed [17:0] t1_im_87_2 = 137; // sfix18 + parameter signed [17:0] t1_im_88_2 = 138; // sfix18 + parameter signed [17:0] t1_im_89_2 = 140; // sfix18 + parameter signed [17:0] t1_im_90_2 = 141; // sfix18 + parameter signed [17:0] t1_im_91_2 = 143; // sfix18 + parameter signed [17:0] t1_im_92_2 = 145; // sfix18 + parameter signed [17:0] t1_im_93_2 = 146; // sfix18 + parameter signed [17:0] t1_im_94_2 = 148; // sfix18 + parameter signed [17:0] t1_im_95_2 = 149; // sfix18 + parameter signed [17:0] t1_im_96_2 = 151; // sfix18 + parameter signed [17:0] t1_im_97_2 = 152; // sfix18 + parameter signed [17:0] t1_im_98_2 = 154; // sfix18 + parameter signed [17:0] t1_im_99_2 = 156; // sfix18 + parameter signed [17:0] t1_im_100_2 = 157; // sfix18 + parameter signed [17:0] t1_im_101_2 = 159; // sfix18 + parameter signed [17:0] t1_im_102_2 = 160; // sfix18 + parameter signed [17:0] t1_im_103_2 = 162; // sfix18 + parameter signed [17:0] t1_im_104_2 = 163; // sfix18 + parameter signed [17:0] t1_im_105_2 = 165; // sfix18 + parameter signed [17:0] t1_im_106_2 = 167; // sfix18 + parameter signed [17:0] t1_im_107_2 = 168; // sfix18 + parameter signed [17:0] t1_im_108_2 = 170; // sfix18 + parameter signed [17:0] t1_im_109_2 = 171; // sfix18 + parameter signed [17:0] t1_im_110_2 = 173; // sfix18 + parameter signed [17:0] t1_im_111_2 = 174; // sfix18 + parameter signed [17:0] t1_im_112_2 = 176; // sfix18 + parameter signed [17:0] t1_im_113_2 = 177; // sfix18 + parameter signed [17:0] t1_im_114_2 = 179; // sfix18 + parameter signed [17:0] t1_im_115_2 = 181; // sfix18 + parameter signed [17:0] t1_im_116_2 = 182; // sfix18 + parameter signed [17:0] t1_im_117_2 = 184; // sfix18 + parameter signed [17:0] t1_im_118_2 = 185; // sfix18 + parameter signed [17:0] t1_im_119_2 = 187; // sfix18 + parameter signed [17:0] t1_im_120_2 = 188; // sfix18 + parameter signed [17:0] t1_im_121_2 = 190; // sfix18 + parameter signed [17:0] t1_im_122_2 = 192; // sfix18 + parameter signed [17:0] t1_im_123_2 = 193; // sfix18 + parameter signed [17:0] t1_im_124_2 = 195; // sfix18 + parameter signed [17:0] t1_im_125_2 = 196; // sfix18 + parameter signed [17:0] t1_im_126_2 = 198; // sfix18 + parameter signed [17:0] t1_im_127_2 = 199; // sfix18 + parameter signed [17:0] t1_im_128_2 = 201; // sfix18 + parameter signed [17:0] t1_im_129_2 = 203; // sfix18 + parameter signed [17:0] t1_im_130_2 = 204; // sfix18 + parameter signed [17:0] t1_im_131_2 = 206; // sfix18 + parameter signed [17:0] t1_im_132_2 = 207; // sfix18 + parameter signed [17:0] t1_im_133_2 = 209; // sfix18 + parameter signed [17:0] t1_im_134_2 = 210; // sfix18 + parameter signed [17:0] t1_im_135_2 = 212; // sfix18 + parameter signed [17:0] t1_im_136_2 = 214; // sfix18 + parameter signed [17:0] t1_im_137_2 = 215; // sfix18 + parameter signed [17:0] t1_im_138_2 = 217; // sfix18 + parameter signed [17:0] t1_im_139_2 = 218; // sfix18 + parameter signed [17:0] t1_im_140_2 = 220; // sfix18 + parameter signed [17:0] t1_im_141_2 = 221; // sfix18 + parameter signed [17:0] t1_im_142_2 = 223; // sfix18 + parameter signed [17:0] t1_im_143_2 = 225; // sfix18 + parameter signed [17:0] t1_im_144_2 = 226; // sfix18 + parameter signed [17:0] t1_im_145_2 = 228; // sfix18 + parameter signed [17:0] t1_im_146_2 = 229; // sfix18 + parameter signed [17:0] t1_im_147_2 = 231; // sfix18 + parameter signed [17:0] t1_im_148_2 = 232; // sfix18 + parameter signed [17:0] t1_im_149_2 = 234; // sfix18 + parameter signed [17:0] t1_im_150_2 = 236; // sfix18 + parameter signed [17:0] t1_im_151_2 = 237; // sfix18 + parameter signed [17:0] t1_im_152_2 = 239; // sfix18 + parameter signed [17:0] t1_im_153_2 = 240; // sfix18 + parameter signed [17:0] t1_im_154_2 = 242; // sfix18 + parameter signed [17:0] t1_im_155_2 = 243; // sfix18 + parameter signed [17:0] t1_im_156_2 = 245; // sfix18 + parameter signed [17:0] t1_im_157_2 = 247; // sfix18 + parameter signed [17:0] t1_im_158_2 = 248; // sfix18 + parameter signed [17:0] t1_im_159_2 = 250; // sfix18 + parameter signed [17:0] t1_im_160_2 = 251; // sfix18 + parameter signed [17:0] t1_im_161_2 = 253; // sfix18 + parameter signed [17:0] t1_im_162_2 = 254; // sfix18 + parameter signed [17:0] t1_im_163_2 = 256; // sfix18 + parameter signed [17:0] t1_im_164_2 = 258; // sfix18 + parameter signed [17:0] t1_im_165_2 = 259; // sfix18 + parameter signed [17:0] t1_im_166_2 = 261; // sfix18 + parameter signed [17:0] t1_im_167_2 = 262; // sfix18 + parameter signed [17:0] t1_im_168_2 = 264; // sfix18 + parameter signed [17:0] t1_im_169_2 = 265; // sfix18 + parameter signed [17:0] t1_im_170_2 = 267; // sfix18 + parameter signed [17:0] t1_im_171_2 = 269; // sfix18 + parameter signed [17:0] t1_im_172_2 = 270; // sfix18 + parameter signed [17:0] t1_im_173_2 = 272; // sfix18 + parameter signed [17:0] t1_im_174_2 = 273; // sfix18 + parameter signed [17:0] t1_im_175_2 = 275; // sfix18 + parameter signed [17:0] t1_im_176_2 = 276; // sfix18 + parameter signed [17:0] t1_im_177_2 = 278; // sfix18 + parameter signed [17:0] t1_im_178_2 = 280; // sfix18 + parameter signed [17:0] t1_im_179_2 = 281; // sfix18 + parameter signed [17:0] t1_im_180_2 = 283; // sfix18 + parameter signed [17:0] t1_im_181_2 = 284; // sfix18 + parameter signed [17:0] t1_im_182_2 = 286; // sfix18 + parameter signed [17:0] t1_im_183_2 = 287; // sfix18 + parameter signed [17:0] t1_im_184_2 = 289; // sfix18 + parameter signed [17:0] t1_im_185_2 = 291; // sfix18 + parameter signed [17:0] t1_im_186_2 = 292; // sfix18 + parameter signed [17:0] t1_im_187_2 = 294; // sfix18 + parameter signed [17:0] t1_im_188_2 = 295; // sfix18 + parameter signed [17:0] t1_im_189_2 = 297; // sfix18 + parameter signed [17:0] t1_im_190_2 = 298; // sfix18 + parameter signed [17:0] t1_im_191_2 = 300; // sfix18 + parameter signed [17:0] t1_im_192_2 = 302; // sfix18 + parameter signed [17:0] t1_im_193_2 = 303; // sfix18 + parameter signed [17:0] t1_im_194_2 = 305; // sfix18 + parameter signed [17:0] t1_im_195_2 = 306; // sfix18 + parameter signed [17:0] t1_im_196_2 = 308; // sfix18 + parameter signed [17:0] t1_im_197_2 = 309; // sfix18 + parameter signed [17:0] t1_im_198_2 = 311; // sfix18 + parameter signed [17:0] t1_im_199_2 = 313; // sfix18 + parameter signed [17:0] t1_im_200_2 = 314; // sfix18 + parameter signed [17:0] t1_im_201_2 = 316; // sfix18 + parameter signed [17:0] t1_im_202_2 = 317; // sfix18 + parameter signed [17:0] t1_im_203_2 = 319; // sfix18 + parameter signed [17:0] t1_im_204_2 = 320; // sfix18 + parameter signed [17:0] t1_im_205_2 = 322; // sfix18 + parameter signed [17:0] t1_im_206_2 = 324; // sfix18 + parameter signed [17:0] t1_im_207_2 = 325; // sfix18 + parameter signed [17:0] t1_im_208_2 = 327; // sfix18 + parameter signed [17:0] t1_im_209_2 = 328; // sfix18 + parameter signed [17:0] t1_im_210_2 = 330; // sfix18 + parameter signed [17:0] t1_im_211_2 = 331; // sfix18 + parameter signed [17:0] t1_im_212_2 = 333; // sfix18 + parameter signed [17:0] t1_im_213_2 = 335; // sfix18 + parameter signed [17:0] t1_im_214_2 = 336; // sfix18 + parameter signed [17:0] t1_im_215_2 = 338; // sfix18 + parameter signed [17:0] t1_im_216_2 = 339; // sfix18 + parameter signed [17:0] t1_im_217_2 = 341; // sfix18 + parameter signed [17:0] t1_im_218_2 = 342; // sfix18 + parameter signed [17:0] t1_im_219_2 = 344; // sfix18 + parameter signed [17:0] t1_im_220_2 = 346; // sfix18 + parameter signed [17:0] t1_im_221_2 = 347; // sfix18 + parameter signed [17:0] t1_im_222_2 = 349; // sfix18 + parameter signed [17:0] t1_im_223_2 = 350; // sfix18 + parameter signed [17:0] t1_im_224_2 = 352; // sfix18 + parameter signed [17:0] t1_im_225_2 = 353; // sfix18 + parameter signed [17:0] t1_im_226_2 = 355; // sfix18 + parameter signed [17:0] t1_im_227_2 = 357; // sfix18 + parameter signed [17:0] t1_im_228_2 = 358; // sfix18 + parameter signed [17:0] t1_im_229_2 = 360; // sfix18 + parameter signed [17:0] t1_im_230_2 = 361; // sfix18 + parameter signed [17:0] t1_im_231_2 = 363; // sfix18 + parameter signed [17:0] t1_im_232_2 = 364; // sfix18 + parameter signed [17:0] t1_im_233_2 = 366; // sfix18 + parameter signed [17:0] t1_im_234_2 = 368; // sfix18 + parameter signed [17:0] t1_im_235_2 = 369; // sfix18 + parameter signed [17:0] t1_im_236_2 = 371; // sfix18 + parameter signed [17:0] t1_im_237_2 = 372; // sfix18 + parameter signed [17:0] t1_im_238_2 = 374; // sfix18 + parameter signed [17:0] t1_im_239_2 = 375; // sfix18 + parameter signed [17:0] t1_im_240_2 = 377; // sfix18 + parameter signed [17:0] t1_im_241_2 = 379; // sfix18 + parameter signed [17:0] t1_im_242_2 = 380; // sfix18 + parameter signed [17:0] t1_im_243_2 = 382; // sfix18 + parameter signed [17:0] t1_im_244_2 = 383; // sfix18 + parameter signed [17:0] t1_im_245_2 = 385; // sfix18 + parameter signed [17:0] t1_im_246_2 = 386; // sfix18 + parameter signed [17:0] t1_im_247_2 = 388; // sfix18 + parameter signed [17:0] t1_im_248_2 = 390; // sfix18 + parameter signed [17:0] t1_im_249_2 = 391; // sfix18 + parameter signed [17:0] t1_im_250_2 = 393; // sfix18 + parameter signed [17:0] t1_im_251_2 = 394; // sfix18 + parameter signed [17:0] t1_im_252_2 = 396; // sfix18 + parameter signed [17:0] t1_im_253_2 = 397; // sfix18 + parameter signed [17:0] t1_im_254_2 = 399; // sfix18 + parameter signed [17:0] t1_im_255_2 = 401; // sfix18 + parameter signed [17:0] t1_im_256_2 = 402; // sfix18 + parameter signed [17:0] t1_im_257_2 = 404; // sfix18 + parameter signed [17:0] t1_im_258_2 = 405; // sfix18 + parameter signed [17:0] t1_im_259_2 = 407; // sfix18 + parameter signed [17:0] t1_im_260_2 = 408; // sfix18 + parameter signed [17:0] t1_im_261_2 = 410; // sfix18 + parameter signed [17:0] t1_im_262_2 = 412; // sfix18 + parameter signed [17:0] t1_im_263_2 = 413; // sfix18 + parameter signed [17:0] t1_im_264_2 = 415; // sfix18 + parameter signed [17:0] t1_im_265_2 = 416; // sfix18 + parameter signed [17:0] t1_im_266_2 = 418; // sfix18 + parameter signed [17:0] t1_im_267_2 = 419; // sfix18 + parameter signed [17:0] t1_im_268_2 = 421; // sfix18 + parameter signed [17:0] t1_im_269_2 = 423; // sfix18 + parameter signed [17:0] t1_im_270_2 = 424; // sfix18 + parameter signed [17:0] t1_im_271_2 = 426; // sfix18 + parameter signed [17:0] t1_im_272_2 = 427; // sfix18 + parameter signed [17:0] t1_im_273_2 = 429; // sfix18 + parameter signed [17:0] t1_im_274_2 = 430; // sfix18 + parameter signed [17:0] t1_im_275_2 = 432; // sfix18 + parameter signed [17:0] t1_im_276_2 = 434; // sfix18 + parameter signed [17:0] t1_im_277_2 = 435; // sfix18 + parameter signed [17:0] t1_im_278_2 = 437; // sfix18 + parameter signed [17:0] t1_im_279_2 = 438; // sfix18 + parameter signed [17:0] t1_im_280_2 = 440; // sfix18 + parameter signed [17:0] t1_im_281_2 = 441; // sfix18 + parameter signed [17:0] t1_im_282_2 = 443; // sfix18 + parameter signed [17:0] t1_im_283_2 = 445; // sfix18 + parameter signed [17:0] t1_im_284_2 = 446; // sfix18 + parameter signed [17:0] t1_im_285_2 = 448; // sfix18 + parameter signed [17:0] t1_im_286_2 = 449; // sfix18 + parameter signed [17:0] t1_im_287_2 = 451; // sfix18 + parameter signed [17:0] t1_im_288_2 = 452; // sfix18 + parameter signed [17:0] t1_im_289_2 = 454; // sfix18 + parameter signed [17:0] t1_im_290_2 = 456; // sfix18 + parameter signed [17:0] t1_im_291_2 = 457; // sfix18 + parameter signed [17:0] t1_im_292_2 = 459; // sfix18 + parameter signed [17:0] t1_im_293_2 = 460; // sfix18 + parameter signed [17:0] t1_im_294_2 = 462; // sfix18 + parameter signed [17:0] t1_im_295_2 = 463; // sfix18 + parameter signed [17:0] t1_im_296_2 = 465; // sfix18 + parameter signed [17:0] t1_im_297_2 = 467; // sfix18 + parameter signed [17:0] t1_im_298_2 = 468; // sfix18 + parameter signed [17:0] t1_im_299_2 = 470; // sfix18 + parameter signed [17:0] t1_im_300_2 = 471; // sfix18 + parameter signed [17:0] t1_im_301_2 = 473; // sfix18 + parameter signed [17:0] t1_im_302_2 = 474; // sfix18 + parameter signed [17:0] t1_im_303_2 = 476; // sfix18 + parameter signed [17:0] t1_im_304_2 = 478; // sfix18 + parameter signed [17:0] t1_im_305_2 = 479; // sfix18 + parameter signed [17:0] t1_im_306_2 = 481; // sfix18 + parameter signed [17:0] t1_im_307_2 = 482; // sfix18 + parameter signed [17:0] t1_im_308_2 = 484; // sfix18 + parameter signed [17:0] t1_im_309_2 = 485; // sfix18 + parameter signed [17:0] t1_im_310_2 = 487; // sfix18 + parameter signed [17:0] t1_im_311_2 = 489; // sfix18 + parameter signed [17:0] t1_im_312_2 = 490; // sfix18 + parameter signed [17:0] t1_im_313_2 = 492; // sfix18 + parameter signed [17:0] t1_im_314_2 = 493; // sfix18 + parameter signed [17:0] t1_im_315_2 = 495; // sfix18 + parameter signed [17:0] t1_im_316_2 = 496; // sfix18 + parameter signed [17:0] t1_im_317_2 = 498; // sfix18 + parameter signed [17:0] t1_im_318_2 = 500; // sfix18 + parameter signed [17:0] t1_im_319_2 = 501; // sfix18 + parameter signed [17:0] t1_im_320_2 = 503; // sfix18 + parameter signed [17:0] t1_im_321_2 = 504; // sfix18 + parameter signed [17:0] t1_im_322_2 = 506; // sfix18 + parameter signed [17:0] t1_im_323_2 = 507; // sfix18 + parameter signed [17:0] t1_im_324_2 = 509; // sfix18 + parameter signed [17:0] t1_im_325_2 = 511; // sfix18 + parameter signed [17:0] t1_im_326_2 = 512; // sfix18 + parameter signed [17:0] t1_im_327_2 = 514; // sfix18 + parameter signed [17:0] t1_im_328_2 = 515; // sfix18 + parameter signed [17:0] t1_im_329_2 = 517; // sfix18 + parameter signed [17:0] t1_im_330_2 = 518; // sfix18 + parameter signed [17:0] t1_im_331_2 = 520; // sfix18 + parameter signed [17:0] t1_im_332_2 = 521; // sfix18 + parameter signed [17:0] t1_im_333_2 = 523; // sfix18 + parameter signed [17:0] t1_im_334_2 = 525; // sfix18 + parameter signed [17:0] t1_im_335_2 = 526; // sfix18 + parameter signed [17:0] t1_im_336_2 = 528; // sfix18 + parameter signed [17:0] t1_im_337_2 = 529; // sfix18 + parameter signed [17:0] t1_im_338_2 = 531; // sfix18 + parameter signed [17:0] t1_im_339_2 = 532; // sfix18 + parameter signed [17:0] t1_im_340_2 = 534; // sfix18 + parameter signed [17:0] t1_im_341_2 = 536; // sfix18 + parameter signed [17:0] t1_im_342_2 = 537; // sfix18 + parameter signed [17:0] t1_im_343_2 = 539; // sfix18 + parameter signed [17:0] t1_im_344_2 = 540; // sfix18 + parameter signed [17:0] t1_im_345_2 = 542; // sfix18 + parameter signed [17:0] t1_im_346_2 = 543; // sfix18 + parameter signed [17:0] t1_im_347_2 = 545; // sfix18 + parameter signed [17:0] t1_im_348_2 = 547; // sfix18 + parameter signed [17:0] t1_im_349_2 = 548; // sfix18 + parameter signed [17:0] t1_im_350_2 = 550; // sfix18 + parameter signed [17:0] t1_im_351_2 = 551; // sfix18 + parameter signed [17:0] t1_im_352_2 = 553; // sfix18 + parameter signed [17:0] t1_im_353_2 = 554; // sfix18 + parameter signed [17:0] t1_im_354_2 = 556; // sfix18 + parameter signed [17:0] t1_im_355_2 = 558; // sfix18 + parameter signed [17:0] t1_im_356_2 = 559; // sfix18 + parameter signed [17:0] t1_im_357_2 = 561; // sfix18 + parameter signed [17:0] t1_im_358_2 = 562; // sfix18 + parameter signed [17:0] t1_im_359_2 = 564; // sfix18 + parameter signed [17:0] t1_im_360_2 = 565; // sfix18 + parameter signed [17:0] t1_im_361_2 = 567; // sfix18 + parameter signed [17:0] t1_im_362_2 = 569; // sfix18 + parameter signed [17:0] t1_im_363_2 = 570; // sfix18 + parameter signed [17:0] t1_im_364_2 = 572; // sfix18 + parameter signed [17:0] t1_im_365_2 = 573; // sfix18 + parameter signed [17:0] t1_im_366_2 = 575; // sfix18 + parameter signed [17:0] t1_im_367_2 = 576; // sfix18 + parameter signed [17:0] t1_im_368_2 = 578; // sfix18 + parameter signed [17:0] t1_im_369_2 = 580; // sfix18 + parameter signed [17:0] t1_im_370_2 = 581; // sfix18 + parameter signed [17:0] t1_im_371_2 = 583; // sfix18 + parameter signed [17:0] t1_im_372_2 = 584; // sfix18 + parameter signed [17:0] t1_im_373_2 = 586; // sfix18 + parameter signed [17:0] t1_im_374_2 = 587; // sfix18 + parameter signed [17:0] t1_im_375_2 = 589; // sfix18 + parameter signed [17:0] t1_im_376_2 = 591; // sfix18 + parameter signed [17:0] t1_im_377_2 = 592; // sfix18 + parameter signed [17:0] t1_im_378_2 = 594; // sfix18 + parameter signed [17:0] t1_im_379_2 = 595; // sfix18 + parameter signed [17:0] t1_im_380_2 = 597; // sfix18 + parameter signed [17:0] t1_im_381_2 = 598; // sfix18 + parameter signed [17:0] t1_im_382_2 = 600; // sfix18 + parameter signed [17:0] t1_im_383_2 = 602; // sfix18 + parameter signed [17:0] t1_im_384_2 = 603; // sfix18 + parameter signed [17:0] t1_im_385_2 = 605; // sfix18 + parameter signed [17:0] t1_im_386_2 = 606; // sfix18 + parameter signed [17:0] t1_im_387_2 = 608; // sfix18 + parameter signed [17:0] t1_im_388_2 = 609; // sfix18 + parameter signed [17:0] t1_im_389_2 = 611; // sfix18 + parameter signed [17:0] t1_im_390_2 = 613; // sfix18 + parameter signed [17:0] t1_im_391_2 = 614; // sfix18 + parameter signed [17:0] t1_im_392_2 = 616; // sfix18 + parameter signed [17:0] t1_im_393_2 = 617; // sfix18 + parameter signed [17:0] t1_im_394_2 = 619; // sfix18 + parameter signed [17:0] t1_im_395_2 = 620; // sfix18 + parameter signed [17:0] t1_im_396_2 = 622; // sfix18 + parameter signed [17:0] t1_im_397_2 = 624; // sfix18 + parameter signed [17:0] t1_im_398_2 = 625; // sfix18 + parameter signed [17:0] t1_im_399_2 = 627; // sfix18 + parameter signed [17:0] t1_im_400_2 = 628; // sfix18 + parameter signed [17:0] t1_im_401_2 = 630; // sfix18 + parameter signed [17:0] t1_im_402_2 = 631; // sfix18 + parameter signed [17:0] t1_im_403_2 = 633; // sfix18 + parameter signed [17:0] t1_im_404_2 = 635; // sfix18 + parameter signed [17:0] t1_im_405_2 = 636; // sfix18 + parameter signed [17:0] t1_im_406_2 = 638; // sfix18 + parameter signed [17:0] t1_im_407_2 = 639; // sfix18 + parameter signed [17:0] t1_im_408_2 = 641; // sfix18 + parameter signed [17:0] t1_im_409_2 = 642; // sfix18 + parameter signed [17:0] t1_im_410_2 = 644; // sfix18 + parameter signed [17:0] t1_im_411_2 = 646; // sfix18 + parameter signed [17:0] t1_im_412_2 = 647; // sfix18 + parameter signed [17:0] t1_im_413_2 = 649; // sfix18 + parameter signed [17:0] t1_im_414_2 = 650; // sfix18 + parameter signed [17:0] t1_im_415_2 = 652; // sfix18 + parameter signed [17:0] t1_im_416_2 = 653; // sfix18 + parameter signed [17:0] t1_im_417_2 = 655; // sfix18 + parameter signed [17:0] t1_im_418_2 = 657; // sfix18 + parameter signed [17:0] t1_im_419_2 = 658; // sfix18 + parameter signed [17:0] t1_im_420_2 = 660; // sfix18 + parameter signed [17:0] t1_im_421_2 = 661; // sfix18 + parameter signed [17:0] t1_im_422_2 = 663; // sfix18 + parameter signed [17:0] t1_im_423_2 = 664; // sfix18 + parameter signed [17:0] t1_im_424_2 = 666; // sfix18 + parameter signed [17:0] t1_im_425_2 = 668; // sfix18 + parameter signed [17:0] t1_im_426_2 = 669; // sfix18 + parameter signed [17:0] t1_im_427_2 = 671; // sfix18 + parameter signed [17:0] t1_im_428_2 = 672; // sfix18 + parameter signed [17:0] t1_im_429_2 = 674; // sfix18 + parameter signed [17:0] t1_im_430_2 = 675; // sfix18 + parameter signed [17:0] t1_im_431_2 = 677; // sfix18 + parameter signed [17:0] t1_im_432_2 = 679; // sfix18 + parameter signed [17:0] t1_im_433_2 = 680; // sfix18 + parameter signed [17:0] t1_im_434_2 = 682; // sfix18 + parameter signed [17:0] t1_im_435_2 = 683; // sfix18 + parameter signed [17:0] t1_im_436_2 = 685; // sfix18 + parameter signed [17:0] t1_im_437_2 = 686; // sfix18 + parameter signed [17:0] t1_im_438_2 = 688; // sfix18 + parameter signed [17:0] t1_im_439_2 = 690; // sfix18 + parameter signed [17:0] t1_im_440_2 = 691; // sfix18 + parameter signed [17:0] t1_im_441_2 = 693; // sfix18 + parameter signed [17:0] t1_im_442_2 = 694; // sfix18 + parameter signed [17:0] t1_im_443_2 = 696; // sfix18 + parameter signed [17:0] t1_im_444_2 = 697; // sfix18 + parameter signed [17:0] t1_im_445_2 = 699; // sfix18 + parameter signed [17:0] t1_im_446_2 = 701; // sfix18 + parameter signed [17:0] t1_im_447_2 = 702; // sfix18 + parameter signed [17:0] t1_im_448_2 = 704; // sfix18 + parameter signed [17:0] t1_im_449_2 = 705; // sfix18 + parameter signed [17:0] t1_im_450_2 = 707; // sfix18 + parameter signed [17:0] t1_im_451_2 = 708; // sfix18 + parameter signed [17:0] t1_im_452_2 = 710; // sfix18 + parameter signed [17:0] t1_im_453_2 = 712; // sfix18 + parameter signed [17:0] t1_im_454_2 = 713; // sfix18 + parameter signed [17:0] t1_im_455_2 = 715; // sfix18 + parameter signed [17:0] t1_im_456_2 = 716; // sfix18 + parameter signed [17:0] t1_im_457_2 = 718; // sfix18 + parameter signed [17:0] t1_im_458_2 = 719; // sfix18 + parameter signed [17:0] t1_im_459_2 = 721; // sfix18 + parameter signed [17:0] t1_im_460_2 = 723; // sfix18 + parameter signed [17:0] t1_im_461_2 = 724; // sfix18 + parameter signed [17:0] t1_im_462_2 = 726; // sfix18 + parameter signed [17:0] t1_im_463_2 = 727; // sfix18 + parameter signed [17:0] t1_im_464_2 = 729; // sfix18 + parameter signed [17:0] t1_im_465_2 = 730; // sfix18 + parameter signed [17:0] t1_im_466_2 = 732; // sfix18 + parameter signed [17:0] t1_im_467_2 = 734; // sfix18 + parameter signed [17:0] t1_im_468_2 = 735; // sfix18 + parameter signed [17:0] t1_im_469_2 = 737; // sfix18 + parameter signed [17:0] t1_im_470_2 = 738; // sfix18 + parameter signed [17:0] t1_im_471_2 = 740; // sfix18 + parameter signed [17:0] t1_im_472_2 = 741; // sfix18 + parameter signed [17:0] t1_im_473_2 = 743; // sfix18 + parameter signed [17:0] t1_im_474_2 = 745; // sfix18 + parameter signed [17:0] t1_im_475_2 = 746; // sfix18 + parameter signed [17:0] t1_im_476_2 = 748; // sfix18 + parameter signed [17:0] t1_im_477_2 = 749; // sfix18 + parameter signed [17:0] t1_im_478_2 = 751; // sfix18 + parameter signed [17:0] t1_im_479_2 = 752; // sfix18 + parameter signed [17:0] t1_im_480_2 = 754; // sfix18 + parameter signed [17:0] t1_im_481_2 = 756; // sfix18 + parameter signed [17:0] t1_im_482_2 = 757; // sfix18 + parameter signed [17:0] t1_im_483_2 = 759; // sfix18 + parameter signed [17:0] t1_im_484_2 = 760; // sfix18 + parameter signed [17:0] t1_im_485_2 = 762; // sfix18 + parameter signed [17:0] t1_im_486_2 = 763; // sfix18 + parameter signed [17:0] t1_im_487_2 = 765; // sfix18 + parameter signed [17:0] t1_im_488_2 = 767; // sfix18 + parameter signed [17:0] t1_im_489_2 = 768; // sfix18 + parameter signed [17:0] t1_im_490_2 = 770; // sfix18 + parameter signed [17:0] t1_im_491_2 = 771; // sfix18 + parameter signed [17:0] t1_im_492_2 = 773; // sfix18 + parameter signed [17:0] t1_im_493_2 = 774; // sfix18 + parameter signed [17:0] t1_im_494_2 = 776; // sfix18 + parameter signed [17:0] t1_im_495_2 = 778; // sfix18 + parameter signed [17:0] t1_im_496_2 = 779; // sfix18 + parameter signed [17:0] t1_im_497_2 = 781; // sfix18 + parameter signed [17:0] t1_im_498_2 = 782; // sfix18 + parameter signed [17:0] t1_im_499_2 = 784; // sfix18 + parameter signed [17:0] t1_im_500_2 = 785; // sfix18 + parameter signed [17:0] t1_im_501_2 = 787; // sfix18 + parameter signed [17:0] t1_im_502_2 = 789; // sfix18 + parameter signed [17:0] t1_im_503_2 = 790; // sfix18 + parameter signed [17:0] t1_im_504_2 = 792; // sfix18 + parameter signed [17:0] t1_im_505_2 = 793; // sfix18 + parameter signed [17:0] t1_im_506_2 = 795; // sfix18 + parameter signed [17:0] t1_im_507_2 = 796; // sfix18 + parameter signed [17:0] t1_im_508_2 = 798; // sfix18 + parameter signed [17:0] t1_im_509_2 = 800; // sfix18 + parameter signed [17:0] t1_im_510_2 = 801; // sfix18 + parameter signed [17:0] t1_im_511_2 = 803; // sfix18 + + wire signed [17:0] Convert_Data_Type_out1; // sfix18_En14 + wire signed [35:0] Normalize_Gain_mul_temp; // sfix36_En33 + wire [17:0] Normalize_Gain_out1; // ufix18_En18 + wire [17:0] elec_pos_scaled; // ufix18 + wire [8:0] y; // ufix9 + wire [15:0] Data_Type_Conversion1_out1; // uint16 + wire signed [17:0] Direct_Lookup_Table_n_D_t1_re [0:511]; // sfix18_En16 [512] + wire signed [17:0] Direct_Lookup_Table_n_D_t1_im [0:511]; // sfix18_En16 [512] + wire signed [17:0] Direct_Lookup_Table_n_D_out1_re; // sfix18_En16 + wire signed [17:0] Direct_Lookup_Table_n_D_out1_im; // sfix18_En16 + wire [8:0] y_1; // ufix9 + wire [15:0] Data_Type_Conversion2_out1; // uint16 + wire signed [17:0] Direct_Lookup_Table_n_D_1_t1_re [0:511]; // sfix18_En16 [512] + wire signed [17:0] Direct_Lookup_Table_n_D_1_t1_im [0:511]; // sfix18_En16 [512] + wire signed [17:0] Direct_Lookup_Table_n_D_1_out1_re; // sfix18_En16 + wire signed [17:0] Direct_Lookup_Table_n_D_1_out1_im; // sfix18_En16 + wire signed [35:0] cos_coefficient; // sfix36_En32 + wire signed [35:0] sin_coefficient; // sfix36_En32 + wire signed [17:0] sin_coefficient_1; // sfix18_En16 + wire signed [17:0] cos_coefficient_1; // sfix18_En16 + + + // /Convert_Data_Type + velocityControlHdl_Convert_Data_Type_block u_Convert_Data_Type (.In1(x), // sfix18_En14 + .Out1(Convert_Data_Type_out1) // sfix18_En14 + ); + + // /Normalize Gain + assign Normalize_Gain_mul_temp = 83443 * Convert_Data_Type_out1; + assign Normalize_Gain_out1 = ((Normalize_Gain_mul_temp[35] == 1'b0) && (Normalize_Gain_mul_temp[34:33] != 2'b00) ? 18'b111111111111111111 : + (Normalize_Gain_mul_temp[35] == 1'b1 ? 18'b000000000000000000 : + Normalize_Gain_mul_temp[32:15])); + + + + // /Remove Scaling + assign elec_pos_scaled = Normalize_Gain_out1; + + + + // /Mark_Extract_Bits + velocityControlHdl_Mark_Extract_Bits u_Mark_Extract_Bits (.In1(elec_pos_scaled), // ufix18 + .Out1(y) // ufix9 + ); + + // /Data Type Conversion1 + assign Data_Type_Conversion1_out1 = y; + + + + // /Direct Lookup Table (n-D) + assign Direct_Lookup_Table_n_D_t1_re[0] = t1_re_0; + assign Direct_Lookup_Table_n_D_t1_re[1] = t1_re_1; + assign Direct_Lookup_Table_n_D_t1_re[2] = t1_re_2; + assign Direct_Lookup_Table_n_D_t1_re[3] = t1_re_3; + assign Direct_Lookup_Table_n_D_t1_re[4] = t1_re_4; + assign Direct_Lookup_Table_n_D_t1_re[5] = t1_re_5; + assign Direct_Lookup_Table_n_D_t1_re[6] = t1_re_6; + assign Direct_Lookup_Table_n_D_t1_re[7] = t1_re_7; + assign Direct_Lookup_Table_n_D_t1_re[8] = t1_re_8; + assign Direct_Lookup_Table_n_D_t1_re[9] = t1_re_9; + assign Direct_Lookup_Table_n_D_t1_re[10] = t1_re_10; + assign Direct_Lookup_Table_n_D_t1_re[11] = t1_re_11; + assign Direct_Lookup_Table_n_D_t1_re[12] = t1_re_12; + assign Direct_Lookup_Table_n_D_t1_re[13] = t1_re_13; + assign Direct_Lookup_Table_n_D_t1_re[14] = t1_re_14; + assign Direct_Lookup_Table_n_D_t1_re[15] = t1_re_15; + assign Direct_Lookup_Table_n_D_t1_re[16] = t1_re_16; + assign Direct_Lookup_Table_n_D_t1_re[17] = t1_re_17; + assign Direct_Lookup_Table_n_D_t1_re[18] = t1_re_18; + assign Direct_Lookup_Table_n_D_t1_re[19] = t1_re_19; + assign Direct_Lookup_Table_n_D_t1_re[20] = t1_re_20; + assign Direct_Lookup_Table_n_D_t1_re[21] = t1_re_21; + assign Direct_Lookup_Table_n_D_t1_re[22] = t1_re_22; + assign Direct_Lookup_Table_n_D_t1_re[23] = t1_re_23; + assign Direct_Lookup_Table_n_D_t1_re[24] = t1_re_24; + assign Direct_Lookup_Table_n_D_t1_re[25] = t1_re_25; + assign Direct_Lookup_Table_n_D_t1_re[26] = t1_re_26; + assign Direct_Lookup_Table_n_D_t1_re[27] = t1_re_27; + assign Direct_Lookup_Table_n_D_t1_re[28] = t1_re_28; + assign Direct_Lookup_Table_n_D_t1_re[29] = t1_re_29; + assign Direct_Lookup_Table_n_D_t1_re[30] = t1_re_30; + assign Direct_Lookup_Table_n_D_t1_re[31] = t1_re_31; + assign Direct_Lookup_Table_n_D_t1_re[32] = t1_re_32; + assign Direct_Lookup_Table_n_D_t1_re[33] = t1_re_33; + assign Direct_Lookup_Table_n_D_t1_re[34] = t1_re_34; + assign Direct_Lookup_Table_n_D_t1_re[35] = t1_re_35; + assign Direct_Lookup_Table_n_D_t1_re[36] = t1_re_36; + assign Direct_Lookup_Table_n_D_t1_re[37] = t1_re_37; + assign Direct_Lookup_Table_n_D_t1_re[38] = t1_re_38; + assign Direct_Lookup_Table_n_D_t1_re[39] = t1_re_39; + assign Direct_Lookup_Table_n_D_t1_re[40] = t1_re_40; + assign Direct_Lookup_Table_n_D_t1_re[41] = t1_re_41; + assign Direct_Lookup_Table_n_D_t1_re[42] = t1_re_42; + assign Direct_Lookup_Table_n_D_t1_re[43] = t1_re_43; + assign Direct_Lookup_Table_n_D_t1_re[44] = t1_re_44; + assign Direct_Lookup_Table_n_D_t1_re[45] = t1_re_45; + assign Direct_Lookup_Table_n_D_t1_re[46] = t1_re_46; + assign Direct_Lookup_Table_n_D_t1_re[47] = t1_re_47; + assign Direct_Lookup_Table_n_D_t1_re[48] = t1_re_48; + assign Direct_Lookup_Table_n_D_t1_re[49] = t1_re_49; + assign Direct_Lookup_Table_n_D_t1_re[50] = t1_re_50; + assign Direct_Lookup_Table_n_D_t1_re[51] = t1_re_51; + assign Direct_Lookup_Table_n_D_t1_re[52] = t1_re_52; + assign Direct_Lookup_Table_n_D_t1_re[53] = t1_re_53; + assign Direct_Lookup_Table_n_D_t1_re[54] = t1_re_54; + assign Direct_Lookup_Table_n_D_t1_re[55] = t1_re_55; + assign Direct_Lookup_Table_n_D_t1_re[56] = t1_re_56; + assign Direct_Lookup_Table_n_D_t1_re[57] = t1_re_57; + assign Direct_Lookup_Table_n_D_t1_re[58] = t1_re_58; + assign Direct_Lookup_Table_n_D_t1_re[59] = t1_re_59; + assign Direct_Lookup_Table_n_D_t1_re[60] = t1_re_60; + assign Direct_Lookup_Table_n_D_t1_re[61] = t1_re_61; + assign Direct_Lookup_Table_n_D_t1_re[62] = t1_re_62; + assign Direct_Lookup_Table_n_D_t1_re[63] = t1_re_63; + assign Direct_Lookup_Table_n_D_t1_re[64] = t1_re_64; + assign Direct_Lookup_Table_n_D_t1_re[65] = t1_re_65; + assign Direct_Lookup_Table_n_D_t1_re[66] = t1_re_66; + assign Direct_Lookup_Table_n_D_t1_re[67] = t1_re_67; + assign Direct_Lookup_Table_n_D_t1_re[68] = t1_re_68; + assign Direct_Lookup_Table_n_D_t1_re[69] = t1_re_69; + assign Direct_Lookup_Table_n_D_t1_re[70] = t1_re_70; + assign Direct_Lookup_Table_n_D_t1_re[71] = t1_re_71; + assign Direct_Lookup_Table_n_D_t1_re[72] = t1_re_72; + assign Direct_Lookup_Table_n_D_t1_re[73] = t1_re_73; + assign Direct_Lookup_Table_n_D_t1_re[74] = t1_re_74; + assign Direct_Lookup_Table_n_D_t1_re[75] = t1_re_75; + assign Direct_Lookup_Table_n_D_t1_re[76] = t1_re_76; + assign Direct_Lookup_Table_n_D_t1_re[77] = t1_re_77; + assign Direct_Lookup_Table_n_D_t1_re[78] = t1_re_78; + assign Direct_Lookup_Table_n_D_t1_re[79] = t1_re_79; + assign Direct_Lookup_Table_n_D_t1_re[80] = t1_re_80; + assign Direct_Lookup_Table_n_D_t1_re[81] = t1_re_81; + assign Direct_Lookup_Table_n_D_t1_re[82] = t1_re_82; + assign Direct_Lookup_Table_n_D_t1_re[83] = t1_re_83; + assign Direct_Lookup_Table_n_D_t1_re[84] = t1_re_84; + assign Direct_Lookup_Table_n_D_t1_re[85] = t1_re_85; + assign Direct_Lookup_Table_n_D_t1_re[86] = t1_re_86; + assign Direct_Lookup_Table_n_D_t1_re[87] = t1_re_87; + assign Direct_Lookup_Table_n_D_t1_re[88] = t1_re_88; + assign Direct_Lookup_Table_n_D_t1_re[89] = t1_re_89; + assign Direct_Lookup_Table_n_D_t1_re[90] = t1_re_90; + assign Direct_Lookup_Table_n_D_t1_re[91] = t1_re_91; + assign Direct_Lookup_Table_n_D_t1_re[92] = t1_re_92; + assign Direct_Lookup_Table_n_D_t1_re[93] = t1_re_93; + assign Direct_Lookup_Table_n_D_t1_re[94] = t1_re_94; + assign Direct_Lookup_Table_n_D_t1_re[95] = t1_re_95; + assign Direct_Lookup_Table_n_D_t1_re[96] = t1_re_96; + assign Direct_Lookup_Table_n_D_t1_re[97] = t1_re_97; + assign Direct_Lookup_Table_n_D_t1_re[98] = t1_re_98; + assign Direct_Lookup_Table_n_D_t1_re[99] = t1_re_99; + assign Direct_Lookup_Table_n_D_t1_re[100] = t1_re_100; + assign Direct_Lookup_Table_n_D_t1_re[101] = t1_re_101; + assign Direct_Lookup_Table_n_D_t1_re[102] = t1_re_102; + assign Direct_Lookup_Table_n_D_t1_re[103] = t1_re_103; + assign Direct_Lookup_Table_n_D_t1_re[104] = t1_re_104; + assign Direct_Lookup_Table_n_D_t1_re[105] = t1_re_105; + assign Direct_Lookup_Table_n_D_t1_re[106] = t1_re_106; + assign Direct_Lookup_Table_n_D_t1_re[107] = t1_re_107; + assign Direct_Lookup_Table_n_D_t1_re[108] = t1_re_108; + assign Direct_Lookup_Table_n_D_t1_re[109] = t1_re_109; + assign Direct_Lookup_Table_n_D_t1_re[110] = t1_re_110; + assign Direct_Lookup_Table_n_D_t1_re[111] = t1_re_111; + assign Direct_Lookup_Table_n_D_t1_re[112] = t1_re_112; + assign Direct_Lookup_Table_n_D_t1_re[113] = t1_re_113; + assign Direct_Lookup_Table_n_D_t1_re[114] = t1_re_114; + assign Direct_Lookup_Table_n_D_t1_re[115] = t1_re_115; + assign Direct_Lookup_Table_n_D_t1_re[116] = t1_re_116; + assign Direct_Lookup_Table_n_D_t1_re[117] = t1_re_117; + assign Direct_Lookup_Table_n_D_t1_re[118] = t1_re_118; + assign Direct_Lookup_Table_n_D_t1_re[119] = t1_re_119; + assign Direct_Lookup_Table_n_D_t1_re[120] = t1_re_120; + assign Direct_Lookup_Table_n_D_t1_re[121] = t1_re_121; + assign Direct_Lookup_Table_n_D_t1_re[122] = t1_re_122; + assign Direct_Lookup_Table_n_D_t1_re[123] = t1_re_123; + assign Direct_Lookup_Table_n_D_t1_re[124] = t1_re_124; + assign Direct_Lookup_Table_n_D_t1_re[125] = t1_re_125; + assign Direct_Lookup_Table_n_D_t1_re[126] = t1_re_126; + assign Direct_Lookup_Table_n_D_t1_re[127] = t1_re_127; + assign Direct_Lookup_Table_n_D_t1_re[128] = t1_re_128; + assign Direct_Lookup_Table_n_D_t1_re[129] = t1_re_129; + assign Direct_Lookup_Table_n_D_t1_re[130] = t1_re_130; + assign Direct_Lookup_Table_n_D_t1_re[131] = t1_re_131; + assign Direct_Lookup_Table_n_D_t1_re[132] = t1_re_132; + assign Direct_Lookup_Table_n_D_t1_re[133] = t1_re_133; + assign Direct_Lookup_Table_n_D_t1_re[134] = t1_re_134; + assign Direct_Lookup_Table_n_D_t1_re[135] = t1_re_135; + assign Direct_Lookup_Table_n_D_t1_re[136] = t1_re_136; + assign Direct_Lookup_Table_n_D_t1_re[137] = t1_re_137; + assign Direct_Lookup_Table_n_D_t1_re[138] = t1_re_138; + assign Direct_Lookup_Table_n_D_t1_re[139] = t1_re_139; + assign Direct_Lookup_Table_n_D_t1_re[140] = t1_re_140; + assign Direct_Lookup_Table_n_D_t1_re[141] = t1_re_141; + assign Direct_Lookup_Table_n_D_t1_re[142] = t1_re_142; + assign Direct_Lookup_Table_n_D_t1_re[143] = t1_re_143; + assign Direct_Lookup_Table_n_D_t1_re[144] = t1_re_144; + assign Direct_Lookup_Table_n_D_t1_re[145] = t1_re_145; + assign Direct_Lookup_Table_n_D_t1_re[146] = t1_re_146; + assign Direct_Lookup_Table_n_D_t1_re[147] = t1_re_147; + assign Direct_Lookup_Table_n_D_t1_re[148] = t1_re_148; + assign Direct_Lookup_Table_n_D_t1_re[149] = t1_re_149; + assign Direct_Lookup_Table_n_D_t1_re[150] = t1_re_150; + assign Direct_Lookup_Table_n_D_t1_re[151] = t1_re_151; + assign Direct_Lookup_Table_n_D_t1_re[152] = t1_re_152; + assign Direct_Lookup_Table_n_D_t1_re[153] = t1_re_153; + assign Direct_Lookup_Table_n_D_t1_re[154] = t1_re_154; + assign Direct_Lookup_Table_n_D_t1_re[155] = t1_re_155; + assign Direct_Lookup_Table_n_D_t1_re[156] = t1_re_156; + assign Direct_Lookup_Table_n_D_t1_re[157] = t1_re_157; + assign Direct_Lookup_Table_n_D_t1_re[158] = t1_re_158; + assign Direct_Lookup_Table_n_D_t1_re[159] = t1_re_159; + assign Direct_Lookup_Table_n_D_t1_re[160] = t1_re_160; + assign Direct_Lookup_Table_n_D_t1_re[161] = t1_re_161; + assign Direct_Lookup_Table_n_D_t1_re[162] = t1_re_162; + assign Direct_Lookup_Table_n_D_t1_re[163] = t1_re_163; + assign Direct_Lookup_Table_n_D_t1_re[164] = t1_re_164; + assign Direct_Lookup_Table_n_D_t1_re[165] = t1_re_165; + assign Direct_Lookup_Table_n_D_t1_re[166] = t1_re_166; + assign Direct_Lookup_Table_n_D_t1_re[167] = t1_re_167; + assign Direct_Lookup_Table_n_D_t1_re[168] = t1_re_168; + assign Direct_Lookup_Table_n_D_t1_re[169] = t1_re_169; + assign Direct_Lookup_Table_n_D_t1_re[170] = t1_re_170; + assign Direct_Lookup_Table_n_D_t1_re[171] = t1_re_171; + assign Direct_Lookup_Table_n_D_t1_re[172] = t1_re_172; + assign Direct_Lookup_Table_n_D_t1_re[173] = t1_re_173; + assign Direct_Lookup_Table_n_D_t1_re[174] = t1_re_174; + assign Direct_Lookup_Table_n_D_t1_re[175] = t1_re_175; + assign Direct_Lookup_Table_n_D_t1_re[176] = t1_re_176; + assign Direct_Lookup_Table_n_D_t1_re[177] = t1_re_177; + assign Direct_Lookup_Table_n_D_t1_re[178] = t1_re_178; + assign Direct_Lookup_Table_n_D_t1_re[179] = t1_re_179; + assign Direct_Lookup_Table_n_D_t1_re[180] = t1_re_180; + assign Direct_Lookup_Table_n_D_t1_re[181] = t1_re_181; + assign Direct_Lookup_Table_n_D_t1_re[182] = t1_re_182; + assign Direct_Lookup_Table_n_D_t1_re[183] = t1_re_183; + assign Direct_Lookup_Table_n_D_t1_re[184] = t1_re_184; + assign Direct_Lookup_Table_n_D_t1_re[185] = t1_re_185; + assign Direct_Lookup_Table_n_D_t1_re[186] = t1_re_186; + assign Direct_Lookup_Table_n_D_t1_re[187] = t1_re_187; + assign Direct_Lookup_Table_n_D_t1_re[188] = t1_re_188; + assign Direct_Lookup_Table_n_D_t1_re[189] = t1_re_189; + assign Direct_Lookup_Table_n_D_t1_re[190] = t1_re_190; + assign Direct_Lookup_Table_n_D_t1_re[191] = t1_re_191; + assign Direct_Lookup_Table_n_D_t1_re[192] = t1_re_192; + assign Direct_Lookup_Table_n_D_t1_re[193] = t1_re_193; + assign Direct_Lookup_Table_n_D_t1_re[194] = t1_re_194; + assign Direct_Lookup_Table_n_D_t1_re[195] = t1_re_195; + assign Direct_Lookup_Table_n_D_t1_re[196] = t1_re_196; + assign Direct_Lookup_Table_n_D_t1_re[197] = t1_re_197; + assign Direct_Lookup_Table_n_D_t1_re[198] = t1_re_198; + assign Direct_Lookup_Table_n_D_t1_re[199] = t1_re_199; + assign Direct_Lookup_Table_n_D_t1_re[200] = t1_re_200; + assign Direct_Lookup_Table_n_D_t1_re[201] = t1_re_201; + assign Direct_Lookup_Table_n_D_t1_re[202] = t1_re_202; + assign Direct_Lookup_Table_n_D_t1_re[203] = t1_re_203; + assign Direct_Lookup_Table_n_D_t1_re[204] = t1_re_204; + assign Direct_Lookup_Table_n_D_t1_re[205] = t1_re_205; + assign Direct_Lookup_Table_n_D_t1_re[206] = t1_re_206; + assign Direct_Lookup_Table_n_D_t1_re[207] = t1_re_207; + assign Direct_Lookup_Table_n_D_t1_re[208] = t1_re_208; + assign Direct_Lookup_Table_n_D_t1_re[209] = t1_re_209; + assign Direct_Lookup_Table_n_D_t1_re[210] = t1_re_210; + assign Direct_Lookup_Table_n_D_t1_re[211] = t1_re_211; + assign Direct_Lookup_Table_n_D_t1_re[212] = t1_re_212; + assign Direct_Lookup_Table_n_D_t1_re[213] = t1_re_213; + assign Direct_Lookup_Table_n_D_t1_re[214] = t1_re_214; + assign Direct_Lookup_Table_n_D_t1_re[215] = t1_re_215; + assign Direct_Lookup_Table_n_D_t1_re[216] = t1_re_216; + assign Direct_Lookup_Table_n_D_t1_re[217] = t1_re_217; + assign Direct_Lookup_Table_n_D_t1_re[218] = t1_re_218; + assign Direct_Lookup_Table_n_D_t1_re[219] = t1_re_219; + assign Direct_Lookup_Table_n_D_t1_re[220] = t1_re_220; + assign Direct_Lookup_Table_n_D_t1_re[221] = t1_re_221; + assign Direct_Lookup_Table_n_D_t1_re[222] = t1_re_222; + assign Direct_Lookup_Table_n_D_t1_re[223] = t1_re_223; + assign Direct_Lookup_Table_n_D_t1_re[224] = t1_re_224; + assign Direct_Lookup_Table_n_D_t1_re[225] = t1_re_225; + assign Direct_Lookup_Table_n_D_t1_re[226] = t1_re_226; + assign Direct_Lookup_Table_n_D_t1_re[227] = t1_re_227; + assign Direct_Lookup_Table_n_D_t1_re[228] = t1_re_228; + assign Direct_Lookup_Table_n_D_t1_re[229] = t1_re_229; + assign Direct_Lookup_Table_n_D_t1_re[230] = t1_re_230; + assign Direct_Lookup_Table_n_D_t1_re[231] = t1_re_231; + assign Direct_Lookup_Table_n_D_t1_re[232] = t1_re_232; + assign Direct_Lookup_Table_n_D_t1_re[233] = t1_re_233; + assign Direct_Lookup_Table_n_D_t1_re[234] = t1_re_234; + assign Direct_Lookup_Table_n_D_t1_re[235] = t1_re_235; + assign Direct_Lookup_Table_n_D_t1_re[236] = t1_re_236; + assign Direct_Lookup_Table_n_D_t1_re[237] = t1_re_237; + assign Direct_Lookup_Table_n_D_t1_re[238] = t1_re_238; + assign Direct_Lookup_Table_n_D_t1_re[239] = t1_re_239; + assign Direct_Lookup_Table_n_D_t1_re[240] = t1_re_240; + assign Direct_Lookup_Table_n_D_t1_re[241] = t1_re_241; + assign Direct_Lookup_Table_n_D_t1_re[242] = t1_re_242; + assign Direct_Lookup_Table_n_D_t1_re[243] = t1_re_243; + assign Direct_Lookup_Table_n_D_t1_re[244] = t1_re_244; + assign Direct_Lookup_Table_n_D_t1_re[245] = t1_re_245; + assign Direct_Lookup_Table_n_D_t1_re[246] = t1_re_246; + assign Direct_Lookup_Table_n_D_t1_re[247] = t1_re_247; + assign Direct_Lookup_Table_n_D_t1_re[248] = t1_re_248; + assign Direct_Lookup_Table_n_D_t1_re[249] = t1_re_249; + assign Direct_Lookup_Table_n_D_t1_re[250] = t1_re_250; + assign Direct_Lookup_Table_n_D_t1_re[251] = t1_re_251; + assign Direct_Lookup_Table_n_D_t1_re[252] = t1_re_252; + assign Direct_Lookup_Table_n_D_t1_re[253] = t1_re_253; + assign Direct_Lookup_Table_n_D_t1_re[254] = t1_re_254; + assign Direct_Lookup_Table_n_D_t1_re[255] = t1_re_255; + assign Direct_Lookup_Table_n_D_t1_re[256] = t1_re_256; + assign Direct_Lookup_Table_n_D_t1_re[257] = t1_re_257; + assign Direct_Lookup_Table_n_D_t1_re[258] = t1_re_258; + assign Direct_Lookup_Table_n_D_t1_re[259] = t1_re_259; + assign Direct_Lookup_Table_n_D_t1_re[260] = t1_re_260; + assign Direct_Lookup_Table_n_D_t1_re[261] = t1_re_261; + assign Direct_Lookup_Table_n_D_t1_re[262] = t1_re_262; + assign Direct_Lookup_Table_n_D_t1_re[263] = t1_re_263; + assign Direct_Lookup_Table_n_D_t1_re[264] = t1_re_264; + assign Direct_Lookup_Table_n_D_t1_re[265] = t1_re_265; + assign Direct_Lookup_Table_n_D_t1_re[266] = t1_re_266; + assign Direct_Lookup_Table_n_D_t1_re[267] = t1_re_267; + assign Direct_Lookup_Table_n_D_t1_re[268] = t1_re_268; + assign Direct_Lookup_Table_n_D_t1_re[269] = t1_re_269; + assign Direct_Lookup_Table_n_D_t1_re[270] = t1_re_270; + assign Direct_Lookup_Table_n_D_t1_re[271] = t1_re_271; + assign Direct_Lookup_Table_n_D_t1_re[272] = t1_re_272; + assign Direct_Lookup_Table_n_D_t1_re[273] = t1_re_273; + assign Direct_Lookup_Table_n_D_t1_re[274] = t1_re_274; + assign Direct_Lookup_Table_n_D_t1_re[275] = t1_re_275; + assign Direct_Lookup_Table_n_D_t1_re[276] = t1_re_276; + assign Direct_Lookup_Table_n_D_t1_re[277] = t1_re_277; + assign Direct_Lookup_Table_n_D_t1_re[278] = t1_re_278; + assign Direct_Lookup_Table_n_D_t1_re[279] = t1_re_279; + assign Direct_Lookup_Table_n_D_t1_re[280] = t1_re_280; + assign Direct_Lookup_Table_n_D_t1_re[281] = t1_re_281; + assign Direct_Lookup_Table_n_D_t1_re[282] = t1_re_282; + assign Direct_Lookup_Table_n_D_t1_re[283] = t1_re_283; + assign Direct_Lookup_Table_n_D_t1_re[284] = t1_re_284; + assign Direct_Lookup_Table_n_D_t1_re[285] = t1_re_285; + assign Direct_Lookup_Table_n_D_t1_re[286] = t1_re_286; + assign Direct_Lookup_Table_n_D_t1_re[287] = t1_re_287; + assign Direct_Lookup_Table_n_D_t1_re[288] = t1_re_288; + assign Direct_Lookup_Table_n_D_t1_re[289] = t1_re_289; + assign Direct_Lookup_Table_n_D_t1_re[290] = t1_re_290; + assign Direct_Lookup_Table_n_D_t1_re[291] = t1_re_291; + assign Direct_Lookup_Table_n_D_t1_re[292] = t1_re_292; + assign Direct_Lookup_Table_n_D_t1_re[293] = t1_re_293; + assign Direct_Lookup_Table_n_D_t1_re[294] = t1_re_294; + assign Direct_Lookup_Table_n_D_t1_re[295] = t1_re_295; + assign Direct_Lookup_Table_n_D_t1_re[296] = t1_re_296; + assign Direct_Lookup_Table_n_D_t1_re[297] = t1_re_297; + assign Direct_Lookup_Table_n_D_t1_re[298] = t1_re_298; + assign Direct_Lookup_Table_n_D_t1_re[299] = t1_re_299; + assign Direct_Lookup_Table_n_D_t1_re[300] = t1_re_300; + assign Direct_Lookup_Table_n_D_t1_re[301] = t1_re_301; + assign Direct_Lookup_Table_n_D_t1_re[302] = t1_re_302; + assign Direct_Lookup_Table_n_D_t1_re[303] = t1_re_303; + assign Direct_Lookup_Table_n_D_t1_re[304] = t1_re_304; + assign Direct_Lookup_Table_n_D_t1_re[305] = t1_re_305; + assign Direct_Lookup_Table_n_D_t1_re[306] = t1_re_306; + assign Direct_Lookup_Table_n_D_t1_re[307] = t1_re_307; + assign Direct_Lookup_Table_n_D_t1_re[308] = t1_re_308; + assign Direct_Lookup_Table_n_D_t1_re[309] = t1_re_309; + assign Direct_Lookup_Table_n_D_t1_re[310] = t1_re_310; + assign Direct_Lookup_Table_n_D_t1_re[311] = t1_re_311; + assign Direct_Lookup_Table_n_D_t1_re[312] = t1_re_312; + assign Direct_Lookup_Table_n_D_t1_re[313] = t1_re_313; + assign Direct_Lookup_Table_n_D_t1_re[314] = t1_re_314; + assign Direct_Lookup_Table_n_D_t1_re[315] = t1_re_315; + assign Direct_Lookup_Table_n_D_t1_re[316] = t1_re_316; + assign Direct_Lookup_Table_n_D_t1_re[317] = t1_re_317; + assign Direct_Lookup_Table_n_D_t1_re[318] = t1_re_318; + assign Direct_Lookup_Table_n_D_t1_re[319] = t1_re_319; + assign Direct_Lookup_Table_n_D_t1_re[320] = t1_re_320; + assign Direct_Lookup_Table_n_D_t1_re[321] = t1_re_321; + assign Direct_Lookup_Table_n_D_t1_re[322] = t1_re_322; + assign Direct_Lookup_Table_n_D_t1_re[323] = t1_re_323; + assign Direct_Lookup_Table_n_D_t1_re[324] = t1_re_324; + assign Direct_Lookup_Table_n_D_t1_re[325] = t1_re_325; + assign Direct_Lookup_Table_n_D_t1_re[326] = t1_re_326; + assign Direct_Lookup_Table_n_D_t1_re[327] = t1_re_327; + assign Direct_Lookup_Table_n_D_t1_re[328] = t1_re_328; + assign Direct_Lookup_Table_n_D_t1_re[329] = t1_re_329; + assign Direct_Lookup_Table_n_D_t1_re[330] = t1_re_330; + assign Direct_Lookup_Table_n_D_t1_re[331] = t1_re_331; + assign Direct_Lookup_Table_n_D_t1_re[332] = t1_re_332; + assign Direct_Lookup_Table_n_D_t1_re[333] = t1_re_333; + assign Direct_Lookup_Table_n_D_t1_re[334] = t1_re_334; + assign Direct_Lookup_Table_n_D_t1_re[335] = t1_re_335; + assign Direct_Lookup_Table_n_D_t1_re[336] = t1_re_336; + assign Direct_Lookup_Table_n_D_t1_re[337] = t1_re_337; + assign Direct_Lookup_Table_n_D_t1_re[338] = t1_re_338; + assign Direct_Lookup_Table_n_D_t1_re[339] = t1_re_339; + assign Direct_Lookup_Table_n_D_t1_re[340] = t1_re_340; + assign Direct_Lookup_Table_n_D_t1_re[341] = t1_re_341; + assign Direct_Lookup_Table_n_D_t1_re[342] = t1_re_342; + assign Direct_Lookup_Table_n_D_t1_re[343] = t1_re_343; + assign Direct_Lookup_Table_n_D_t1_re[344] = t1_re_344; + assign Direct_Lookup_Table_n_D_t1_re[345] = t1_re_345; + assign Direct_Lookup_Table_n_D_t1_re[346] = t1_re_346; + assign Direct_Lookup_Table_n_D_t1_re[347] = t1_re_347; + assign Direct_Lookup_Table_n_D_t1_re[348] = t1_re_348; + assign Direct_Lookup_Table_n_D_t1_re[349] = t1_re_349; + assign Direct_Lookup_Table_n_D_t1_re[350] = t1_re_350; + assign Direct_Lookup_Table_n_D_t1_re[351] = t1_re_351; + assign Direct_Lookup_Table_n_D_t1_re[352] = t1_re_352; + assign Direct_Lookup_Table_n_D_t1_re[353] = t1_re_353; + assign Direct_Lookup_Table_n_D_t1_re[354] = t1_re_354; + assign Direct_Lookup_Table_n_D_t1_re[355] = t1_re_355; + assign Direct_Lookup_Table_n_D_t1_re[356] = t1_re_356; + assign Direct_Lookup_Table_n_D_t1_re[357] = t1_re_357; + assign Direct_Lookup_Table_n_D_t1_re[358] = t1_re_358; + assign Direct_Lookup_Table_n_D_t1_re[359] = t1_re_359; + assign Direct_Lookup_Table_n_D_t1_re[360] = t1_re_360; + assign Direct_Lookup_Table_n_D_t1_re[361] = t1_re_361; + assign Direct_Lookup_Table_n_D_t1_re[362] = t1_re_362; + assign Direct_Lookup_Table_n_D_t1_re[363] = t1_re_363; + assign Direct_Lookup_Table_n_D_t1_re[364] = t1_re_364; + assign Direct_Lookup_Table_n_D_t1_re[365] = t1_re_365; + assign Direct_Lookup_Table_n_D_t1_re[366] = t1_re_366; + assign Direct_Lookup_Table_n_D_t1_re[367] = t1_re_367; + assign Direct_Lookup_Table_n_D_t1_re[368] = t1_re_368; + assign Direct_Lookup_Table_n_D_t1_re[369] = t1_re_369; + assign Direct_Lookup_Table_n_D_t1_re[370] = t1_re_370; + assign Direct_Lookup_Table_n_D_t1_re[371] = t1_re_371; + assign Direct_Lookup_Table_n_D_t1_re[372] = t1_re_372; + assign Direct_Lookup_Table_n_D_t1_re[373] = t1_re_373; + assign Direct_Lookup_Table_n_D_t1_re[374] = t1_re_374; + assign Direct_Lookup_Table_n_D_t1_re[375] = t1_re_375; + assign Direct_Lookup_Table_n_D_t1_re[376] = t1_re_376; + assign Direct_Lookup_Table_n_D_t1_re[377] = t1_re_377; + assign Direct_Lookup_Table_n_D_t1_re[378] = t1_re_378; + assign Direct_Lookup_Table_n_D_t1_re[379] = t1_re_379; + assign Direct_Lookup_Table_n_D_t1_re[380] = t1_re_380; + assign Direct_Lookup_Table_n_D_t1_re[381] = t1_re_381; + assign Direct_Lookup_Table_n_D_t1_re[382] = t1_re_382; + assign Direct_Lookup_Table_n_D_t1_re[383] = t1_re_383; + assign Direct_Lookup_Table_n_D_t1_re[384] = t1_re_384; + assign Direct_Lookup_Table_n_D_t1_re[385] = t1_re_385; + assign Direct_Lookup_Table_n_D_t1_re[386] = t1_re_386; + assign Direct_Lookup_Table_n_D_t1_re[387] = t1_re_387; + assign Direct_Lookup_Table_n_D_t1_re[388] = t1_re_388; + assign Direct_Lookup_Table_n_D_t1_re[389] = t1_re_389; + assign Direct_Lookup_Table_n_D_t1_re[390] = t1_re_390; + assign Direct_Lookup_Table_n_D_t1_re[391] = t1_re_391; + assign Direct_Lookup_Table_n_D_t1_re[392] = t1_re_392; + assign Direct_Lookup_Table_n_D_t1_re[393] = t1_re_393; + assign Direct_Lookup_Table_n_D_t1_re[394] = t1_re_394; + assign Direct_Lookup_Table_n_D_t1_re[395] = t1_re_395; + assign Direct_Lookup_Table_n_D_t1_re[396] = t1_re_396; + assign Direct_Lookup_Table_n_D_t1_re[397] = t1_re_397; + assign Direct_Lookup_Table_n_D_t1_re[398] = t1_re_398; + assign Direct_Lookup_Table_n_D_t1_re[399] = t1_re_399; + assign Direct_Lookup_Table_n_D_t1_re[400] = t1_re_400; + assign Direct_Lookup_Table_n_D_t1_re[401] = t1_re_401; + assign Direct_Lookup_Table_n_D_t1_re[402] = t1_re_402; + assign Direct_Lookup_Table_n_D_t1_re[403] = t1_re_403; + assign Direct_Lookup_Table_n_D_t1_re[404] = t1_re_404; + assign Direct_Lookup_Table_n_D_t1_re[405] = t1_re_405; + assign Direct_Lookup_Table_n_D_t1_re[406] = t1_re_406; + assign Direct_Lookup_Table_n_D_t1_re[407] = t1_re_407; + assign Direct_Lookup_Table_n_D_t1_re[408] = t1_re_408; + assign Direct_Lookup_Table_n_D_t1_re[409] = t1_re_409; + assign Direct_Lookup_Table_n_D_t1_re[410] = t1_re_410; + assign Direct_Lookup_Table_n_D_t1_re[411] = t1_re_411; + assign Direct_Lookup_Table_n_D_t1_re[412] = t1_re_412; + assign Direct_Lookup_Table_n_D_t1_re[413] = t1_re_413; + assign Direct_Lookup_Table_n_D_t1_re[414] = t1_re_414; + assign Direct_Lookup_Table_n_D_t1_re[415] = t1_re_415; + assign Direct_Lookup_Table_n_D_t1_re[416] = t1_re_416; + assign Direct_Lookup_Table_n_D_t1_re[417] = t1_re_417; + assign Direct_Lookup_Table_n_D_t1_re[418] = t1_re_418; + assign Direct_Lookup_Table_n_D_t1_re[419] = t1_re_419; + assign Direct_Lookup_Table_n_D_t1_re[420] = t1_re_420; + assign Direct_Lookup_Table_n_D_t1_re[421] = t1_re_421; + assign Direct_Lookup_Table_n_D_t1_re[422] = t1_re_422; + assign Direct_Lookup_Table_n_D_t1_re[423] = t1_re_423; + assign Direct_Lookup_Table_n_D_t1_re[424] = t1_re_424; + assign Direct_Lookup_Table_n_D_t1_re[425] = t1_re_425; + assign Direct_Lookup_Table_n_D_t1_re[426] = t1_re_426; + assign Direct_Lookup_Table_n_D_t1_re[427] = t1_re_427; + assign Direct_Lookup_Table_n_D_t1_re[428] = t1_re_428; + assign Direct_Lookup_Table_n_D_t1_re[429] = t1_re_429; + assign Direct_Lookup_Table_n_D_t1_re[430] = t1_re_430; + assign Direct_Lookup_Table_n_D_t1_re[431] = t1_re_431; + assign Direct_Lookup_Table_n_D_t1_re[432] = t1_re_432; + assign Direct_Lookup_Table_n_D_t1_re[433] = t1_re_433; + assign Direct_Lookup_Table_n_D_t1_re[434] = t1_re_434; + assign Direct_Lookup_Table_n_D_t1_re[435] = t1_re_435; + assign Direct_Lookup_Table_n_D_t1_re[436] = t1_re_436; + assign Direct_Lookup_Table_n_D_t1_re[437] = t1_re_437; + assign Direct_Lookup_Table_n_D_t1_re[438] = t1_re_438; + assign Direct_Lookup_Table_n_D_t1_re[439] = t1_re_439; + assign Direct_Lookup_Table_n_D_t1_re[440] = t1_re_440; + assign Direct_Lookup_Table_n_D_t1_re[441] = t1_re_441; + assign Direct_Lookup_Table_n_D_t1_re[442] = t1_re_442; + assign Direct_Lookup_Table_n_D_t1_re[443] = t1_re_443; + assign Direct_Lookup_Table_n_D_t1_re[444] = t1_re_444; + assign Direct_Lookup_Table_n_D_t1_re[445] = t1_re_445; + assign Direct_Lookup_Table_n_D_t1_re[446] = t1_re_446; + assign Direct_Lookup_Table_n_D_t1_re[447] = t1_re_447; + assign Direct_Lookup_Table_n_D_t1_re[448] = t1_re_448; + assign Direct_Lookup_Table_n_D_t1_re[449] = t1_re_449; + assign Direct_Lookup_Table_n_D_t1_re[450] = t1_re_450; + assign Direct_Lookup_Table_n_D_t1_re[451] = t1_re_451; + assign Direct_Lookup_Table_n_D_t1_re[452] = t1_re_452; + assign Direct_Lookup_Table_n_D_t1_re[453] = t1_re_453; + assign Direct_Lookup_Table_n_D_t1_re[454] = t1_re_454; + assign Direct_Lookup_Table_n_D_t1_re[455] = t1_re_455; + assign Direct_Lookup_Table_n_D_t1_re[456] = t1_re_456; + assign Direct_Lookup_Table_n_D_t1_re[457] = t1_re_457; + assign Direct_Lookup_Table_n_D_t1_re[458] = t1_re_458; + assign Direct_Lookup_Table_n_D_t1_re[459] = t1_re_459; + assign Direct_Lookup_Table_n_D_t1_re[460] = t1_re_460; + assign Direct_Lookup_Table_n_D_t1_re[461] = t1_re_461; + assign Direct_Lookup_Table_n_D_t1_re[462] = t1_re_462; + assign Direct_Lookup_Table_n_D_t1_re[463] = t1_re_463; + assign Direct_Lookup_Table_n_D_t1_re[464] = t1_re_464; + assign Direct_Lookup_Table_n_D_t1_re[465] = t1_re_465; + assign Direct_Lookup_Table_n_D_t1_re[466] = t1_re_466; + assign Direct_Lookup_Table_n_D_t1_re[467] = t1_re_467; + assign Direct_Lookup_Table_n_D_t1_re[468] = t1_re_468; + assign Direct_Lookup_Table_n_D_t1_re[469] = t1_re_469; + assign Direct_Lookup_Table_n_D_t1_re[470] = t1_re_470; + assign Direct_Lookup_Table_n_D_t1_re[471] = t1_re_471; + assign Direct_Lookup_Table_n_D_t1_re[472] = t1_re_472; + assign Direct_Lookup_Table_n_D_t1_re[473] = t1_re_473; + assign Direct_Lookup_Table_n_D_t1_re[474] = t1_re_474; + assign Direct_Lookup_Table_n_D_t1_re[475] = t1_re_475; + assign Direct_Lookup_Table_n_D_t1_re[476] = t1_re_476; + assign Direct_Lookup_Table_n_D_t1_re[477] = t1_re_477; + assign Direct_Lookup_Table_n_D_t1_re[478] = t1_re_478; + assign Direct_Lookup_Table_n_D_t1_re[479] = t1_re_479; + assign Direct_Lookup_Table_n_D_t1_re[480] = t1_re_480; + assign Direct_Lookup_Table_n_D_t1_re[481] = t1_re_481; + assign Direct_Lookup_Table_n_D_t1_re[482] = t1_re_482; + assign Direct_Lookup_Table_n_D_t1_re[483] = t1_re_483; + assign Direct_Lookup_Table_n_D_t1_re[484] = t1_re_484; + assign Direct_Lookup_Table_n_D_t1_re[485] = t1_re_485; + assign Direct_Lookup_Table_n_D_t1_re[486] = t1_re_486; + assign Direct_Lookup_Table_n_D_t1_re[487] = t1_re_487; + assign Direct_Lookup_Table_n_D_t1_re[488] = t1_re_488; + assign Direct_Lookup_Table_n_D_t1_re[489] = t1_re_489; + assign Direct_Lookup_Table_n_D_t1_re[490] = t1_re_490; + assign Direct_Lookup_Table_n_D_t1_re[491] = t1_re_491; + assign Direct_Lookup_Table_n_D_t1_re[492] = t1_re_492; + assign Direct_Lookup_Table_n_D_t1_re[493] = t1_re_493; + assign Direct_Lookup_Table_n_D_t1_re[494] = t1_re_494; + assign Direct_Lookup_Table_n_D_t1_re[495] = t1_re_495; + assign Direct_Lookup_Table_n_D_t1_re[496] = t1_re_496; + assign Direct_Lookup_Table_n_D_t1_re[497] = t1_re_497; + assign Direct_Lookup_Table_n_D_t1_re[498] = t1_re_498; + assign Direct_Lookup_Table_n_D_t1_re[499] = t1_re_499; + assign Direct_Lookup_Table_n_D_t1_re[500] = t1_re_500; + assign Direct_Lookup_Table_n_D_t1_re[501] = t1_re_501; + assign Direct_Lookup_Table_n_D_t1_re[502] = t1_re_502; + assign Direct_Lookup_Table_n_D_t1_re[503] = t1_re_503; + assign Direct_Lookup_Table_n_D_t1_re[504] = t1_re_504; + assign Direct_Lookup_Table_n_D_t1_re[505] = t1_re_505; + assign Direct_Lookup_Table_n_D_t1_re[506] = t1_re_506; + assign Direct_Lookup_Table_n_D_t1_re[507] = t1_re_507; + assign Direct_Lookup_Table_n_D_t1_re[508] = t1_re_508; + assign Direct_Lookup_Table_n_D_t1_re[509] = t1_re_509; + assign Direct_Lookup_Table_n_D_t1_re[510] = t1_re_510; + assign Direct_Lookup_Table_n_D_t1_re[511] = t1_re_511; + assign Direct_Lookup_Table_n_D_t1_im[0] = t1_im_0; + assign Direct_Lookup_Table_n_D_t1_im[1] = t1_im_1; + assign Direct_Lookup_Table_n_D_t1_im[2] = t1_im_2; + assign Direct_Lookup_Table_n_D_t1_im[3] = t1_im_3; + assign Direct_Lookup_Table_n_D_t1_im[4] = t1_im_4; + assign Direct_Lookup_Table_n_D_t1_im[5] = t1_im_5; + assign Direct_Lookup_Table_n_D_t1_im[6] = t1_im_6; + assign Direct_Lookup_Table_n_D_t1_im[7] = t1_im_7; + assign Direct_Lookup_Table_n_D_t1_im[8] = t1_im_8; + assign Direct_Lookup_Table_n_D_t1_im[9] = t1_im_9; + assign Direct_Lookup_Table_n_D_t1_im[10] = t1_im_10; + assign Direct_Lookup_Table_n_D_t1_im[11] = t1_im_11; + assign Direct_Lookup_Table_n_D_t1_im[12] = t1_im_12; + assign Direct_Lookup_Table_n_D_t1_im[13] = t1_im_13; + assign Direct_Lookup_Table_n_D_t1_im[14] = t1_im_14; + assign Direct_Lookup_Table_n_D_t1_im[15] = t1_im_15; + assign Direct_Lookup_Table_n_D_t1_im[16] = t1_im_16; + assign Direct_Lookup_Table_n_D_t1_im[17] = t1_im_17; + assign Direct_Lookup_Table_n_D_t1_im[18] = t1_im_18; + assign Direct_Lookup_Table_n_D_t1_im[19] = t1_im_19; + assign Direct_Lookup_Table_n_D_t1_im[20] = t1_im_20; + assign Direct_Lookup_Table_n_D_t1_im[21] = t1_im_21; + assign Direct_Lookup_Table_n_D_t1_im[22] = t1_im_22; + assign Direct_Lookup_Table_n_D_t1_im[23] = t1_im_23; + assign Direct_Lookup_Table_n_D_t1_im[24] = t1_im_24; + assign Direct_Lookup_Table_n_D_t1_im[25] = t1_im_25; + assign Direct_Lookup_Table_n_D_t1_im[26] = t1_im_26; + assign Direct_Lookup_Table_n_D_t1_im[27] = t1_im_27; + assign Direct_Lookup_Table_n_D_t1_im[28] = t1_im_28; + assign Direct_Lookup_Table_n_D_t1_im[29] = t1_im_29; + assign Direct_Lookup_Table_n_D_t1_im[30] = t1_im_30; + assign Direct_Lookup_Table_n_D_t1_im[31] = t1_im_31; + assign Direct_Lookup_Table_n_D_t1_im[32] = t1_im_32; + assign Direct_Lookup_Table_n_D_t1_im[33] = t1_im_33; + assign Direct_Lookup_Table_n_D_t1_im[34] = t1_im_34; + assign Direct_Lookup_Table_n_D_t1_im[35] = t1_im_35; + assign Direct_Lookup_Table_n_D_t1_im[36] = t1_im_36; + assign Direct_Lookup_Table_n_D_t1_im[37] = t1_im_37; + assign Direct_Lookup_Table_n_D_t1_im[38] = t1_im_38; + assign Direct_Lookup_Table_n_D_t1_im[39] = t1_im_39; + assign Direct_Lookup_Table_n_D_t1_im[40] = t1_im_40; + assign Direct_Lookup_Table_n_D_t1_im[41] = t1_im_41; + assign Direct_Lookup_Table_n_D_t1_im[42] = t1_im_42; + assign Direct_Lookup_Table_n_D_t1_im[43] = t1_im_43; + assign Direct_Lookup_Table_n_D_t1_im[44] = t1_im_44; + assign Direct_Lookup_Table_n_D_t1_im[45] = t1_im_45; + assign Direct_Lookup_Table_n_D_t1_im[46] = t1_im_46; + assign Direct_Lookup_Table_n_D_t1_im[47] = t1_im_47; + assign Direct_Lookup_Table_n_D_t1_im[48] = t1_im_48; + assign Direct_Lookup_Table_n_D_t1_im[49] = t1_im_49; + assign Direct_Lookup_Table_n_D_t1_im[50] = t1_im_50; + assign Direct_Lookup_Table_n_D_t1_im[51] = t1_im_51; + assign Direct_Lookup_Table_n_D_t1_im[52] = t1_im_52; + assign Direct_Lookup_Table_n_D_t1_im[53] = t1_im_53; + assign Direct_Lookup_Table_n_D_t1_im[54] = t1_im_54; + assign Direct_Lookup_Table_n_D_t1_im[55] = t1_im_55; + assign Direct_Lookup_Table_n_D_t1_im[56] = t1_im_56; + assign Direct_Lookup_Table_n_D_t1_im[57] = t1_im_57; + assign Direct_Lookup_Table_n_D_t1_im[58] = t1_im_58; + assign Direct_Lookup_Table_n_D_t1_im[59] = t1_im_59; + assign Direct_Lookup_Table_n_D_t1_im[60] = t1_im_60; + assign Direct_Lookup_Table_n_D_t1_im[61] = t1_im_61; + assign Direct_Lookup_Table_n_D_t1_im[62] = t1_im_62; + assign Direct_Lookup_Table_n_D_t1_im[63] = t1_im_63; + assign Direct_Lookup_Table_n_D_t1_im[64] = t1_im_64; + assign Direct_Lookup_Table_n_D_t1_im[65] = t1_im_65; + assign Direct_Lookup_Table_n_D_t1_im[66] = t1_im_66; + assign Direct_Lookup_Table_n_D_t1_im[67] = t1_im_67; + assign Direct_Lookup_Table_n_D_t1_im[68] = t1_im_68; + assign Direct_Lookup_Table_n_D_t1_im[69] = t1_im_69; + assign Direct_Lookup_Table_n_D_t1_im[70] = t1_im_70; + assign Direct_Lookup_Table_n_D_t1_im[71] = t1_im_71; + assign Direct_Lookup_Table_n_D_t1_im[72] = t1_im_72; + assign Direct_Lookup_Table_n_D_t1_im[73] = t1_im_73; + assign Direct_Lookup_Table_n_D_t1_im[74] = t1_im_74; + assign Direct_Lookup_Table_n_D_t1_im[75] = t1_im_75; + assign Direct_Lookup_Table_n_D_t1_im[76] = t1_im_76; + assign Direct_Lookup_Table_n_D_t1_im[77] = t1_im_77; + assign Direct_Lookup_Table_n_D_t1_im[78] = t1_im_78; + assign Direct_Lookup_Table_n_D_t1_im[79] = t1_im_79; + assign Direct_Lookup_Table_n_D_t1_im[80] = t1_im_80; + assign Direct_Lookup_Table_n_D_t1_im[81] = t1_im_81; + assign Direct_Lookup_Table_n_D_t1_im[82] = t1_im_82; + assign Direct_Lookup_Table_n_D_t1_im[83] = t1_im_83; + assign Direct_Lookup_Table_n_D_t1_im[84] = t1_im_84; + assign Direct_Lookup_Table_n_D_t1_im[85] = t1_im_85; + assign Direct_Lookup_Table_n_D_t1_im[86] = t1_im_86; + assign Direct_Lookup_Table_n_D_t1_im[87] = t1_im_87; + assign Direct_Lookup_Table_n_D_t1_im[88] = t1_im_88; + assign Direct_Lookup_Table_n_D_t1_im[89] = t1_im_89; + assign Direct_Lookup_Table_n_D_t1_im[90] = t1_im_90; + assign Direct_Lookup_Table_n_D_t1_im[91] = t1_im_91; + assign Direct_Lookup_Table_n_D_t1_im[92] = t1_im_92; + assign Direct_Lookup_Table_n_D_t1_im[93] = t1_im_93; + assign Direct_Lookup_Table_n_D_t1_im[94] = t1_im_94; + assign Direct_Lookup_Table_n_D_t1_im[95] = t1_im_95; + assign Direct_Lookup_Table_n_D_t1_im[96] = t1_im_96; + assign Direct_Lookup_Table_n_D_t1_im[97] = t1_im_97; + assign Direct_Lookup_Table_n_D_t1_im[98] = t1_im_98; + assign Direct_Lookup_Table_n_D_t1_im[99] = t1_im_99; + assign Direct_Lookup_Table_n_D_t1_im[100] = t1_im_100; + assign Direct_Lookup_Table_n_D_t1_im[101] = t1_im_101; + assign Direct_Lookup_Table_n_D_t1_im[102] = t1_im_102; + assign Direct_Lookup_Table_n_D_t1_im[103] = t1_im_103; + assign Direct_Lookup_Table_n_D_t1_im[104] = t1_im_104; + assign Direct_Lookup_Table_n_D_t1_im[105] = t1_im_105; + assign Direct_Lookup_Table_n_D_t1_im[106] = t1_im_106; + assign Direct_Lookup_Table_n_D_t1_im[107] = t1_im_107; + assign Direct_Lookup_Table_n_D_t1_im[108] = t1_im_108; + assign Direct_Lookup_Table_n_D_t1_im[109] = t1_im_109; + assign Direct_Lookup_Table_n_D_t1_im[110] = t1_im_110; + assign Direct_Lookup_Table_n_D_t1_im[111] = t1_im_111; + assign Direct_Lookup_Table_n_D_t1_im[112] = t1_im_112; + assign Direct_Lookup_Table_n_D_t1_im[113] = t1_im_113; + assign Direct_Lookup_Table_n_D_t1_im[114] = t1_im_114; + assign Direct_Lookup_Table_n_D_t1_im[115] = t1_im_115; + assign Direct_Lookup_Table_n_D_t1_im[116] = t1_im_116; + assign Direct_Lookup_Table_n_D_t1_im[117] = t1_im_117; + assign Direct_Lookup_Table_n_D_t1_im[118] = t1_im_118; + assign Direct_Lookup_Table_n_D_t1_im[119] = t1_im_119; + assign Direct_Lookup_Table_n_D_t1_im[120] = t1_im_120; + assign Direct_Lookup_Table_n_D_t1_im[121] = t1_im_121; + assign Direct_Lookup_Table_n_D_t1_im[122] = t1_im_122; + assign Direct_Lookup_Table_n_D_t1_im[123] = t1_im_123; + assign Direct_Lookup_Table_n_D_t1_im[124] = t1_im_124; + assign Direct_Lookup_Table_n_D_t1_im[125] = t1_im_125; + assign Direct_Lookup_Table_n_D_t1_im[126] = t1_im_126; + assign Direct_Lookup_Table_n_D_t1_im[127] = t1_im_127; + assign Direct_Lookup_Table_n_D_t1_im[128] = t1_im_128; + assign Direct_Lookup_Table_n_D_t1_im[129] = t1_im_129; + assign Direct_Lookup_Table_n_D_t1_im[130] = t1_im_130; + assign Direct_Lookup_Table_n_D_t1_im[131] = t1_im_131; + assign Direct_Lookup_Table_n_D_t1_im[132] = t1_im_132; + assign Direct_Lookup_Table_n_D_t1_im[133] = t1_im_133; + assign Direct_Lookup_Table_n_D_t1_im[134] = t1_im_134; + assign Direct_Lookup_Table_n_D_t1_im[135] = t1_im_135; + assign Direct_Lookup_Table_n_D_t1_im[136] = t1_im_136; + assign Direct_Lookup_Table_n_D_t1_im[137] = t1_im_137; + assign Direct_Lookup_Table_n_D_t1_im[138] = t1_im_138; + assign Direct_Lookup_Table_n_D_t1_im[139] = t1_im_139; + assign Direct_Lookup_Table_n_D_t1_im[140] = t1_im_140; + assign Direct_Lookup_Table_n_D_t1_im[141] = t1_im_141; + assign Direct_Lookup_Table_n_D_t1_im[142] = t1_im_142; + assign Direct_Lookup_Table_n_D_t1_im[143] = t1_im_143; + assign Direct_Lookup_Table_n_D_t1_im[144] = t1_im_144; + assign Direct_Lookup_Table_n_D_t1_im[145] = t1_im_145; + assign Direct_Lookup_Table_n_D_t1_im[146] = t1_im_146; + assign Direct_Lookup_Table_n_D_t1_im[147] = t1_im_147; + assign Direct_Lookup_Table_n_D_t1_im[148] = t1_im_148; + assign Direct_Lookup_Table_n_D_t1_im[149] = t1_im_149; + assign Direct_Lookup_Table_n_D_t1_im[150] = t1_im_150; + assign Direct_Lookup_Table_n_D_t1_im[151] = t1_im_151; + assign Direct_Lookup_Table_n_D_t1_im[152] = t1_im_152; + assign Direct_Lookup_Table_n_D_t1_im[153] = t1_im_153; + assign Direct_Lookup_Table_n_D_t1_im[154] = t1_im_154; + assign Direct_Lookup_Table_n_D_t1_im[155] = t1_im_155; + assign Direct_Lookup_Table_n_D_t1_im[156] = t1_im_156; + assign Direct_Lookup_Table_n_D_t1_im[157] = t1_im_157; + assign Direct_Lookup_Table_n_D_t1_im[158] = t1_im_158; + assign Direct_Lookup_Table_n_D_t1_im[159] = t1_im_159; + assign Direct_Lookup_Table_n_D_t1_im[160] = t1_im_160; + assign Direct_Lookup_Table_n_D_t1_im[161] = t1_im_161; + assign Direct_Lookup_Table_n_D_t1_im[162] = t1_im_162; + assign Direct_Lookup_Table_n_D_t1_im[163] = t1_im_163; + assign Direct_Lookup_Table_n_D_t1_im[164] = t1_im_164; + assign Direct_Lookup_Table_n_D_t1_im[165] = t1_im_165; + assign Direct_Lookup_Table_n_D_t1_im[166] = t1_im_166; + assign Direct_Lookup_Table_n_D_t1_im[167] = t1_im_167; + assign Direct_Lookup_Table_n_D_t1_im[168] = t1_im_168; + assign Direct_Lookup_Table_n_D_t1_im[169] = t1_im_169; + assign Direct_Lookup_Table_n_D_t1_im[170] = t1_im_170; + assign Direct_Lookup_Table_n_D_t1_im[171] = t1_im_171; + assign Direct_Lookup_Table_n_D_t1_im[172] = t1_im_172; + assign Direct_Lookup_Table_n_D_t1_im[173] = t1_im_173; + assign Direct_Lookup_Table_n_D_t1_im[174] = t1_im_174; + assign Direct_Lookup_Table_n_D_t1_im[175] = t1_im_175; + assign Direct_Lookup_Table_n_D_t1_im[176] = t1_im_176; + assign Direct_Lookup_Table_n_D_t1_im[177] = t1_im_177; + assign Direct_Lookup_Table_n_D_t1_im[178] = t1_im_178; + assign Direct_Lookup_Table_n_D_t1_im[179] = t1_im_179; + assign Direct_Lookup_Table_n_D_t1_im[180] = t1_im_180; + assign Direct_Lookup_Table_n_D_t1_im[181] = t1_im_181; + assign Direct_Lookup_Table_n_D_t1_im[182] = t1_im_182; + assign Direct_Lookup_Table_n_D_t1_im[183] = t1_im_183; + assign Direct_Lookup_Table_n_D_t1_im[184] = t1_im_184; + assign Direct_Lookup_Table_n_D_t1_im[185] = t1_im_185; + assign Direct_Lookup_Table_n_D_t1_im[186] = t1_im_186; + assign Direct_Lookup_Table_n_D_t1_im[187] = t1_im_187; + assign Direct_Lookup_Table_n_D_t1_im[188] = t1_im_188; + assign Direct_Lookup_Table_n_D_t1_im[189] = t1_im_189; + assign Direct_Lookup_Table_n_D_t1_im[190] = t1_im_190; + assign Direct_Lookup_Table_n_D_t1_im[191] = t1_im_191; + assign Direct_Lookup_Table_n_D_t1_im[192] = t1_im_192; + assign Direct_Lookup_Table_n_D_t1_im[193] = t1_im_193; + assign Direct_Lookup_Table_n_D_t1_im[194] = t1_im_194; + assign Direct_Lookup_Table_n_D_t1_im[195] = t1_im_195; + assign Direct_Lookup_Table_n_D_t1_im[196] = t1_im_196; + assign Direct_Lookup_Table_n_D_t1_im[197] = t1_im_197; + assign Direct_Lookup_Table_n_D_t1_im[198] = t1_im_198; + assign Direct_Lookup_Table_n_D_t1_im[199] = t1_im_199; + assign Direct_Lookup_Table_n_D_t1_im[200] = t1_im_200; + assign Direct_Lookup_Table_n_D_t1_im[201] = t1_im_201; + assign Direct_Lookup_Table_n_D_t1_im[202] = t1_im_202; + assign Direct_Lookup_Table_n_D_t1_im[203] = t1_im_203; + assign Direct_Lookup_Table_n_D_t1_im[204] = t1_im_204; + assign Direct_Lookup_Table_n_D_t1_im[205] = t1_im_205; + assign Direct_Lookup_Table_n_D_t1_im[206] = t1_im_206; + assign Direct_Lookup_Table_n_D_t1_im[207] = t1_im_207; + assign Direct_Lookup_Table_n_D_t1_im[208] = t1_im_208; + assign Direct_Lookup_Table_n_D_t1_im[209] = t1_im_209; + assign Direct_Lookup_Table_n_D_t1_im[210] = t1_im_210; + assign Direct_Lookup_Table_n_D_t1_im[211] = t1_im_211; + assign Direct_Lookup_Table_n_D_t1_im[212] = t1_im_212; + assign Direct_Lookup_Table_n_D_t1_im[213] = t1_im_213; + assign Direct_Lookup_Table_n_D_t1_im[214] = t1_im_214; + assign Direct_Lookup_Table_n_D_t1_im[215] = t1_im_215; + assign Direct_Lookup_Table_n_D_t1_im[216] = t1_im_216; + assign Direct_Lookup_Table_n_D_t1_im[217] = t1_im_217; + assign Direct_Lookup_Table_n_D_t1_im[218] = t1_im_218; + assign Direct_Lookup_Table_n_D_t1_im[219] = t1_im_219; + assign Direct_Lookup_Table_n_D_t1_im[220] = t1_im_220; + assign Direct_Lookup_Table_n_D_t1_im[221] = t1_im_221; + assign Direct_Lookup_Table_n_D_t1_im[222] = t1_im_222; + assign Direct_Lookup_Table_n_D_t1_im[223] = t1_im_223; + assign Direct_Lookup_Table_n_D_t1_im[224] = t1_im_224; + assign Direct_Lookup_Table_n_D_t1_im[225] = t1_im_225; + assign Direct_Lookup_Table_n_D_t1_im[226] = t1_im_226; + assign Direct_Lookup_Table_n_D_t1_im[227] = t1_im_227; + assign Direct_Lookup_Table_n_D_t1_im[228] = t1_im_228; + assign Direct_Lookup_Table_n_D_t1_im[229] = t1_im_229; + assign Direct_Lookup_Table_n_D_t1_im[230] = t1_im_230; + assign Direct_Lookup_Table_n_D_t1_im[231] = t1_im_231; + assign Direct_Lookup_Table_n_D_t1_im[232] = t1_im_232; + assign Direct_Lookup_Table_n_D_t1_im[233] = t1_im_233; + assign Direct_Lookup_Table_n_D_t1_im[234] = t1_im_234; + assign Direct_Lookup_Table_n_D_t1_im[235] = t1_im_235; + assign Direct_Lookup_Table_n_D_t1_im[236] = t1_im_236; + assign Direct_Lookup_Table_n_D_t1_im[237] = t1_im_237; + assign Direct_Lookup_Table_n_D_t1_im[238] = t1_im_238; + assign Direct_Lookup_Table_n_D_t1_im[239] = t1_im_239; + assign Direct_Lookup_Table_n_D_t1_im[240] = t1_im_240; + assign Direct_Lookup_Table_n_D_t1_im[241] = t1_im_241; + assign Direct_Lookup_Table_n_D_t1_im[242] = t1_im_242; + assign Direct_Lookup_Table_n_D_t1_im[243] = t1_im_243; + assign Direct_Lookup_Table_n_D_t1_im[244] = t1_im_244; + assign Direct_Lookup_Table_n_D_t1_im[245] = t1_im_245; + assign Direct_Lookup_Table_n_D_t1_im[246] = t1_im_246; + assign Direct_Lookup_Table_n_D_t1_im[247] = t1_im_247; + assign Direct_Lookup_Table_n_D_t1_im[248] = t1_im_248; + assign Direct_Lookup_Table_n_D_t1_im[249] = t1_im_249; + assign Direct_Lookup_Table_n_D_t1_im[250] = t1_im_250; + assign Direct_Lookup_Table_n_D_t1_im[251] = t1_im_251; + assign Direct_Lookup_Table_n_D_t1_im[252] = t1_im_252; + assign Direct_Lookup_Table_n_D_t1_im[253] = t1_im_253; + assign Direct_Lookup_Table_n_D_t1_im[254] = t1_im_254; + assign Direct_Lookup_Table_n_D_t1_im[255] = t1_im_255; + assign Direct_Lookup_Table_n_D_t1_im[256] = t1_im_256; + assign Direct_Lookup_Table_n_D_t1_im[257] = t1_im_257; + assign Direct_Lookup_Table_n_D_t1_im[258] = t1_im_258; + assign Direct_Lookup_Table_n_D_t1_im[259] = t1_im_259; + assign Direct_Lookup_Table_n_D_t1_im[260] = t1_im_260; + assign Direct_Lookup_Table_n_D_t1_im[261] = t1_im_261; + assign Direct_Lookup_Table_n_D_t1_im[262] = t1_im_262; + assign Direct_Lookup_Table_n_D_t1_im[263] = t1_im_263; + assign Direct_Lookup_Table_n_D_t1_im[264] = t1_im_264; + assign Direct_Lookup_Table_n_D_t1_im[265] = t1_im_265; + assign Direct_Lookup_Table_n_D_t1_im[266] = t1_im_266; + assign Direct_Lookup_Table_n_D_t1_im[267] = t1_im_267; + assign Direct_Lookup_Table_n_D_t1_im[268] = t1_im_268; + assign Direct_Lookup_Table_n_D_t1_im[269] = t1_im_269; + assign Direct_Lookup_Table_n_D_t1_im[270] = t1_im_270; + assign Direct_Lookup_Table_n_D_t1_im[271] = t1_im_271; + assign Direct_Lookup_Table_n_D_t1_im[272] = t1_im_272; + assign Direct_Lookup_Table_n_D_t1_im[273] = t1_im_273; + assign Direct_Lookup_Table_n_D_t1_im[274] = t1_im_274; + assign Direct_Lookup_Table_n_D_t1_im[275] = t1_im_275; + assign Direct_Lookup_Table_n_D_t1_im[276] = t1_im_276; + assign Direct_Lookup_Table_n_D_t1_im[277] = t1_im_277; + assign Direct_Lookup_Table_n_D_t1_im[278] = t1_im_278; + assign Direct_Lookup_Table_n_D_t1_im[279] = t1_im_279; + assign Direct_Lookup_Table_n_D_t1_im[280] = t1_im_280; + assign Direct_Lookup_Table_n_D_t1_im[281] = t1_im_281; + assign Direct_Lookup_Table_n_D_t1_im[282] = t1_im_282; + assign Direct_Lookup_Table_n_D_t1_im[283] = t1_im_283; + assign Direct_Lookup_Table_n_D_t1_im[284] = t1_im_284; + assign Direct_Lookup_Table_n_D_t1_im[285] = t1_im_285; + assign Direct_Lookup_Table_n_D_t1_im[286] = t1_im_286; + assign Direct_Lookup_Table_n_D_t1_im[287] = t1_im_287; + assign Direct_Lookup_Table_n_D_t1_im[288] = t1_im_288; + assign Direct_Lookup_Table_n_D_t1_im[289] = t1_im_289; + assign Direct_Lookup_Table_n_D_t1_im[290] = t1_im_290; + assign Direct_Lookup_Table_n_D_t1_im[291] = t1_im_291; + assign Direct_Lookup_Table_n_D_t1_im[292] = t1_im_292; + assign Direct_Lookup_Table_n_D_t1_im[293] = t1_im_293; + assign Direct_Lookup_Table_n_D_t1_im[294] = t1_im_294; + assign Direct_Lookup_Table_n_D_t1_im[295] = t1_im_295; + assign Direct_Lookup_Table_n_D_t1_im[296] = t1_im_296; + assign Direct_Lookup_Table_n_D_t1_im[297] = t1_im_297; + assign Direct_Lookup_Table_n_D_t1_im[298] = t1_im_298; + assign Direct_Lookup_Table_n_D_t1_im[299] = t1_im_299; + assign Direct_Lookup_Table_n_D_t1_im[300] = t1_im_300; + assign Direct_Lookup_Table_n_D_t1_im[301] = t1_im_301; + assign Direct_Lookup_Table_n_D_t1_im[302] = t1_im_302; + assign Direct_Lookup_Table_n_D_t1_im[303] = t1_im_303; + assign Direct_Lookup_Table_n_D_t1_im[304] = t1_im_304; + assign Direct_Lookup_Table_n_D_t1_im[305] = t1_im_305; + assign Direct_Lookup_Table_n_D_t1_im[306] = t1_im_306; + assign Direct_Lookup_Table_n_D_t1_im[307] = t1_im_307; + assign Direct_Lookup_Table_n_D_t1_im[308] = t1_im_308; + assign Direct_Lookup_Table_n_D_t1_im[309] = t1_im_309; + assign Direct_Lookup_Table_n_D_t1_im[310] = t1_im_310; + assign Direct_Lookup_Table_n_D_t1_im[311] = t1_im_311; + assign Direct_Lookup_Table_n_D_t1_im[312] = t1_im_312; + assign Direct_Lookup_Table_n_D_t1_im[313] = t1_im_313; + assign Direct_Lookup_Table_n_D_t1_im[314] = t1_im_314; + assign Direct_Lookup_Table_n_D_t1_im[315] = t1_im_315; + assign Direct_Lookup_Table_n_D_t1_im[316] = t1_im_316; + assign Direct_Lookup_Table_n_D_t1_im[317] = t1_im_317; + assign Direct_Lookup_Table_n_D_t1_im[318] = t1_im_318; + assign Direct_Lookup_Table_n_D_t1_im[319] = t1_im_319; + assign Direct_Lookup_Table_n_D_t1_im[320] = t1_im_320; + assign Direct_Lookup_Table_n_D_t1_im[321] = t1_im_321; + assign Direct_Lookup_Table_n_D_t1_im[322] = t1_im_322; + assign Direct_Lookup_Table_n_D_t1_im[323] = t1_im_323; + assign Direct_Lookup_Table_n_D_t1_im[324] = t1_im_324; + assign Direct_Lookup_Table_n_D_t1_im[325] = t1_im_325; + assign Direct_Lookup_Table_n_D_t1_im[326] = t1_im_326; + assign Direct_Lookup_Table_n_D_t1_im[327] = t1_im_327; + assign Direct_Lookup_Table_n_D_t1_im[328] = t1_im_328; + assign Direct_Lookup_Table_n_D_t1_im[329] = t1_im_329; + assign Direct_Lookup_Table_n_D_t1_im[330] = t1_im_330; + assign Direct_Lookup_Table_n_D_t1_im[331] = t1_im_331; + assign Direct_Lookup_Table_n_D_t1_im[332] = t1_im_332; + assign Direct_Lookup_Table_n_D_t1_im[333] = t1_im_333; + assign Direct_Lookup_Table_n_D_t1_im[334] = t1_im_334; + assign Direct_Lookup_Table_n_D_t1_im[335] = t1_im_335; + assign Direct_Lookup_Table_n_D_t1_im[336] = t1_im_336; + assign Direct_Lookup_Table_n_D_t1_im[337] = t1_im_337; + assign Direct_Lookup_Table_n_D_t1_im[338] = t1_im_338; + assign Direct_Lookup_Table_n_D_t1_im[339] = t1_im_339; + assign Direct_Lookup_Table_n_D_t1_im[340] = t1_im_340; + assign Direct_Lookup_Table_n_D_t1_im[341] = t1_im_341; + assign Direct_Lookup_Table_n_D_t1_im[342] = t1_im_342; + assign Direct_Lookup_Table_n_D_t1_im[343] = t1_im_343; + assign Direct_Lookup_Table_n_D_t1_im[344] = t1_im_344; + assign Direct_Lookup_Table_n_D_t1_im[345] = t1_im_345; + assign Direct_Lookup_Table_n_D_t1_im[346] = t1_im_346; + assign Direct_Lookup_Table_n_D_t1_im[347] = t1_im_347; + assign Direct_Lookup_Table_n_D_t1_im[348] = t1_im_348; + assign Direct_Lookup_Table_n_D_t1_im[349] = t1_im_349; + assign Direct_Lookup_Table_n_D_t1_im[350] = t1_im_350; + assign Direct_Lookup_Table_n_D_t1_im[351] = t1_im_351; + assign Direct_Lookup_Table_n_D_t1_im[352] = t1_im_352; + assign Direct_Lookup_Table_n_D_t1_im[353] = t1_im_353; + assign Direct_Lookup_Table_n_D_t1_im[354] = t1_im_354; + assign Direct_Lookup_Table_n_D_t1_im[355] = t1_im_355; + assign Direct_Lookup_Table_n_D_t1_im[356] = t1_im_356; + assign Direct_Lookup_Table_n_D_t1_im[357] = t1_im_357; + assign Direct_Lookup_Table_n_D_t1_im[358] = t1_im_358; + assign Direct_Lookup_Table_n_D_t1_im[359] = t1_im_359; + assign Direct_Lookup_Table_n_D_t1_im[360] = t1_im_360; + assign Direct_Lookup_Table_n_D_t1_im[361] = t1_im_361; + assign Direct_Lookup_Table_n_D_t1_im[362] = t1_im_362; + assign Direct_Lookup_Table_n_D_t1_im[363] = t1_im_363; + assign Direct_Lookup_Table_n_D_t1_im[364] = t1_im_364; + assign Direct_Lookup_Table_n_D_t1_im[365] = t1_im_365; + assign Direct_Lookup_Table_n_D_t1_im[366] = t1_im_366; + assign Direct_Lookup_Table_n_D_t1_im[367] = t1_im_367; + assign Direct_Lookup_Table_n_D_t1_im[368] = t1_im_368; + assign Direct_Lookup_Table_n_D_t1_im[369] = t1_im_369; + assign Direct_Lookup_Table_n_D_t1_im[370] = t1_im_370; + assign Direct_Lookup_Table_n_D_t1_im[371] = t1_im_371; + assign Direct_Lookup_Table_n_D_t1_im[372] = t1_im_372; + assign Direct_Lookup_Table_n_D_t1_im[373] = t1_im_373; + assign Direct_Lookup_Table_n_D_t1_im[374] = t1_im_374; + assign Direct_Lookup_Table_n_D_t1_im[375] = t1_im_375; + assign Direct_Lookup_Table_n_D_t1_im[376] = t1_im_376; + assign Direct_Lookup_Table_n_D_t1_im[377] = t1_im_377; + assign Direct_Lookup_Table_n_D_t1_im[378] = t1_im_378; + assign Direct_Lookup_Table_n_D_t1_im[379] = t1_im_379; + assign Direct_Lookup_Table_n_D_t1_im[380] = t1_im_380; + assign Direct_Lookup_Table_n_D_t1_im[381] = t1_im_381; + assign Direct_Lookup_Table_n_D_t1_im[382] = t1_im_382; + assign Direct_Lookup_Table_n_D_t1_im[383] = t1_im_383; + assign Direct_Lookup_Table_n_D_t1_im[384] = t1_im_384; + assign Direct_Lookup_Table_n_D_t1_im[385] = t1_im_385; + assign Direct_Lookup_Table_n_D_t1_im[386] = t1_im_386; + assign Direct_Lookup_Table_n_D_t1_im[387] = t1_im_387; + assign Direct_Lookup_Table_n_D_t1_im[388] = t1_im_388; + assign Direct_Lookup_Table_n_D_t1_im[389] = t1_im_389; + assign Direct_Lookup_Table_n_D_t1_im[390] = t1_im_390; + assign Direct_Lookup_Table_n_D_t1_im[391] = t1_im_391; + assign Direct_Lookup_Table_n_D_t1_im[392] = t1_im_392; + assign Direct_Lookup_Table_n_D_t1_im[393] = t1_im_393; + assign Direct_Lookup_Table_n_D_t1_im[394] = t1_im_394; + assign Direct_Lookup_Table_n_D_t1_im[395] = t1_im_395; + assign Direct_Lookup_Table_n_D_t1_im[396] = t1_im_396; + assign Direct_Lookup_Table_n_D_t1_im[397] = t1_im_397; + assign Direct_Lookup_Table_n_D_t1_im[398] = t1_im_398; + assign Direct_Lookup_Table_n_D_t1_im[399] = t1_im_399; + assign Direct_Lookup_Table_n_D_t1_im[400] = t1_im_400; + assign Direct_Lookup_Table_n_D_t1_im[401] = t1_im_401; + assign Direct_Lookup_Table_n_D_t1_im[402] = t1_im_402; + assign Direct_Lookup_Table_n_D_t1_im[403] = t1_im_403; + assign Direct_Lookup_Table_n_D_t1_im[404] = t1_im_404; + assign Direct_Lookup_Table_n_D_t1_im[405] = t1_im_405; + assign Direct_Lookup_Table_n_D_t1_im[406] = t1_im_406; + assign Direct_Lookup_Table_n_D_t1_im[407] = t1_im_407; + assign Direct_Lookup_Table_n_D_t1_im[408] = t1_im_408; + assign Direct_Lookup_Table_n_D_t1_im[409] = t1_im_409; + assign Direct_Lookup_Table_n_D_t1_im[410] = t1_im_410; + assign Direct_Lookup_Table_n_D_t1_im[411] = t1_im_411; + assign Direct_Lookup_Table_n_D_t1_im[412] = t1_im_412; + assign Direct_Lookup_Table_n_D_t1_im[413] = t1_im_413; + assign Direct_Lookup_Table_n_D_t1_im[414] = t1_im_414; + assign Direct_Lookup_Table_n_D_t1_im[415] = t1_im_415; + assign Direct_Lookup_Table_n_D_t1_im[416] = t1_im_416; + assign Direct_Lookup_Table_n_D_t1_im[417] = t1_im_417; + assign Direct_Lookup_Table_n_D_t1_im[418] = t1_im_418; + assign Direct_Lookup_Table_n_D_t1_im[419] = t1_im_419; + assign Direct_Lookup_Table_n_D_t1_im[420] = t1_im_420; + assign Direct_Lookup_Table_n_D_t1_im[421] = t1_im_421; + assign Direct_Lookup_Table_n_D_t1_im[422] = t1_im_422; + assign Direct_Lookup_Table_n_D_t1_im[423] = t1_im_423; + assign Direct_Lookup_Table_n_D_t1_im[424] = t1_im_424; + assign Direct_Lookup_Table_n_D_t1_im[425] = t1_im_425; + assign Direct_Lookup_Table_n_D_t1_im[426] = t1_im_426; + assign Direct_Lookup_Table_n_D_t1_im[427] = t1_im_427; + assign Direct_Lookup_Table_n_D_t1_im[428] = t1_im_428; + assign Direct_Lookup_Table_n_D_t1_im[429] = t1_im_429; + assign Direct_Lookup_Table_n_D_t1_im[430] = t1_im_430; + assign Direct_Lookup_Table_n_D_t1_im[431] = t1_im_431; + assign Direct_Lookup_Table_n_D_t1_im[432] = t1_im_432; + assign Direct_Lookup_Table_n_D_t1_im[433] = t1_im_433; + assign Direct_Lookup_Table_n_D_t1_im[434] = t1_im_434; + assign Direct_Lookup_Table_n_D_t1_im[435] = t1_im_435; + assign Direct_Lookup_Table_n_D_t1_im[436] = t1_im_436; + assign Direct_Lookup_Table_n_D_t1_im[437] = t1_im_437; + assign Direct_Lookup_Table_n_D_t1_im[438] = t1_im_438; + assign Direct_Lookup_Table_n_D_t1_im[439] = t1_im_439; + assign Direct_Lookup_Table_n_D_t1_im[440] = t1_im_440; + assign Direct_Lookup_Table_n_D_t1_im[441] = t1_im_441; + assign Direct_Lookup_Table_n_D_t1_im[442] = t1_im_442; + assign Direct_Lookup_Table_n_D_t1_im[443] = t1_im_443; + assign Direct_Lookup_Table_n_D_t1_im[444] = t1_im_444; + assign Direct_Lookup_Table_n_D_t1_im[445] = t1_im_445; + assign Direct_Lookup_Table_n_D_t1_im[446] = t1_im_446; + assign Direct_Lookup_Table_n_D_t1_im[447] = t1_im_447; + assign Direct_Lookup_Table_n_D_t1_im[448] = t1_im_448; + assign Direct_Lookup_Table_n_D_t1_im[449] = t1_im_449; + assign Direct_Lookup_Table_n_D_t1_im[450] = t1_im_450; + assign Direct_Lookup_Table_n_D_t1_im[451] = t1_im_451; + assign Direct_Lookup_Table_n_D_t1_im[452] = t1_im_452; + assign Direct_Lookup_Table_n_D_t1_im[453] = t1_im_453; + assign Direct_Lookup_Table_n_D_t1_im[454] = t1_im_454; + assign Direct_Lookup_Table_n_D_t1_im[455] = t1_im_455; + assign Direct_Lookup_Table_n_D_t1_im[456] = t1_im_456; + assign Direct_Lookup_Table_n_D_t1_im[457] = t1_im_457; + assign Direct_Lookup_Table_n_D_t1_im[458] = t1_im_458; + assign Direct_Lookup_Table_n_D_t1_im[459] = t1_im_459; + assign Direct_Lookup_Table_n_D_t1_im[460] = t1_im_460; + assign Direct_Lookup_Table_n_D_t1_im[461] = t1_im_461; + assign Direct_Lookup_Table_n_D_t1_im[462] = t1_im_462; + assign Direct_Lookup_Table_n_D_t1_im[463] = t1_im_463; + assign Direct_Lookup_Table_n_D_t1_im[464] = t1_im_464; + assign Direct_Lookup_Table_n_D_t1_im[465] = t1_im_465; + assign Direct_Lookup_Table_n_D_t1_im[466] = t1_im_466; + assign Direct_Lookup_Table_n_D_t1_im[467] = t1_im_467; + assign Direct_Lookup_Table_n_D_t1_im[468] = t1_im_468; + assign Direct_Lookup_Table_n_D_t1_im[469] = t1_im_469; + assign Direct_Lookup_Table_n_D_t1_im[470] = t1_im_470; + assign Direct_Lookup_Table_n_D_t1_im[471] = t1_im_471; + assign Direct_Lookup_Table_n_D_t1_im[472] = t1_im_472; + assign Direct_Lookup_Table_n_D_t1_im[473] = t1_im_473; + assign Direct_Lookup_Table_n_D_t1_im[474] = t1_im_474; + assign Direct_Lookup_Table_n_D_t1_im[475] = t1_im_475; + assign Direct_Lookup_Table_n_D_t1_im[476] = t1_im_476; + assign Direct_Lookup_Table_n_D_t1_im[477] = t1_im_477; + assign Direct_Lookup_Table_n_D_t1_im[478] = t1_im_478; + assign Direct_Lookup_Table_n_D_t1_im[479] = t1_im_479; + assign Direct_Lookup_Table_n_D_t1_im[480] = t1_im_480; + assign Direct_Lookup_Table_n_D_t1_im[481] = t1_im_481; + assign Direct_Lookup_Table_n_D_t1_im[482] = t1_im_482; + assign Direct_Lookup_Table_n_D_t1_im[483] = t1_im_483; + assign Direct_Lookup_Table_n_D_t1_im[484] = t1_im_484; + assign Direct_Lookup_Table_n_D_t1_im[485] = t1_im_485; + assign Direct_Lookup_Table_n_D_t1_im[486] = t1_im_486; + assign Direct_Lookup_Table_n_D_t1_im[487] = t1_im_487; + assign Direct_Lookup_Table_n_D_t1_im[488] = t1_im_488; + assign Direct_Lookup_Table_n_D_t1_im[489] = t1_im_489; + assign Direct_Lookup_Table_n_D_t1_im[490] = t1_im_490; + assign Direct_Lookup_Table_n_D_t1_im[491] = t1_im_491; + assign Direct_Lookup_Table_n_D_t1_im[492] = t1_im_492; + assign Direct_Lookup_Table_n_D_t1_im[493] = t1_im_493; + assign Direct_Lookup_Table_n_D_t1_im[494] = t1_im_494; + assign Direct_Lookup_Table_n_D_t1_im[495] = t1_im_495; + assign Direct_Lookup_Table_n_D_t1_im[496] = t1_im_496; + assign Direct_Lookup_Table_n_D_t1_im[497] = t1_im_497; + assign Direct_Lookup_Table_n_D_t1_im[498] = t1_im_498; + assign Direct_Lookup_Table_n_D_t1_im[499] = t1_im_499; + assign Direct_Lookup_Table_n_D_t1_im[500] = t1_im_500; + assign Direct_Lookup_Table_n_D_t1_im[501] = t1_im_501; + assign Direct_Lookup_Table_n_D_t1_im[502] = t1_im_502; + assign Direct_Lookup_Table_n_D_t1_im[503] = t1_im_503; + assign Direct_Lookup_Table_n_D_t1_im[504] = t1_im_504; + assign Direct_Lookup_Table_n_D_t1_im[505] = t1_im_505; + assign Direct_Lookup_Table_n_D_t1_im[506] = t1_im_506; + assign Direct_Lookup_Table_n_D_t1_im[507] = t1_im_507; + assign Direct_Lookup_Table_n_D_t1_im[508] = t1_im_508; + assign Direct_Lookup_Table_n_D_t1_im[509] = t1_im_509; + assign Direct_Lookup_Table_n_D_t1_im[510] = t1_im_510; + assign Direct_Lookup_Table_n_D_t1_im[511] = t1_im_511; + assign Direct_Lookup_Table_n_D_out1_re = Direct_Lookup_Table_n_D_t1_re[Data_Type_Conversion1_out1]; + assign Direct_Lookup_Table_n_D_out1_im = Direct_Lookup_Table_n_D_t1_im[Data_Type_Conversion1_out1]; + + + + // /Mark_Extract_Bits1 + velocityControlHdl_Mark_Extract_Bits1 u_Mark_Extract_Bits1 (.In1(elec_pos_scaled), // ufix18 + .Out1(y_1) // ufix9 + ); + + // /Data Type Conversion2 + assign Data_Type_Conversion2_out1 = y_1; + + + + // /Direct Lookup Table (n-D)1 + assign Direct_Lookup_Table_n_D_1_t1_re[0] = t1_re_0_2; + assign Direct_Lookup_Table_n_D_1_t1_re[1] = t1_re_1_2; + assign Direct_Lookup_Table_n_D_1_t1_re[2] = t1_re_2_2; + assign Direct_Lookup_Table_n_D_1_t1_re[3] = t1_re_3_2; + assign Direct_Lookup_Table_n_D_1_t1_re[4] = t1_re_4_2; + assign Direct_Lookup_Table_n_D_1_t1_re[5] = t1_re_5_2; + assign Direct_Lookup_Table_n_D_1_t1_re[6] = t1_re_6_2; + assign Direct_Lookup_Table_n_D_1_t1_re[7] = t1_re_7_2; + assign Direct_Lookup_Table_n_D_1_t1_re[8] = t1_re_8_2; + assign Direct_Lookup_Table_n_D_1_t1_re[9] = t1_re_9_2; + assign Direct_Lookup_Table_n_D_1_t1_re[10] = t1_re_10_2; + assign Direct_Lookup_Table_n_D_1_t1_re[11] = t1_re_11_2; + assign Direct_Lookup_Table_n_D_1_t1_re[12] = t1_re_12_2; + assign Direct_Lookup_Table_n_D_1_t1_re[13] = t1_re_13_2; + assign Direct_Lookup_Table_n_D_1_t1_re[14] = t1_re_14_2; + assign Direct_Lookup_Table_n_D_1_t1_re[15] = t1_re_15_2; + assign Direct_Lookup_Table_n_D_1_t1_re[16] = t1_re_16_2; + assign Direct_Lookup_Table_n_D_1_t1_re[17] = t1_re_17_2; + assign Direct_Lookup_Table_n_D_1_t1_re[18] = t1_re_18_2; + assign Direct_Lookup_Table_n_D_1_t1_re[19] = t1_re_19_2; + assign Direct_Lookup_Table_n_D_1_t1_re[20] = t1_re_20_2; + assign Direct_Lookup_Table_n_D_1_t1_re[21] = t1_re_21_2; + assign Direct_Lookup_Table_n_D_1_t1_re[22] = t1_re_22_2; + assign Direct_Lookup_Table_n_D_1_t1_re[23] = t1_re_23_2; + assign Direct_Lookup_Table_n_D_1_t1_re[24] = t1_re_24_2; + assign Direct_Lookup_Table_n_D_1_t1_re[25] = t1_re_25_2; + assign Direct_Lookup_Table_n_D_1_t1_re[26] = t1_re_26_2; + assign Direct_Lookup_Table_n_D_1_t1_re[27] = t1_re_27_2; + assign Direct_Lookup_Table_n_D_1_t1_re[28] = t1_re_28_2; + assign Direct_Lookup_Table_n_D_1_t1_re[29] = t1_re_29_2; + assign Direct_Lookup_Table_n_D_1_t1_re[30] = t1_re_30_2; + assign Direct_Lookup_Table_n_D_1_t1_re[31] = t1_re_31_2; + assign Direct_Lookup_Table_n_D_1_t1_re[32] = t1_re_32_2; + assign Direct_Lookup_Table_n_D_1_t1_re[33] = t1_re_33_2; + assign Direct_Lookup_Table_n_D_1_t1_re[34] = t1_re_34_2; + assign Direct_Lookup_Table_n_D_1_t1_re[35] = t1_re_35_2; + assign Direct_Lookup_Table_n_D_1_t1_re[36] = t1_re_36_2; + assign Direct_Lookup_Table_n_D_1_t1_re[37] = t1_re_37_2; + assign Direct_Lookup_Table_n_D_1_t1_re[38] = t1_re_38_2; + assign Direct_Lookup_Table_n_D_1_t1_re[39] = t1_re_39_2; + assign Direct_Lookup_Table_n_D_1_t1_re[40] = t1_re_40_2; + assign Direct_Lookup_Table_n_D_1_t1_re[41] = t1_re_41_2; + assign Direct_Lookup_Table_n_D_1_t1_re[42] = t1_re_42_2; + assign Direct_Lookup_Table_n_D_1_t1_re[43] = t1_re_43_2; + assign Direct_Lookup_Table_n_D_1_t1_re[44] = t1_re_44_2; + assign Direct_Lookup_Table_n_D_1_t1_re[45] = t1_re_45_2; + assign Direct_Lookup_Table_n_D_1_t1_re[46] = t1_re_46_2; + assign Direct_Lookup_Table_n_D_1_t1_re[47] = t1_re_47_2; + assign Direct_Lookup_Table_n_D_1_t1_re[48] = t1_re_48_2; + assign Direct_Lookup_Table_n_D_1_t1_re[49] = t1_re_49_2; + assign Direct_Lookup_Table_n_D_1_t1_re[50] = t1_re_50_2; + assign Direct_Lookup_Table_n_D_1_t1_re[51] = t1_re_51_2; + assign Direct_Lookup_Table_n_D_1_t1_re[52] = t1_re_52_2; + assign Direct_Lookup_Table_n_D_1_t1_re[53] = t1_re_53_2; + assign Direct_Lookup_Table_n_D_1_t1_re[54] = t1_re_54_2; + assign Direct_Lookup_Table_n_D_1_t1_re[55] = t1_re_55_2; + assign Direct_Lookup_Table_n_D_1_t1_re[56] = t1_re_56_2; + assign Direct_Lookup_Table_n_D_1_t1_re[57] = t1_re_57_2; + assign Direct_Lookup_Table_n_D_1_t1_re[58] = t1_re_58_2; + assign Direct_Lookup_Table_n_D_1_t1_re[59] = t1_re_59_2; + assign Direct_Lookup_Table_n_D_1_t1_re[60] = t1_re_60_2; + assign Direct_Lookup_Table_n_D_1_t1_re[61] = t1_re_61_2; + assign Direct_Lookup_Table_n_D_1_t1_re[62] = t1_re_62_2; + assign Direct_Lookup_Table_n_D_1_t1_re[63] = t1_re_63_2; + assign Direct_Lookup_Table_n_D_1_t1_re[64] = t1_re_64_2; + assign Direct_Lookup_Table_n_D_1_t1_re[65] = t1_re_65_2; + assign Direct_Lookup_Table_n_D_1_t1_re[66] = t1_re_66_2; + assign Direct_Lookup_Table_n_D_1_t1_re[67] = t1_re_67_2; + assign Direct_Lookup_Table_n_D_1_t1_re[68] = t1_re_68_2; + assign Direct_Lookup_Table_n_D_1_t1_re[69] = t1_re_69_2; + assign Direct_Lookup_Table_n_D_1_t1_re[70] = t1_re_70_2; + assign Direct_Lookup_Table_n_D_1_t1_re[71] = t1_re_71_2; + assign Direct_Lookup_Table_n_D_1_t1_re[72] = t1_re_72_2; + assign Direct_Lookup_Table_n_D_1_t1_re[73] = t1_re_73_2; + assign Direct_Lookup_Table_n_D_1_t1_re[74] = t1_re_74_2; + assign Direct_Lookup_Table_n_D_1_t1_re[75] = t1_re_75_2; + assign Direct_Lookup_Table_n_D_1_t1_re[76] = t1_re_76_2; + assign Direct_Lookup_Table_n_D_1_t1_re[77] = t1_re_77_2; + assign Direct_Lookup_Table_n_D_1_t1_re[78] = t1_re_78_2; + assign Direct_Lookup_Table_n_D_1_t1_re[79] = t1_re_79_2; + assign Direct_Lookup_Table_n_D_1_t1_re[80] = t1_re_80_2; + assign Direct_Lookup_Table_n_D_1_t1_re[81] = t1_re_81_2; + assign Direct_Lookup_Table_n_D_1_t1_re[82] = t1_re_82_2; + assign Direct_Lookup_Table_n_D_1_t1_re[83] = t1_re_83_2; + assign Direct_Lookup_Table_n_D_1_t1_re[84] = t1_re_84_2; + assign Direct_Lookup_Table_n_D_1_t1_re[85] = t1_re_85_2; + assign Direct_Lookup_Table_n_D_1_t1_re[86] = t1_re_86_2; + assign Direct_Lookup_Table_n_D_1_t1_re[87] = t1_re_87_2; + assign Direct_Lookup_Table_n_D_1_t1_re[88] = t1_re_88_2; + assign Direct_Lookup_Table_n_D_1_t1_re[89] = t1_re_89_2; + assign Direct_Lookup_Table_n_D_1_t1_re[90] = t1_re_90_2; + assign Direct_Lookup_Table_n_D_1_t1_re[91] = t1_re_91_2; + assign Direct_Lookup_Table_n_D_1_t1_re[92] = t1_re_92_2; + assign Direct_Lookup_Table_n_D_1_t1_re[93] = t1_re_93_2; + assign Direct_Lookup_Table_n_D_1_t1_re[94] = t1_re_94_2; + assign Direct_Lookup_Table_n_D_1_t1_re[95] = t1_re_95_2; + assign Direct_Lookup_Table_n_D_1_t1_re[96] = t1_re_96_2; + assign Direct_Lookup_Table_n_D_1_t1_re[97] = t1_re_97_2; + assign Direct_Lookup_Table_n_D_1_t1_re[98] = t1_re_98_2; + assign Direct_Lookup_Table_n_D_1_t1_re[99] = t1_re_99_2; + assign Direct_Lookup_Table_n_D_1_t1_re[100] = t1_re_100_2; + assign Direct_Lookup_Table_n_D_1_t1_re[101] = t1_re_101_2; + assign Direct_Lookup_Table_n_D_1_t1_re[102] = t1_re_102_2; + assign Direct_Lookup_Table_n_D_1_t1_re[103] = t1_re_103_2; + assign Direct_Lookup_Table_n_D_1_t1_re[104] = t1_re_104_2; + assign Direct_Lookup_Table_n_D_1_t1_re[105] = t1_re_105_2; + assign Direct_Lookup_Table_n_D_1_t1_re[106] = t1_re_106_2; + assign Direct_Lookup_Table_n_D_1_t1_re[107] = t1_re_107_2; + assign Direct_Lookup_Table_n_D_1_t1_re[108] = t1_re_108_2; + assign Direct_Lookup_Table_n_D_1_t1_re[109] = t1_re_109_2; + assign Direct_Lookup_Table_n_D_1_t1_re[110] = t1_re_110_2; + assign Direct_Lookup_Table_n_D_1_t1_re[111] = t1_re_111_2; + assign Direct_Lookup_Table_n_D_1_t1_re[112] = t1_re_112_2; + assign Direct_Lookup_Table_n_D_1_t1_re[113] = t1_re_113_2; + assign Direct_Lookup_Table_n_D_1_t1_re[114] = t1_re_114_2; + assign Direct_Lookup_Table_n_D_1_t1_re[115] = t1_re_115_2; + assign Direct_Lookup_Table_n_D_1_t1_re[116] = t1_re_116_2; + assign Direct_Lookup_Table_n_D_1_t1_re[117] = t1_re_117_2; + assign Direct_Lookup_Table_n_D_1_t1_re[118] = t1_re_118_2; + assign Direct_Lookup_Table_n_D_1_t1_re[119] = t1_re_119_2; + assign Direct_Lookup_Table_n_D_1_t1_re[120] = t1_re_120_2; + assign Direct_Lookup_Table_n_D_1_t1_re[121] = t1_re_121_2; + assign Direct_Lookup_Table_n_D_1_t1_re[122] = t1_re_122_2; + assign Direct_Lookup_Table_n_D_1_t1_re[123] = t1_re_123_2; + assign Direct_Lookup_Table_n_D_1_t1_re[124] = t1_re_124_2; + assign Direct_Lookup_Table_n_D_1_t1_re[125] = t1_re_125_2; + assign Direct_Lookup_Table_n_D_1_t1_re[126] = t1_re_126_2; + assign Direct_Lookup_Table_n_D_1_t1_re[127] = t1_re_127_2; + assign Direct_Lookup_Table_n_D_1_t1_re[128] = t1_re_128_2; + assign Direct_Lookup_Table_n_D_1_t1_re[129] = t1_re_129_2; + assign Direct_Lookup_Table_n_D_1_t1_re[130] = t1_re_130_2; + assign Direct_Lookup_Table_n_D_1_t1_re[131] = t1_re_131_2; + assign Direct_Lookup_Table_n_D_1_t1_re[132] = t1_re_132_2; + assign Direct_Lookup_Table_n_D_1_t1_re[133] = t1_re_133_2; + assign Direct_Lookup_Table_n_D_1_t1_re[134] = t1_re_134_2; + assign Direct_Lookup_Table_n_D_1_t1_re[135] = t1_re_135_2; + assign Direct_Lookup_Table_n_D_1_t1_re[136] = t1_re_136_2; + assign Direct_Lookup_Table_n_D_1_t1_re[137] = t1_re_137_2; + assign Direct_Lookup_Table_n_D_1_t1_re[138] = t1_re_138_2; + assign Direct_Lookup_Table_n_D_1_t1_re[139] = t1_re_139_2; + assign Direct_Lookup_Table_n_D_1_t1_re[140] = t1_re_140_2; + assign Direct_Lookup_Table_n_D_1_t1_re[141] = t1_re_141_2; + assign Direct_Lookup_Table_n_D_1_t1_re[142] = t1_re_142_2; + assign Direct_Lookup_Table_n_D_1_t1_re[143] = t1_re_143_2; + assign Direct_Lookup_Table_n_D_1_t1_re[144] = t1_re_144_2; + assign Direct_Lookup_Table_n_D_1_t1_re[145] = t1_re_145_2; + assign Direct_Lookup_Table_n_D_1_t1_re[146] = t1_re_146_2; + assign Direct_Lookup_Table_n_D_1_t1_re[147] = t1_re_147_2; + assign Direct_Lookup_Table_n_D_1_t1_re[148] = t1_re_148_2; + assign Direct_Lookup_Table_n_D_1_t1_re[149] = t1_re_149_2; + assign Direct_Lookup_Table_n_D_1_t1_re[150] = t1_re_150_2; + assign Direct_Lookup_Table_n_D_1_t1_re[151] = t1_re_151_2; + assign Direct_Lookup_Table_n_D_1_t1_re[152] = t1_re_152_2; + assign Direct_Lookup_Table_n_D_1_t1_re[153] = t1_re_153_2; + assign Direct_Lookup_Table_n_D_1_t1_re[154] = t1_re_154_2; + assign Direct_Lookup_Table_n_D_1_t1_re[155] = t1_re_155_2; + assign Direct_Lookup_Table_n_D_1_t1_re[156] = t1_re_156_2; + assign Direct_Lookup_Table_n_D_1_t1_re[157] = t1_re_157_2; + assign Direct_Lookup_Table_n_D_1_t1_re[158] = t1_re_158_2; + assign Direct_Lookup_Table_n_D_1_t1_re[159] = t1_re_159_2; + assign Direct_Lookup_Table_n_D_1_t1_re[160] = t1_re_160_2; + assign Direct_Lookup_Table_n_D_1_t1_re[161] = t1_re_161_2; + assign Direct_Lookup_Table_n_D_1_t1_re[162] = t1_re_162_2; + assign Direct_Lookup_Table_n_D_1_t1_re[163] = t1_re_163_2; + assign Direct_Lookup_Table_n_D_1_t1_re[164] = t1_re_164_2; + assign Direct_Lookup_Table_n_D_1_t1_re[165] = t1_re_165_2; + assign Direct_Lookup_Table_n_D_1_t1_re[166] = t1_re_166_2; + assign Direct_Lookup_Table_n_D_1_t1_re[167] = t1_re_167_2; + assign Direct_Lookup_Table_n_D_1_t1_re[168] = t1_re_168_2; + assign Direct_Lookup_Table_n_D_1_t1_re[169] = t1_re_169_2; + assign Direct_Lookup_Table_n_D_1_t1_re[170] = t1_re_170_2; + assign Direct_Lookup_Table_n_D_1_t1_re[171] = t1_re_171_2; + assign Direct_Lookup_Table_n_D_1_t1_re[172] = t1_re_172_2; + assign Direct_Lookup_Table_n_D_1_t1_re[173] = t1_re_173_2; + assign Direct_Lookup_Table_n_D_1_t1_re[174] = t1_re_174_2; + assign Direct_Lookup_Table_n_D_1_t1_re[175] = t1_re_175_2; + assign Direct_Lookup_Table_n_D_1_t1_re[176] = t1_re_176_2; + assign Direct_Lookup_Table_n_D_1_t1_re[177] = t1_re_177_2; + assign Direct_Lookup_Table_n_D_1_t1_re[178] = t1_re_178_2; + assign Direct_Lookup_Table_n_D_1_t1_re[179] = t1_re_179_2; + assign Direct_Lookup_Table_n_D_1_t1_re[180] = t1_re_180_2; + assign Direct_Lookup_Table_n_D_1_t1_re[181] = t1_re_181_2; + assign Direct_Lookup_Table_n_D_1_t1_re[182] = t1_re_182_2; + assign Direct_Lookup_Table_n_D_1_t1_re[183] = t1_re_183_2; + assign Direct_Lookup_Table_n_D_1_t1_re[184] = t1_re_184_2; + assign Direct_Lookup_Table_n_D_1_t1_re[185] = t1_re_185_2; + assign Direct_Lookup_Table_n_D_1_t1_re[186] = t1_re_186_2; + assign Direct_Lookup_Table_n_D_1_t1_re[187] = t1_re_187_2; + assign Direct_Lookup_Table_n_D_1_t1_re[188] = t1_re_188_2; + assign Direct_Lookup_Table_n_D_1_t1_re[189] = t1_re_189_2; + assign Direct_Lookup_Table_n_D_1_t1_re[190] = t1_re_190_2; + assign Direct_Lookup_Table_n_D_1_t1_re[191] = t1_re_191_2; + assign Direct_Lookup_Table_n_D_1_t1_re[192] = t1_re_192_2; + assign Direct_Lookup_Table_n_D_1_t1_re[193] = t1_re_193_2; + assign Direct_Lookup_Table_n_D_1_t1_re[194] = t1_re_194_2; + assign Direct_Lookup_Table_n_D_1_t1_re[195] = t1_re_195_2; + assign Direct_Lookup_Table_n_D_1_t1_re[196] = t1_re_196_2; + assign Direct_Lookup_Table_n_D_1_t1_re[197] = t1_re_197_2; + assign Direct_Lookup_Table_n_D_1_t1_re[198] = t1_re_198_2; + assign Direct_Lookup_Table_n_D_1_t1_re[199] = t1_re_199_2; + assign Direct_Lookup_Table_n_D_1_t1_re[200] = t1_re_200_2; + assign Direct_Lookup_Table_n_D_1_t1_re[201] = t1_re_201_2; + assign Direct_Lookup_Table_n_D_1_t1_re[202] = t1_re_202_2; + assign Direct_Lookup_Table_n_D_1_t1_re[203] = t1_re_203_2; + assign Direct_Lookup_Table_n_D_1_t1_re[204] = t1_re_204_2; + assign Direct_Lookup_Table_n_D_1_t1_re[205] = t1_re_205_2; + assign Direct_Lookup_Table_n_D_1_t1_re[206] = t1_re_206_2; + assign Direct_Lookup_Table_n_D_1_t1_re[207] = t1_re_207_2; + assign Direct_Lookup_Table_n_D_1_t1_re[208] = t1_re_208_2; + assign Direct_Lookup_Table_n_D_1_t1_re[209] = t1_re_209_2; + assign Direct_Lookup_Table_n_D_1_t1_re[210] = t1_re_210_2; + assign Direct_Lookup_Table_n_D_1_t1_re[211] = t1_re_211_2; + assign Direct_Lookup_Table_n_D_1_t1_re[212] = t1_re_212_2; + assign Direct_Lookup_Table_n_D_1_t1_re[213] = t1_re_213_2; + assign Direct_Lookup_Table_n_D_1_t1_re[214] = t1_re_214_2; + assign Direct_Lookup_Table_n_D_1_t1_re[215] = t1_re_215_2; + assign Direct_Lookup_Table_n_D_1_t1_re[216] = t1_re_216_2; + assign Direct_Lookup_Table_n_D_1_t1_re[217] = t1_re_217_2; + assign Direct_Lookup_Table_n_D_1_t1_re[218] = t1_re_218_2; + assign Direct_Lookup_Table_n_D_1_t1_re[219] = t1_re_219_2; + assign Direct_Lookup_Table_n_D_1_t1_re[220] = t1_re_220_2; + assign Direct_Lookup_Table_n_D_1_t1_re[221] = t1_re_221_2; + assign Direct_Lookup_Table_n_D_1_t1_re[222] = t1_re_222_2; + assign Direct_Lookup_Table_n_D_1_t1_re[223] = t1_re_223_2; + assign Direct_Lookup_Table_n_D_1_t1_re[224] = t1_re_224_2; + assign Direct_Lookup_Table_n_D_1_t1_re[225] = t1_re_225_2; + assign Direct_Lookup_Table_n_D_1_t1_re[226] = t1_re_226_2; + assign Direct_Lookup_Table_n_D_1_t1_re[227] = t1_re_227_2; + assign Direct_Lookup_Table_n_D_1_t1_re[228] = t1_re_228_2; + assign Direct_Lookup_Table_n_D_1_t1_re[229] = t1_re_229_2; + assign Direct_Lookup_Table_n_D_1_t1_re[230] = t1_re_230_2; + assign Direct_Lookup_Table_n_D_1_t1_re[231] = t1_re_231_2; + assign Direct_Lookup_Table_n_D_1_t1_re[232] = t1_re_232_2; + assign Direct_Lookup_Table_n_D_1_t1_re[233] = t1_re_233_2; + assign Direct_Lookup_Table_n_D_1_t1_re[234] = t1_re_234_2; + assign Direct_Lookup_Table_n_D_1_t1_re[235] = t1_re_235_2; + assign Direct_Lookup_Table_n_D_1_t1_re[236] = t1_re_236_2; + assign Direct_Lookup_Table_n_D_1_t1_re[237] = t1_re_237_2; + assign Direct_Lookup_Table_n_D_1_t1_re[238] = t1_re_238_2; + assign Direct_Lookup_Table_n_D_1_t1_re[239] = t1_re_239_2; + assign Direct_Lookup_Table_n_D_1_t1_re[240] = t1_re_240_2; + assign Direct_Lookup_Table_n_D_1_t1_re[241] = t1_re_241_2; + assign Direct_Lookup_Table_n_D_1_t1_re[242] = t1_re_242_2; + assign Direct_Lookup_Table_n_D_1_t1_re[243] = t1_re_243_2; + assign Direct_Lookup_Table_n_D_1_t1_re[244] = t1_re_244_2; + assign Direct_Lookup_Table_n_D_1_t1_re[245] = t1_re_245_2; + assign Direct_Lookup_Table_n_D_1_t1_re[246] = t1_re_246_2; + assign Direct_Lookup_Table_n_D_1_t1_re[247] = t1_re_247_2; + assign Direct_Lookup_Table_n_D_1_t1_re[248] = t1_re_248_2; + assign Direct_Lookup_Table_n_D_1_t1_re[249] = t1_re_249_2; + assign Direct_Lookup_Table_n_D_1_t1_re[250] = t1_re_250_2; + assign Direct_Lookup_Table_n_D_1_t1_re[251] = t1_re_251_2; + assign Direct_Lookup_Table_n_D_1_t1_re[252] = t1_re_252_2; + assign Direct_Lookup_Table_n_D_1_t1_re[253] = t1_re_253_2; + assign Direct_Lookup_Table_n_D_1_t1_re[254] = t1_re_254_2; + assign Direct_Lookup_Table_n_D_1_t1_re[255] = t1_re_255_2; + assign Direct_Lookup_Table_n_D_1_t1_re[256] = t1_re_256_2; + assign Direct_Lookup_Table_n_D_1_t1_re[257] = t1_re_257_2; + assign Direct_Lookup_Table_n_D_1_t1_re[258] = t1_re_258_2; + assign Direct_Lookup_Table_n_D_1_t1_re[259] = t1_re_259_2; + assign Direct_Lookup_Table_n_D_1_t1_re[260] = t1_re_260_2; + assign Direct_Lookup_Table_n_D_1_t1_re[261] = t1_re_261_2; + assign Direct_Lookup_Table_n_D_1_t1_re[262] = t1_re_262_2; + assign Direct_Lookup_Table_n_D_1_t1_re[263] = t1_re_263_2; + assign Direct_Lookup_Table_n_D_1_t1_re[264] = t1_re_264_2; + assign Direct_Lookup_Table_n_D_1_t1_re[265] = t1_re_265_2; + assign Direct_Lookup_Table_n_D_1_t1_re[266] = t1_re_266_2; + assign Direct_Lookup_Table_n_D_1_t1_re[267] = t1_re_267_2; + assign Direct_Lookup_Table_n_D_1_t1_re[268] = t1_re_268_2; + assign Direct_Lookup_Table_n_D_1_t1_re[269] = t1_re_269_2; + assign Direct_Lookup_Table_n_D_1_t1_re[270] = t1_re_270_2; + assign Direct_Lookup_Table_n_D_1_t1_re[271] = t1_re_271_2; + assign Direct_Lookup_Table_n_D_1_t1_re[272] = t1_re_272_2; + assign Direct_Lookup_Table_n_D_1_t1_re[273] = t1_re_273_2; + assign Direct_Lookup_Table_n_D_1_t1_re[274] = t1_re_274_2; + assign Direct_Lookup_Table_n_D_1_t1_re[275] = t1_re_275_2; + assign Direct_Lookup_Table_n_D_1_t1_re[276] = t1_re_276_2; + assign Direct_Lookup_Table_n_D_1_t1_re[277] = t1_re_277_2; + assign Direct_Lookup_Table_n_D_1_t1_re[278] = t1_re_278_2; + assign Direct_Lookup_Table_n_D_1_t1_re[279] = t1_re_279_2; + assign Direct_Lookup_Table_n_D_1_t1_re[280] = t1_re_280_2; + assign Direct_Lookup_Table_n_D_1_t1_re[281] = t1_re_281_2; + assign Direct_Lookup_Table_n_D_1_t1_re[282] = t1_re_282_2; + assign Direct_Lookup_Table_n_D_1_t1_re[283] = t1_re_283_2; + assign Direct_Lookup_Table_n_D_1_t1_re[284] = t1_re_284_2; + assign Direct_Lookup_Table_n_D_1_t1_re[285] = t1_re_285_2; + assign Direct_Lookup_Table_n_D_1_t1_re[286] = t1_re_286_2; + assign Direct_Lookup_Table_n_D_1_t1_re[287] = t1_re_287_2; + assign Direct_Lookup_Table_n_D_1_t1_re[288] = t1_re_288_2; + assign Direct_Lookup_Table_n_D_1_t1_re[289] = t1_re_289_2; + assign Direct_Lookup_Table_n_D_1_t1_re[290] = t1_re_290_2; + assign Direct_Lookup_Table_n_D_1_t1_re[291] = t1_re_291_2; + assign Direct_Lookup_Table_n_D_1_t1_re[292] = t1_re_292_2; + assign Direct_Lookup_Table_n_D_1_t1_re[293] = t1_re_293_2; + assign Direct_Lookup_Table_n_D_1_t1_re[294] = t1_re_294_2; + assign Direct_Lookup_Table_n_D_1_t1_re[295] = t1_re_295_2; + assign Direct_Lookup_Table_n_D_1_t1_re[296] = t1_re_296_2; + assign Direct_Lookup_Table_n_D_1_t1_re[297] = t1_re_297_2; + assign Direct_Lookup_Table_n_D_1_t1_re[298] = t1_re_298_2; + assign Direct_Lookup_Table_n_D_1_t1_re[299] = t1_re_299_2; + assign Direct_Lookup_Table_n_D_1_t1_re[300] = t1_re_300_2; + assign Direct_Lookup_Table_n_D_1_t1_re[301] = t1_re_301_2; + assign Direct_Lookup_Table_n_D_1_t1_re[302] = t1_re_302_2; + assign Direct_Lookup_Table_n_D_1_t1_re[303] = t1_re_303_2; + assign Direct_Lookup_Table_n_D_1_t1_re[304] = t1_re_304_2; + assign Direct_Lookup_Table_n_D_1_t1_re[305] = t1_re_305_2; + assign Direct_Lookup_Table_n_D_1_t1_re[306] = t1_re_306_2; + assign Direct_Lookup_Table_n_D_1_t1_re[307] = t1_re_307_2; + assign Direct_Lookup_Table_n_D_1_t1_re[308] = t1_re_308_2; + assign Direct_Lookup_Table_n_D_1_t1_re[309] = t1_re_309_2; + assign Direct_Lookup_Table_n_D_1_t1_re[310] = t1_re_310_2; + assign Direct_Lookup_Table_n_D_1_t1_re[311] = t1_re_311_2; + assign Direct_Lookup_Table_n_D_1_t1_re[312] = t1_re_312_2; + assign Direct_Lookup_Table_n_D_1_t1_re[313] = t1_re_313_2; + assign Direct_Lookup_Table_n_D_1_t1_re[314] = t1_re_314_2; + assign Direct_Lookup_Table_n_D_1_t1_re[315] = t1_re_315_2; + assign Direct_Lookup_Table_n_D_1_t1_re[316] = t1_re_316_2; + assign Direct_Lookup_Table_n_D_1_t1_re[317] = t1_re_317_2; + assign Direct_Lookup_Table_n_D_1_t1_re[318] = t1_re_318_2; + assign Direct_Lookup_Table_n_D_1_t1_re[319] = t1_re_319_2; + assign Direct_Lookup_Table_n_D_1_t1_re[320] = t1_re_320_2; + assign Direct_Lookup_Table_n_D_1_t1_re[321] = t1_re_321_2; + assign Direct_Lookup_Table_n_D_1_t1_re[322] = t1_re_322_2; + assign Direct_Lookup_Table_n_D_1_t1_re[323] = t1_re_323_2; + assign Direct_Lookup_Table_n_D_1_t1_re[324] = t1_re_324_2; + assign Direct_Lookup_Table_n_D_1_t1_re[325] = t1_re_325_2; + assign Direct_Lookup_Table_n_D_1_t1_re[326] = t1_re_326_2; + assign Direct_Lookup_Table_n_D_1_t1_re[327] = t1_re_327_2; + assign Direct_Lookup_Table_n_D_1_t1_re[328] = t1_re_328_2; + assign Direct_Lookup_Table_n_D_1_t1_re[329] = t1_re_329_2; + assign Direct_Lookup_Table_n_D_1_t1_re[330] = t1_re_330_2; + assign Direct_Lookup_Table_n_D_1_t1_re[331] = t1_re_331_2; + assign Direct_Lookup_Table_n_D_1_t1_re[332] = t1_re_332_2; + assign Direct_Lookup_Table_n_D_1_t1_re[333] = t1_re_333_2; + assign Direct_Lookup_Table_n_D_1_t1_re[334] = t1_re_334_2; + assign Direct_Lookup_Table_n_D_1_t1_re[335] = t1_re_335_2; + assign Direct_Lookup_Table_n_D_1_t1_re[336] = t1_re_336_2; + assign Direct_Lookup_Table_n_D_1_t1_re[337] = t1_re_337_2; + assign Direct_Lookup_Table_n_D_1_t1_re[338] = t1_re_338_2; + assign Direct_Lookup_Table_n_D_1_t1_re[339] = t1_re_339_2; + assign Direct_Lookup_Table_n_D_1_t1_re[340] = t1_re_340_2; + assign Direct_Lookup_Table_n_D_1_t1_re[341] = t1_re_341_2; + assign Direct_Lookup_Table_n_D_1_t1_re[342] = t1_re_342_2; + assign Direct_Lookup_Table_n_D_1_t1_re[343] = t1_re_343_2; + assign Direct_Lookup_Table_n_D_1_t1_re[344] = t1_re_344_2; + assign Direct_Lookup_Table_n_D_1_t1_re[345] = t1_re_345_2; + assign Direct_Lookup_Table_n_D_1_t1_re[346] = t1_re_346_2; + assign Direct_Lookup_Table_n_D_1_t1_re[347] = t1_re_347_2; + assign Direct_Lookup_Table_n_D_1_t1_re[348] = t1_re_348_2; + assign Direct_Lookup_Table_n_D_1_t1_re[349] = t1_re_349_2; + assign Direct_Lookup_Table_n_D_1_t1_re[350] = t1_re_350_2; + assign Direct_Lookup_Table_n_D_1_t1_re[351] = t1_re_351_2; + assign Direct_Lookup_Table_n_D_1_t1_re[352] = t1_re_352_2; + assign Direct_Lookup_Table_n_D_1_t1_re[353] = t1_re_353_2; + assign Direct_Lookup_Table_n_D_1_t1_re[354] = t1_re_354_2; + assign Direct_Lookup_Table_n_D_1_t1_re[355] = t1_re_355_2; + assign Direct_Lookup_Table_n_D_1_t1_re[356] = t1_re_356_2; + assign Direct_Lookup_Table_n_D_1_t1_re[357] = t1_re_357_2; + assign Direct_Lookup_Table_n_D_1_t1_re[358] = t1_re_358_2; + assign Direct_Lookup_Table_n_D_1_t1_re[359] = t1_re_359_2; + assign Direct_Lookup_Table_n_D_1_t1_re[360] = t1_re_360_2; + assign Direct_Lookup_Table_n_D_1_t1_re[361] = t1_re_361_2; + assign Direct_Lookup_Table_n_D_1_t1_re[362] = t1_re_362_2; + assign Direct_Lookup_Table_n_D_1_t1_re[363] = t1_re_363_2; + assign Direct_Lookup_Table_n_D_1_t1_re[364] = t1_re_364_2; + assign Direct_Lookup_Table_n_D_1_t1_re[365] = t1_re_365_2; + assign Direct_Lookup_Table_n_D_1_t1_re[366] = t1_re_366_2; + assign Direct_Lookup_Table_n_D_1_t1_re[367] = t1_re_367_2; + assign Direct_Lookup_Table_n_D_1_t1_re[368] = t1_re_368_2; + assign Direct_Lookup_Table_n_D_1_t1_re[369] = t1_re_369_2; + assign Direct_Lookup_Table_n_D_1_t1_re[370] = t1_re_370_2; + assign Direct_Lookup_Table_n_D_1_t1_re[371] = t1_re_371_2; + assign Direct_Lookup_Table_n_D_1_t1_re[372] = t1_re_372_2; + assign Direct_Lookup_Table_n_D_1_t1_re[373] = t1_re_373_2; + assign Direct_Lookup_Table_n_D_1_t1_re[374] = t1_re_374_2; + assign Direct_Lookup_Table_n_D_1_t1_re[375] = t1_re_375_2; + assign Direct_Lookup_Table_n_D_1_t1_re[376] = t1_re_376_2; + assign Direct_Lookup_Table_n_D_1_t1_re[377] = t1_re_377_2; + assign Direct_Lookup_Table_n_D_1_t1_re[378] = t1_re_378_2; + assign Direct_Lookup_Table_n_D_1_t1_re[379] = t1_re_379_2; + assign Direct_Lookup_Table_n_D_1_t1_re[380] = t1_re_380_2; + assign Direct_Lookup_Table_n_D_1_t1_re[381] = t1_re_381_2; + assign Direct_Lookup_Table_n_D_1_t1_re[382] = t1_re_382_2; + assign Direct_Lookup_Table_n_D_1_t1_re[383] = t1_re_383_2; + assign Direct_Lookup_Table_n_D_1_t1_re[384] = t1_re_384_2; + assign Direct_Lookup_Table_n_D_1_t1_re[385] = t1_re_385_2; + assign Direct_Lookup_Table_n_D_1_t1_re[386] = t1_re_386_2; + assign Direct_Lookup_Table_n_D_1_t1_re[387] = t1_re_387_2; + assign Direct_Lookup_Table_n_D_1_t1_re[388] = t1_re_388_2; + assign Direct_Lookup_Table_n_D_1_t1_re[389] = t1_re_389_2; + assign Direct_Lookup_Table_n_D_1_t1_re[390] = t1_re_390_2; + assign Direct_Lookup_Table_n_D_1_t1_re[391] = t1_re_391_2; + assign Direct_Lookup_Table_n_D_1_t1_re[392] = t1_re_392_2; + assign Direct_Lookup_Table_n_D_1_t1_re[393] = t1_re_393_2; + assign Direct_Lookup_Table_n_D_1_t1_re[394] = t1_re_394_2; + assign Direct_Lookup_Table_n_D_1_t1_re[395] = t1_re_395_2; + assign Direct_Lookup_Table_n_D_1_t1_re[396] = t1_re_396_2; + assign Direct_Lookup_Table_n_D_1_t1_re[397] = t1_re_397_2; + assign Direct_Lookup_Table_n_D_1_t1_re[398] = t1_re_398_2; + assign Direct_Lookup_Table_n_D_1_t1_re[399] = t1_re_399_2; + assign Direct_Lookup_Table_n_D_1_t1_re[400] = t1_re_400_2; + assign Direct_Lookup_Table_n_D_1_t1_re[401] = t1_re_401_2; + assign Direct_Lookup_Table_n_D_1_t1_re[402] = t1_re_402_2; + assign Direct_Lookup_Table_n_D_1_t1_re[403] = t1_re_403_2; + assign Direct_Lookup_Table_n_D_1_t1_re[404] = t1_re_404_2; + assign Direct_Lookup_Table_n_D_1_t1_re[405] = t1_re_405_2; + assign Direct_Lookup_Table_n_D_1_t1_re[406] = t1_re_406_2; + assign Direct_Lookup_Table_n_D_1_t1_re[407] = t1_re_407_2; + assign Direct_Lookup_Table_n_D_1_t1_re[408] = t1_re_408_2; + assign Direct_Lookup_Table_n_D_1_t1_re[409] = t1_re_409_2; + assign Direct_Lookup_Table_n_D_1_t1_re[410] = t1_re_410_2; + assign Direct_Lookup_Table_n_D_1_t1_re[411] = t1_re_411_2; + assign Direct_Lookup_Table_n_D_1_t1_re[412] = t1_re_412_2; + assign Direct_Lookup_Table_n_D_1_t1_re[413] = t1_re_413_2; + assign Direct_Lookup_Table_n_D_1_t1_re[414] = t1_re_414_2; + assign Direct_Lookup_Table_n_D_1_t1_re[415] = t1_re_415_2; + assign Direct_Lookup_Table_n_D_1_t1_re[416] = t1_re_416_2; + assign Direct_Lookup_Table_n_D_1_t1_re[417] = t1_re_417_2; + assign Direct_Lookup_Table_n_D_1_t1_re[418] = t1_re_418_2; + assign Direct_Lookup_Table_n_D_1_t1_re[419] = t1_re_419_2; + assign Direct_Lookup_Table_n_D_1_t1_re[420] = t1_re_420_2; + assign Direct_Lookup_Table_n_D_1_t1_re[421] = t1_re_421_2; + assign Direct_Lookup_Table_n_D_1_t1_re[422] = t1_re_422_2; + assign Direct_Lookup_Table_n_D_1_t1_re[423] = t1_re_423_2; + assign Direct_Lookup_Table_n_D_1_t1_re[424] = t1_re_424_2; + assign Direct_Lookup_Table_n_D_1_t1_re[425] = t1_re_425_2; + assign Direct_Lookup_Table_n_D_1_t1_re[426] = t1_re_426_2; + assign Direct_Lookup_Table_n_D_1_t1_re[427] = t1_re_427_2; + assign Direct_Lookup_Table_n_D_1_t1_re[428] = t1_re_428_2; + assign Direct_Lookup_Table_n_D_1_t1_re[429] = t1_re_429_2; + assign Direct_Lookup_Table_n_D_1_t1_re[430] = t1_re_430_2; + assign Direct_Lookup_Table_n_D_1_t1_re[431] = t1_re_431_2; + assign Direct_Lookup_Table_n_D_1_t1_re[432] = t1_re_432_2; + assign Direct_Lookup_Table_n_D_1_t1_re[433] = t1_re_433_2; + assign Direct_Lookup_Table_n_D_1_t1_re[434] = t1_re_434_2; + assign Direct_Lookup_Table_n_D_1_t1_re[435] = t1_re_435_2; + assign Direct_Lookup_Table_n_D_1_t1_re[436] = t1_re_436_2; + assign Direct_Lookup_Table_n_D_1_t1_re[437] = t1_re_437_2; + assign Direct_Lookup_Table_n_D_1_t1_re[438] = t1_re_438_2; + assign Direct_Lookup_Table_n_D_1_t1_re[439] = t1_re_439_2; + assign Direct_Lookup_Table_n_D_1_t1_re[440] = t1_re_440_2; + assign Direct_Lookup_Table_n_D_1_t1_re[441] = t1_re_441_2; + assign Direct_Lookup_Table_n_D_1_t1_re[442] = t1_re_442_2; + assign Direct_Lookup_Table_n_D_1_t1_re[443] = t1_re_443_2; + assign Direct_Lookup_Table_n_D_1_t1_re[444] = t1_re_444_2; + assign Direct_Lookup_Table_n_D_1_t1_re[445] = t1_re_445_2; + assign Direct_Lookup_Table_n_D_1_t1_re[446] = t1_re_446_2; + assign Direct_Lookup_Table_n_D_1_t1_re[447] = t1_re_447_2; + assign Direct_Lookup_Table_n_D_1_t1_re[448] = t1_re_448_2; + assign Direct_Lookup_Table_n_D_1_t1_re[449] = t1_re_449_2; + assign Direct_Lookup_Table_n_D_1_t1_re[450] = t1_re_450_2; + assign Direct_Lookup_Table_n_D_1_t1_re[451] = t1_re_451_2; + assign Direct_Lookup_Table_n_D_1_t1_re[452] = t1_re_452_2; + assign Direct_Lookup_Table_n_D_1_t1_re[453] = t1_re_453_2; + assign Direct_Lookup_Table_n_D_1_t1_re[454] = t1_re_454_2; + assign Direct_Lookup_Table_n_D_1_t1_re[455] = t1_re_455_2; + assign Direct_Lookup_Table_n_D_1_t1_re[456] = t1_re_456_2; + assign Direct_Lookup_Table_n_D_1_t1_re[457] = t1_re_457_2; + assign Direct_Lookup_Table_n_D_1_t1_re[458] = t1_re_458_2; + assign Direct_Lookup_Table_n_D_1_t1_re[459] = t1_re_459_2; + assign Direct_Lookup_Table_n_D_1_t1_re[460] = t1_re_460_2; + assign Direct_Lookup_Table_n_D_1_t1_re[461] = t1_re_461_2; + assign Direct_Lookup_Table_n_D_1_t1_re[462] = t1_re_462_2; + assign Direct_Lookup_Table_n_D_1_t1_re[463] = t1_re_463_2; + assign Direct_Lookup_Table_n_D_1_t1_re[464] = t1_re_464_2; + assign Direct_Lookup_Table_n_D_1_t1_re[465] = t1_re_465_2; + assign Direct_Lookup_Table_n_D_1_t1_re[466] = t1_re_466_2; + assign Direct_Lookup_Table_n_D_1_t1_re[467] = t1_re_467_2; + assign Direct_Lookup_Table_n_D_1_t1_re[468] = t1_re_468_2; + assign Direct_Lookup_Table_n_D_1_t1_re[469] = t1_re_469_2; + assign Direct_Lookup_Table_n_D_1_t1_re[470] = t1_re_470_2; + assign Direct_Lookup_Table_n_D_1_t1_re[471] = t1_re_471_2; + assign Direct_Lookup_Table_n_D_1_t1_re[472] = t1_re_472_2; + assign Direct_Lookup_Table_n_D_1_t1_re[473] = t1_re_473_2; + assign Direct_Lookup_Table_n_D_1_t1_re[474] = t1_re_474_2; + assign Direct_Lookup_Table_n_D_1_t1_re[475] = t1_re_475_2; + assign Direct_Lookup_Table_n_D_1_t1_re[476] = t1_re_476_2; + assign Direct_Lookup_Table_n_D_1_t1_re[477] = t1_re_477_2; + assign Direct_Lookup_Table_n_D_1_t1_re[478] = t1_re_478_2; + assign Direct_Lookup_Table_n_D_1_t1_re[479] = t1_re_479_2; + assign Direct_Lookup_Table_n_D_1_t1_re[480] = t1_re_480_2; + assign Direct_Lookup_Table_n_D_1_t1_re[481] = t1_re_481_2; + assign Direct_Lookup_Table_n_D_1_t1_re[482] = t1_re_482_2; + assign Direct_Lookup_Table_n_D_1_t1_re[483] = t1_re_483_2; + assign Direct_Lookup_Table_n_D_1_t1_re[484] = t1_re_484_2; + assign Direct_Lookup_Table_n_D_1_t1_re[485] = t1_re_485_2; + assign Direct_Lookup_Table_n_D_1_t1_re[486] = t1_re_486_2; + assign Direct_Lookup_Table_n_D_1_t1_re[487] = t1_re_487_2; + assign Direct_Lookup_Table_n_D_1_t1_re[488] = t1_re_488_2; + assign Direct_Lookup_Table_n_D_1_t1_re[489] = t1_re_489_2; + assign Direct_Lookup_Table_n_D_1_t1_re[490] = t1_re_490_2; + assign Direct_Lookup_Table_n_D_1_t1_re[491] = t1_re_491_2; + assign Direct_Lookup_Table_n_D_1_t1_re[492] = t1_re_492_2; + assign Direct_Lookup_Table_n_D_1_t1_re[493] = t1_re_493_2; + assign Direct_Lookup_Table_n_D_1_t1_re[494] = t1_re_494_2; + assign Direct_Lookup_Table_n_D_1_t1_re[495] = t1_re_495_2; + assign Direct_Lookup_Table_n_D_1_t1_re[496] = t1_re_496_2; + assign Direct_Lookup_Table_n_D_1_t1_re[497] = t1_re_497_2; + assign Direct_Lookup_Table_n_D_1_t1_re[498] = t1_re_498_2; + assign Direct_Lookup_Table_n_D_1_t1_re[499] = t1_re_499_2; + assign Direct_Lookup_Table_n_D_1_t1_re[500] = t1_re_500_2; + assign Direct_Lookup_Table_n_D_1_t1_re[501] = t1_re_501_2; + assign Direct_Lookup_Table_n_D_1_t1_re[502] = t1_re_502_2; + assign Direct_Lookup_Table_n_D_1_t1_re[503] = t1_re_503_2; + assign Direct_Lookup_Table_n_D_1_t1_re[504] = t1_re_504_2; + assign Direct_Lookup_Table_n_D_1_t1_re[505] = t1_re_505_2; + assign Direct_Lookup_Table_n_D_1_t1_re[506] = t1_re_506_2; + assign Direct_Lookup_Table_n_D_1_t1_re[507] = t1_re_507_2; + assign Direct_Lookup_Table_n_D_1_t1_re[508] = t1_re_508_2; + assign Direct_Lookup_Table_n_D_1_t1_re[509] = t1_re_509_2; + assign Direct_Lookup_Table_n_D_1_t1_re[510] = t1_re_510_2; + assign Direct_Lookup_Table_n_D_1_t1_re[511] = t1_re_511_2; + assign Direct_Lookup_Table_n_D_1_t1_im[0] = t1_im_0_2; + assign Direct_Lookup_Table_n_D_1_t1_im[1] = t1_im_1_2; + assign Direct_Lookup_Table_n_D_1_t1_im[2] = t1_im_2_2; + assign Direct_Lookup_Table_n_D_1_t1_im[3] = t1_im_3_2; + assign Direct_Lookup_Table_n_D_1_t1_im[4] = t1_im_4_2; + assign Direct_Lookup_Table_n_D_1_t1_im[5] = t1_im_5_2; + assign Direct_Lookup_Table_n_D_1_t1_im[6] = t1_im_6_2; + assign Direct_Lookup_Table_n_D_1_t1_im[7] = t1_im_7_2; + assign Direct_Lookup_Table_n_D_1_t1_im[8] = t1_im_8_2; + assign Direct_Lookup_Table_n_D_1_t1_im[9] = t1_im_9_2; + assign Direct_Lookup_Table_n_D_1_t1_im[10] = t1_im_10_2; + assign Direct_Lookup_Table_n_D_1_t1_im[11] = t1_im_11_2; + assign Direct_Lookup_Table_n_D_1_t1_im[12] = t1_im_12_2; + assign Direct_Lookup_Table_n_D_1_t1_im[13] = t1_im_13_2; + assign Direct_Lookup_Table_n_D_1_t1_im[14] = t1_im_14_2; + assign Direct_Lookup_Table_n_D_1_t1_im[15] = t1_im_15_2; + assign Direct_Lookup_Table_n_D_1_t1_im[16] = t1_im_16_2; + assign Direct_Lookup_Table_n_D_1_t1_im[17] = t1_im_17_2; + assign Direct_Lookup_Table_n_D_1_t1_im[18] = t1_im_18_2; + assign Direct_Lookup_Table_n_D_1_t1_im[19] = t1_im_19_2; + assign Direct_Lookup_Table_n_D_1_t1_im[20] = t1_im_20_2; + assign Direct_Lookup_Table_n_D_1_t1_im[21] = t1_im_21_2; + assign Direct_Lookup_Table_n_D_1_t1_im[22] = t1_im_22_2; + assign Direct_Lookup_Table_n_D_1_t1_im[23] = t1_im_23_2; + assign Direct_Lookup_Table_n_D_1_t1_im[24] = t1_im_24_2; + assign Direct_Lookup_Table_n_D_1_t1_im[25] = t1_im_25_2; + assign Direct_Lookup_Table_n_D_1_t1_im[26] = t1_im_26_2; + assign Direct_Lookup_Table_n_D_1_t1_im[27] = t1_im_27_2; + assign Direct_Lookup_Table_n_D_1_t1_im[28] = t1_im_28_2; + assign Direct_Lookup_Table_n_D_1_t1_im[29] = t1_im_29_2; + assign Direct_Lookup_Table_n_D_1_t1_im[30] = t1_im_30_2; + assign Direct_Lookup_Table_n_D_1_t1_im[31] = t1_im_31_2; + assign Direct_Lookup_Table_n_D_1_t1_im[32] = t1_im_32_2; + assign Direct_Lookup_Table_n_D_1_t1_im[33] = t1_im_33_2; + assign Direct_Lookup_Table_n_D_1_t1_im[34] = t1_im_34_2; + assign Direct_Lookup_Table_n_D_1_t1_im[35] = t1_im_35_2; + assign Direct_Lookup_Table_n_D_1_t1_im[36] = t1_im_36_2; + assign Direct_Lookup_Table_n_D_1_t1_im[37] = t1_im_37_2; + assign Direct_Lookup_Table_n_D_1_t1_im[38] = t1_im_38_2; + assign Direct_Lookup_Table_n_D_1_t1_im[39] = t1_im_39_2; + assign Direct_Lookup_Table_n_D_1_t1_im[40] = t1_im_40_2; + assign Direct_Lookup_Table_n_D_1_t1_im[41] = t1_im_41_2; + assign Direct_Lookup_Table_n_D_1_t1_im[42] = t1_im_42_2; + assign Direct_Lookup_Table_n_D_1_t1_im[43] = t1_im_43_2; + assign Direct_Lookup_Table_n_D_1_t1_im[44] = t1_im_44_2; + assign Direct_Lookup_Table_n_D_1_t1_im[45] = t1_im_45_2; + assign Direct_Lookup_Table_n_D_1_t1_im[46] = t1_im_46_2; + assign Direct_Lookup_Table_n_D_1_t1_im[47] = t1_im_47_2; + assign Direct_Lookup_Table_n_D_1_t1_im[48] = t1_im_48_2; + assign Direct_Lookup_Table_n_D_1_t1_im[49] = t1_im_49_2; + assign Direct_Lookup_Table_n_D_1_t1_im[50] = t1_im_50_2; + assign Direct_Lookup_Table_n_D_1_t1_im[51] = t1_im_51_2; + assign Direct_Lookup_Table_n_D_1_t1_im[52] = t1_im_52_2; + assign Direct_Lookup_Table_n_D_1_t1_im[53] = t1_im_53_2; + assign Direct_Lookup_Table_n_D_1_t1_im[54] = t1_im_54_2; + assign Direct_Lookup_Table_n_D_1_t1_im[55] = t1_im_55_2; + assign Direct_Lookup_Table_n_D_1_t1_im[56] = t1_im_56_2; + assign Direct_Lookup_Table_n_D_1_t1_im[57] = t1_im_57_2; + assign Direct_Lookup_Table_n_D_1_t1_im[58] = t1_im_58_2; + assign Direct_Lookup_Table_n_D_1_t1_im[59] = t1_im_59_2; + assign Direct_Lookup_Table_n_D_1_t1_im[60] = t1_im_60_2; + assign Direct_Lookup_Table_n_D_1_t1_im[61] = t1_im_61_2; + assign Direct_Lookup_Table_n_D_1_t1_im[62] = t1_im_62_2; + assign Direct_Lookup_Table_n_D_1_t1_im[63] = t1_im_63_2; + assign Direct_Lookup_Table_n_D_1_t1_im[64] = t1_im_64_2; + assign Direct_Lookup_Table_n_D_1_t1_im[65] = t1_im_65_2; + assign Direct_Lookup_Table_n_D_1_t1_im[66] = t1_im_66_2; + assign Direct_Lookup_Table_n_D_1_t1_im[67] = t1_im_67_2; + assign Direct_Lookup_Table_n_D_1_t1_im[68] = t1_im_68_2; + assign Direct_Lookup_Table_n_D_1_t1_im[69] = t1_im_69_2; + assign Direct_Lookup_Table_n_D_1_t1_im[70] = t1_im_70_2; + assign Direct_Lookup_Table_n_D_1_t1_im[71] = t1_im_71_2; + assign Direct_Lookup_Table_n_D_1_t1_im[72] = t1_im_72_2; + assign Direct_Lookup_Table_n_D_1_t1_im[73] = t1_im_73_2; + assign Direct_Lookup_Table_n_D_1_t1_im[74] = t1_im_74_2; + assign Direct_Lookup_Table_n_D_1_t1_im[75] = t1_im_75_2; + assign Direct_Lookup_Table_n_D_1_t1_im[76] = t1_im_76_2; + assign Direct_Lookup_Table_n_D_1_t1_im[77] = t1_im_77_2; + assign Direct_Lookup_Table_n_D_1_t1_im[78] = t1_im_78_2; + assign Direct_Lookup_Table_n_D_1_t1_im[79] = t1_im_79_2; + assign Direct_Lookup_Table_n_D_1_t1_im[80] = t1_im_80_2; + assign Direct_Lookup_Table_n_D_1_t1_im[81] = t1_im_81_2; + assign Direct_Lookup_Table_n_D_1_t1_im[82] = t1_im_82_2; + assign Direct_Lookup_Table_n_D_1_t1_im[83] = t1_im_83_2; + assign Direct_Lookup_Table_n_D_1_t1_im[84] = t1_im_84_2; + assign Direct_Lookup_Table_n_D_1_t1_im[85] = t1_im_85_2; + assign Direct_Lookup_Table_n_D_1_t1_im[86] = t1_im_86_2; + assign Direct_Lookup_Table_n_D_1_t1_im[87] = t1_im_87_2; + assign Direct_Lookup_Table_n_D_1_t1_im[88] = t1_im_88_2; + assign Direct_Lookup_Table_n_D_1_t1_im[89] = t1_im_89_2; + assign Direct_Lookup_Table_n_D_1_t1_im[90] = t1_im_90_2; + assign Direct_Lookup_Table_n_D_1_t1_im[91] = t1_im_91_2; + assign Direct_Lookup_Table_n_D_1_t1_im[92] = t1_im_92_2; + assign Direct_Lookup_Table_n_D_1_t1_im[93] = t1_im_93_2; + assign Direct_Lookup_Table_n_D_1_t1_im[94] = t1_im_94_2; + assign Direct_Lookup_Table_n_D_1_t1_im[95] = t1_im_95_2; + assign Direct_Lookup_Table_n_D_1_t1_im[96] = t1_im_96_2; + assign Direct_Lookup_Table_n_D_1_t1_im[97] = t1_im_97_2; + assign Direct_Lookup_Table_n_D_1_t1_im[98] = t1_im_98_2; + assign Direct_Lookup_Table_n_D_1_t1_im[99] = t1_im_99_2; + assign Direct_Lookup_Table_n_D_1_t1_im[100] = t1_im_100_2; + assign Direct_Lookup_Table_n_D_1_t1_im[101] = t1_im_101_2; + assign Direct_Lookup_Table_n_D_1_t1_im[102] = t1_im_102_2; + assign Direct_Lookup_Table_n_D_1_t1_im[103] = t1_im_103_2; + assign Direct_Lookup_Table_n_D_1_t1_im[104] = t1_im_104_2; + assign Direct_Lookup_Table_n_D_1_t1_im[105] = t1_im_105_2; + assign Direct_Lookup_Table_n_D_1_t1_im[106] = t1_im_106_2; + assign Direct_Lookup_Table_n_D_1_t1_im[107] = t1_im_107_2; + assign Direct_Lookup_Table_n_D_1_t1_im[108] = t1_im_108_2; + assign Direct_Lookup_Table_n_D_1_t1_im[109] = t1_im_109_2; + assign Direct_Lookup_Table_n_D_1_t1_im[110] = t1_im_110_2; + assign Direct_Lookup_Table_n_D_1_t1_im[111] = t1_im_111_2; + assign Direct_Lookup_Table_n_D_1_t1_im[112] = t1_im_112_2; + assign Direct_Lookup_Table_n_D_1_t1_im[113] = t1_im_113_2; + assign Direct_Lookup_Table_n_D_1_t1_im[114] = t1_im_114_2; + assign Direct_Lookup_Table_n_D_1_t1_im[115] = t1_im_115_2; + assign Direct_Lookup_Table_n_D_1_t1_im[116] = t1_im_116_2; + assign Direct_Lookup_Table_n_D_1_t1_im[117] = t1_im_117_2; + assign Direct_Lookup_Table_n_D_1_t1_im[118] = t1_im_118_2; + assign Direct_Lookup_Table_n_D_1_t1_im[119] = t1_im_119_2; + assign Direct_Lookup_Table_n_D_1_t1_im[120] = t1_im_120_2; + assign Direct_Lookup_Table_n_D_1_t1_im[121] = t1_im_121_2; + assign Direct_Lookup_Table_n_D_1_t1_im[122] = t1_im_122_2; + assign Direct_Lookup_Table_n_D_1_t1_im[123] = t1_im_123_2; + assign Direct_Lookup_Table_n_D_1_t1_im[124] = t1_im_124_2; + assign Direct_Lookup_Table_n_D_1_t1_im[125] = t1_im_125_2; + assign Direct_Lookup_Table_n_D_1_t1_im[126] = t1_im_126_2; + assign Direct_Lookup_Table_n_D_1_t1_im[127] = t1_im_127_2; + assign Direct_Lookup_Table_n_D_1_t1_im[128] = t1_im_128_2; + assign Direct_Lookup_Table_n_D_1_t1_im[129] = t1_im_129_2; + assign Direct_Lookup_Table_n_D_1_t1_im[130] = t1_im_130_2; + assign Direct_Lookup_Table_n_D_1_t1_im[131] = t1_im_131_2; + assign Direct_Lookup_Table_n_D_1_t1_im[132] = t1_im_132_2; + assign Direct_Lookup_Table_n_D_1_t1_im[133] = t1_im_133_2; + assign Direct_Lookup_Table_n_D_1_t1_im[134] = t1_im_134_2; + assign Direct_Lookup_Table_n_D_1_t1_im[135] = t1_im_135_2; + assign Direct_Lookup_Table_n_D_1_t1_im[136] = t1_im_136_2; + assign Direct_Lookup_Table_n_D_1_t1_im[137] = t1_im_137_2; + assign Direct_Lookup_Table_n_D_1_t1_im[138] = t1_im_138_2; + assign Direct_Lookup_Table_n_D_1_t1_im[139] = t1_im_139_2; + assign Direct_Lookup_Table_n_D_1_t1_im[140] = t1_im_140_2; + assign Direct_Lookup_Table_n_D_1_t1_im[141] = t1_im_141_2; + assign Direct_Lookup_Table_n_D_1_t1_im[142] = t1_im_142_2; + assign Direct_Lookup_Table_n_D_1_t1_im[143] = t1_im_143_2; + assign Direct_Lookup_Table_n_D_1_t1_im[144] = t1_im_144_2; + assign Direct_Lookup_Table_n_D_1_t1_im[145] = t1_im_145_2; + assign Direct_Lookup_Table_n_D_1_t1_im[146] = t1_im_146_2; + assign Direct_Lookup_Table_n_D_1_t1_im[147] = t1_im_147_2; + assign Direct_Lookup_Table_n_D_1_t1_im[148] = t1_im_148_2; + assign Direct_Lookup_Table_n_D_1_t1_im[149] = t1_im_149_2; + assign Direct_Lookup_Table_n_D_1_t1_im[150] = t1_im_150_2; + assign Direct_Lookup_Table_n_D_1_t1_im[151] = t1_im_151_2; + assign Direct_Lookup_Table_n_D_1_t1_im[152] = t1_im_152_2; + assign Direct_Lookup_Table_n_D_1_t1_im[153] = t1_im_153_2; + assign Direct_Lookup_Table_n_D_1_t1_im[154] = t1_im_154_2; + assign Direct_Lookup_Table_n_D_1_t1_im[155] = t1_im_155_2; + assign Direct_Lookup_Table_n_D_1_t1_im[156] = t1_im_156_2; + assign Direct_Lookup_Table_n_D_1_t1_im[157] = t1_im_157_2; + assign Direct_Lookup_Table_n_D_1_t1_im[158] = t1_im_158_2; + assign Direct_Lookup_Table_n_D_1_t1_im[159] = t1_im_159_2; + assign Direct_Lookup_Table_n_D_1_t1_im[160] = t1_im_160_2; + assign Direct_Lookup_Table_n_D_1_t1_im[161] = t1_im_161_2; + assign Direct_Lookup_Table_n_D_1_t1_im[162] = t1_im_162_2; + assign Direct_Lookup_Table_n_D_1_t1_im[163] = t1_im_163_2; + assign Direct_Lookup_Table_n_D_1_t1_im[164] = t1_im_164_2; + assign Direct_Lookup_Table_n_D_1_t1_im[165] = t1_im_165_2; + assign Direct_Lookup_Table_n_D_1_t1_im[166] = t1_im_166_2; + assign Direct_Lookup_Table_n_D_1_t1_im[167] = t1_im_167_2; + assign Direct_Lookup_Table_n_D_1_t1_im[168] = t1_im_168_2; + assign Direct_Lookup_Table_n_D_1_t1_im[169] = t1_im_169_2; + assign Direct_Lookup_Table_n_D_1_t1_im[170] = t1_im_170_2; + assign Direct_Lookup_Table_n_D_1_t1_im[171] = t1_im_171_2; + assign Direct_Lookup_Table_n_D_1_t1_im[172] = t1_im_172_2; + assign Direct_Lookup_Table_n_D_1_t1_im[173] = t1_im_173_2; + assign Direct_Lookup_Table_n_D_1_t1_im[174] = t1_im_174_2; + assign Direct_Lookup_Table_n_D_1_t1_im[175] = t1_im_175_2; + assign Direct_Lookup_Table_n_D_1_t1_im[176] = t1_im_176_2; + assign Direct_Lookup_Table_n_D_1_t1_im[177] = t1_im_177_2; + assign Direct_Lookup_Table_n_D_1_t1_im[178] = t1_im_178_2; + assign Direct_Lookup_Table_n_D_1_t1_im[179] = t1_im_179_2; + assign Direct_Lookup_Table_n_D_1_t1_im[180] = t1_im_180_2; + assign Direct_Lookup_Table_n_D_1_t1_im[181] = t1_im_181_2; + assign Direct_Lookup_Table_n_D_1_t1_im[182] = t1_im_182_2; + assign Direct_Lookup_Table_n_D_1_t1_im[183] = t1_im_183_2; + assign Direct_Lookup_Table_n_D_1_t1_im[184] = t1_im_184_2; + assign Direct_Lookup_Table_n_D_1_t1_im[185] = t1_im_185_2; + assign Direct_Lookup_Table_n_D_1_t1_im[186] = t1_im_186_2; + assign Direct_Lookup_Table_n_D_1_t1_im[187] = t1_im_187_2; + assign Direct_Lookup_Table_n_D_1_t1_im[188] = t1_im_188_2; + assign Direct_Lookup_Table_n_D_1_t1_im[189] = t1_im_189_2; + assign Direct_Lookup_Table_n_D_1_t1_im[190] = t1_im_190_2; + assign Direct_Lookup_Table_n_D_1_t1_im[191] = t1_im_191_2; + assign Direct_Lookup_Table_n_D_1_t1_im[192] = t1_im_192_2; + assign Direct_Lookup_Table_n_D_1_t1_im[193] = t1_im_193_2; + assign Direct_Lookup_Table_n_D_1_t1_im[194] = t1_im_194_2; + assign Direct_Lookup_Table_n_D_1_t1_im[195] = t1_im_195_2; + assign Direct_Lookup_Table_n_D_1_t1_im[196] = t1_im_196_2; + assign Direct_Lookup_Table_n_D_1_t1_im[197] = t1_im_197_2; + assign Direct_Lookup_Table_n_D_1_t1_im[198] = t1_im_198_2; + assign Direct_Lookup_Table_n_D_1_t1_im[199] = t1_im_199_2; + assign Direct_Lookup_Table_n_D_1_t1_im[200] = t1_im_200_2; + assign Direct_Lookup_Table_n_D_1_t1_im[201] = t1_im_201_2; + assign Direct_Lookup_Table_n_D_1_t1_im[202] = t1_im_202_2; + assign Direct_Lookup_Table_n_D_1_t1_im[203] = t1_im_203_2; + assign Direct_Lookup_Table_n_D_1_t1_im[204] = t1_im_204_2; + assign Direct_Lookup_Table_n_D_1_t1_im[205] = t1_im_205_2; + assign Direct_Lookup_Table_n_D_1_t1_im[206] = t1_im_206_2; + assign Direct_Lookup_Table_n_D_1_t1_im[207] = t1_im_207_2; + assign Direct_Lookup_Table_n_D_1_t1_im[208] = t1_im_208_2; + assign Direct_Lookup_Table_n_D_1_t1_im[209] = t1_im_209_2; + assign Direct_Lookup_Table_n_D_1_t1_im[210] = t1_im_210_2; + assign Direct_Lookup_Table_n_D_1_t1_im[211] = t1_im_211_2; + assign Direct_Lookup_Table_n_D_1_t1_im[212] = t1_im_212_2; + assign Direct_Lookup_Table_n_D_1_t1_im[213] = t1_im_213_2; + assign Direct_Lookup_Table_n_D_1_t1_im[214] = t1_im_214_2; + assign Direct_Lookup_Table_n_D_1_t1_im[215] = t1_im_215_2; + assign Direct_Lookup_Table_n_D_1_t1_im[216] = t1_im_216_2; + assign Direct_Lookup_Table_n_D_1_t1_im[217] = t1_im_217_2; + assign Direct_Lookup_Table_n_D_1_t1_im[218] = t1_im_218_2; + assign Direct_Lookup_Table_n_D_1_t1_im[219] = t1_im_219_2; + assign Direct_Lookup_Table_n_D_1_t1_im[220] = t1_im_220_2; + assign Direct_Lookup_Table_n_D_1_t1_im[221] = t1_im_221_2; + assign Direct_Lookup_Table_n_D_1_t1_im[222] = t1_im_222_2; + assign Direct_Lookup_Table_n_D_1_t1_im[223] = t1_im_223_2; + assign Direct_Lookup_Table_n_D_1_t1_im[224] = t1_im_224_2; + assign Direct_Lookup_Table_n_D_1_t1_im[225] = t1_im_225_2; + assign Direct_Lookup_Table_n_D_1_t1_im[226] = t1_im_226_2; + assign Direct_Lookup_Table_n_D_1_t1_im[227] = t1_im_227_2; + assign Direct_Lookup_Table_n_D_1_t1_im[228] = t1_im_228_2; + assign Direct_Lookup_Table_n_D_1_t1_im[229] = t1_im_229_2; + assign Direct_Lookup_Table_n_D_1_t1_im[230] = t1_im_230_2; + assign Direct_Lookup_Table_n_D_1_t1_im[231] = t1_im_231_2; + assign Direct_Lookup_Table_n_D_1_t1_im[232] = t1_im_232_2; + assign Direct_Lookup_Table_n_D_1_t1_im[233] = t1_im_233_2; + assign Direct_Lookup_Table_n_D_1_t1_im[234] = t1_im_234_2; + assign Direct_Lookup_Table_n_D_1_t1_im[235] = t1_im_235_2; + assign Direct_Lookup_Table_n_D_1_t1_im[236] = t1_im_236_2; + assign Direct_Lookup_Table_n_D_1_t1_im[237] = t1_im_237_2; + assign Direct_Lookup_Table_n_D_1_t1_im[238] = t1_im_238_2; + assign Direct_Lookup_Table_n_D_1_t1_im[239] = t1_im_239_2; + assign Direct_Lookup_Table_n_D_1_t1_im[240] = t1_im_240_2; + assign Direct_Lookup_Table_n_D_1_t1_im[241] = t1_im_241_2; + assign Direct_Lookup_Table_n_D_1_t1_im[242] = t1_im_242_2; + assign Direct_Lookup_Table_n_D_1_t1_im[243] = t1_im_243_2; + assign Direct_Lookup_Table_n_D_1_t1_im[244] = t1_im_244_2; + assign Direct_Lookup_Table_n_D_1_t1_im[245] = t1_im_245_2; + assign Direct_Lookup_Table_n_D_1_t1_im[246] = t1_im_246_2; + assign Direct_Lookup_Table_n_D_1_t1_im[247] = t1_im_247_2; + assign Direct_Lookup_Table_n_D_1_t1_im[248] = t1_im_248_2; + assign Direct_Lookup_Table_n_D_1_t1_im[249] = t1_im_249_2; + assign Direct_Lookup_Table_n_D_1_t1_im[250] = t1_im_250_2; + assign Direct_Lookup_Table_n_D_1_t1_im[251] = t1_im_251_2; + assign Direct_Lookup_Table_n_D_1_t1_im[252] = t1_im_252_2; + assign Direct_Lookup_Table_n_D_1_t1_im[253] = t1_im_253_2; + assign Direct_Lookup_Table_n_D_1_t1_im[254] = t1_im_254_2; + assign Direct_Lookup_Table_n_D_1_t1_im[255] = t1_im_255_2; + assign Direct_Lookup_Table_n_D_1_t1_im[256] = t1_im_256_2; + assign Direct_Lookup_Table_n_D_1_t1_im[257] = t1_im_257_2; + assign Direct_Lookup_Table_n_D_1_t1_im[258] = t1_im_258_2; + assign Direct_Lookup_Table_n_D_1_t1_im[259] = t1_im_259_2; + assign Direct_Lookup_Table_n_D_1_t1_im[260] = t1_im_260_2; + assign Direct_Lookup_Table_n_D_1_t1_im[261] = t1_im_261_2; + assign Direct_Lookup_Table_n_D_1_t1_im[262] = t1_im_262_2; + assign Direct_Lookup_Table_n_D_1_t1_im[263] = t1_im_263_2; + assign Direct_Lookup_Table_n_D_1_t1_im[264] = t1_im_264_2; + assign Direct_Lookup_Table_n_D_1_t1_im[265] = t1_im_265_2; + assign Direct_Lookup_Table_n_D_1_t1_im[266] = t1_im_266_2; + assign Direct_Lookup_Table_n_D_1_t1_im[267] = t1_im_267_2; + assign Direct_Lookup_Table_n_D_1_t1_im[268] = t1_im_268_2; + assign Direct_Lookup_Table_n_D_1_t1_im[269] = t1_im_269_2; + assign Direct_Lookup_Table_n_D_1_t1_im[270] = t1_im_270_2; + assign Direct_Lookup_Table_n_D_1_t1_im[271] = t1_im_271_2; + assign Direct_Lookup_Table_n_D_1_t1_im[272] = t1_im_272_2; + assign Direct_Lookup_Table_n_D_1_t1_im[273] = t1_im_273_2; + assign Direct_Lookup_Table_n_D_1_t1_im[274] = t1_im_274_2; + assign Direct_Lookup_Table_n_D_1_t1_im[275] = t1_im_275_2; + assign Direct_Lookup_Table_n_D_1_t1_im[276] = t1_im_276_2; + assign Direct_Lookup_Table_n_D_1_t1_im[277] = t1_im_277_2; + assign Direct_Lookup_Table_n_D_1_t1_im[278] = t1_im_278_2; + assign Direct_Lookup_Table_n_D_1_t1_im[279] = t1_im_279_2; + assign Direct_Lookup_Table_n_D_1_t1_im[280] = t1_im_280_2; + assign Direct_Lookup_Table_n_D_1_t1_im[281] = t1_im_281_2; + assign Direct_Lookup_Table_n_D_1_t1_im[282] = t1_im_282_2; + assign Direct_Lookup_Table_n_D_1_t1_im[283] = t1_im_283_2; + assign Direct_Lookup_Table_n_D_1_t1_im[284] = t1_im_284_2; + assign Direct_Lookup_Table_n_D_1_t1_im[285] = t1_im_285_2; + assign Direct_Lookup_Table_n_D_1_t1_im[286] = t1_im_286_2; + assign Direct_Lookup_Table_n_D_1_t1_im[287] = t1_im_287_2; + assign Direct_Lookup_Table_n_D_1_t1_im[288] = t1_im_288_2; + assign Direct_Lookup_Table_n_D_1_t1_im[289] = t1_im_289_2; + assign Direct_Lookup_Table_n_D_1_t1_im[290] = t1_im_290_2; + assign Direct_Lookup_Table_n_D_1_t1_im[291] = t1_im_291_2; + assign Direct_Lookup_Table_n_D_1_t1_im[292] = t1_im_292_2; + assign Direct_Lookup_Table_n_D_1_t1_im[293] = t1_im_293_2; + assign Direct_Lookup_Table_n_D_1_t1_im[294] = t1_im_294_2; + assign Direct_Lookup_Table_n_D_1_t1_im[295] = t1_im_295_2; + assign Direct_Lookup_Table_n_D_1_t1_im[296] = t1_im_296_2; + assign Direct_Lookup_Table_n_D_1_t1_im[297] = t1_im_297_2; + assign Direct_Lookup_Table_n_D_1_t1_im[298] = t1_im_298_2; + assign Direct_Lookup_Table_n_D_1_t1_im[299] = t1_im_299_2; + assign Direct_Lookup_Table_n_D_1_t1_im[300] = t1_im_300_2; + assign Direct_Lookup_Table_n_D_1_t1_im[301] = t1_im_301_2; + assign Direct_Lookup_Table_n_D_1_t1_im[302] = t1_im_302_2; + assign Direct_Lookup_Table_n_D_1_t1_im[303] = t1_im_303_2; + assign Direct_Lookup_Table_n_D_1_t1_im[304] = t1_im_304_2; + assign Direct_Lookup_Table_n_D_1_t1_im[305] = t1_im_305_2; + assign Direct_Lookup_Table_n_D_1_t1_im[306] = t1_im_306_2; + assign Direct_Lookup_Table_n_D_1_t1_im[307] = t1_im_307_2; + assign Direct_Lookup_Table_n_D_1_t1_im[308] = t1_im_308_2; + assign Direct_Lookup_Table_n_D_1_t1_im[309] = t1_im_309_2; + assign Direct_Lookup_Table_n_D_1_t1_im[310] = t1_im_310_2; + assign Direct_Lookup_Table_n_D_1_t1_im[311] = t1_im_311_2; + assign Direct_Lookup_Table_n_D_1_t1_im[312] = t1_im_312_2; + assign Direct_Lookup_Table_n_D_1_t1_im[313] = t1_im_313_2; + assign Direct_Lookup_Table_n_D_1_t1_im[314] = t1_im_314_2; + assign Direct_Lookup_Table_n_D_1_t1_im[315] = t1_im_315_2; + assign Direct_Lookup_Table_n_D_1_t1_im[316] = t1_im_316_2; + assign Direct_Lookup_Table_n_D_1_t1_im[317] = t1_im_317_2; + assign Direct_Lookup_Table_n_D_1_t1_im[318] = t1_im_318_2; + assign Direct_Lookup_Table_n_D_1_t1_im[319] = t1_im_319_2; + assign Direct_Lookup_Table_n_D_1_t1_im[320] = t1_im_320_2; + assign Direct_Lookup_Table_n_D_1_t1_im[321] = t1_im_321_2; + assign Direct_Lookup_Table_n_D_1_t1_im[322] = t1_im_322_2; + assign Direct_Lookup_Table_n_D_1_t1_im[323] = t1_im_323_2; + assign Direct_Lookup_Table_n_D_1_t1_im[324] = t1_im_324_2; + assign Direct_Lookup_Table_n_D_1_t1_im[325] = t1_im_325_2; + assign Direct_Lookup_Table_n_D_1_t1_im[326] = t1_im_326_2; + assign Direct_Lookup_Table_n_D_1_t1_im[327] = t1_im_327_2; + assign Direct_Lookup_Table_n_D_1_t1_im[328] = t1_im_328_2; + assign Direct_Lookup_Table_n_D_1_t1_im[329] = t1_im_329_2; + assign Direct_Lookup_Table_n_D_1_t1_im[330] = t1_im_330_2; + assign Direct_Lookup_Table_n_D_1_t1_im[331] = t1_im_331_2; + assign Direct_Lookup_Table_n_D_1_t1_im[332] = t1_im_332_2; + assign Direct_Lookup_Table_n_D_1_t1_im[333] = t1_im_333_2; + assign Direct_Lookup_Table_n_D_1_t1_im[334] = t1_im_334_2; + assign Direct_Lookup_Table_n_D_1_t1_im[335] = t1_im_335_2; + assign Direct_Lookup_Table_n_D_1_t1_im[336] = t1_im_336_2; + assign Direct_Lookup_Table_n_D_1_t1_im[337] = t1_im_337_2; + assign Direct_Lookup_Table_n_D_1_t1_im[338] = t1_im_338_2; + assign Direct_Lookup_Table_n_D_1_t1_im[339] = t1_im_339_2; + assign Direct_Lookup_Table_n_D_1_t1_im[340] = t1_im_340_2; + assign Direct_Lookup_Table_n_D_1_t1_im[341] = t1_im_341_2; + assign Direct_Lookup_Table_n_D_1_t1_im[342] = t1_im_342_2; + assign Direct_Lookup_Table_n_D_1_t1_im[343] = t1_im_343_2; + assign Direct_Lookup_Table_n_D_1_t1_im[344] = t1_im_344_2; + assign Direct_Lookup_Table_n_D_1_t1_im[345] = t1_im_345_2; + assign Direct_Lookup_Table_n_D_1_t1_im[346] = t1_im_346_2; + assign Direct_Lookup_Table_n_D_1_t1_im[347] = t1_im_347_2; + assign Direct_Lookup_Table_n_D_1_t1_im[348] = t1_im_348_2; + assign Direct_Lookup_Table_n_D_1_t1_im[349] = t1_im_349_2; + assign Direct_Lookup_Table_n_D_1_t1_im[350] = t1_im_350_2; + assign Direct_Lookup_Table_n_D_1_t1_im[351] = t1_im_351_2; + assign Direct_Lookup_Table_n_D_1_t1_im[352] = t1_im_352_2; + assign Direct_Lookup_Table_n_D_1_t1_im[353] = t1_im_353_2; + assign Direct_Lookup_Table_n_D_1_t1_im[354] = t1_im_354_2; + assign Direct_Lookup_Table_n_D_1_t1_im[355] = t1_im_355_2; + assign Direct_Lookup_Table_n_D_1_t1_im[356] = t1_im_356_2; + assign Direct_Lookup_Table_n_D_1_t1_im[357] = t1_im_357_2; + assign Direct_Lookup_Table_n_D_1_t1_im[358] = t1_im_358_2; + assign Direct_Lookup_Table_n_D_1_t1_im[359] = t1_im_359_2; + assign Direct_Lookup_Table_n_D_1_t1_im[360] = t1_im_360_2; + assign Direct_Lookup_Table_n_D_1_t1_im[361] = t1_im_361_2; + assign Direct_Lookup_Table_n_D_1_t1_im[362] = t1_im_362_2; + assign Direct_Lookup_Table_n_D_1_t1_im[363] = t1_im_363_2; + assign Direct_Lookup_Table_n_D_1_t1_im[364] = t1_im_364_2; + assign Direct_Lookup_Table_n_D_1_t1_im[365] = t1_im_365_2; + assign Direct_Lookup_Table_n_D_1_t1_im[366] = t1_im_366_2; + assign Direct_Lookup_Table_n_D_1_t1_im[367] = t1_im_367_2; + assign Direct_Lookup_Table_n_D_1_t1_im[368] = t1_im_368_2; + assign Direct_Lookup_Table_n_D_1_t1_im[369] = t1_im_369_2; + assign Direct_Lookup_Table_n_D_1_t1_im[370] = t1_im_370_2; + assign Direct_Lookup_Table_n_D_1_t1_im[371] = t1_im_371_2; + assign Direct_Lookup_Table_n_D_1_t1_im[372] = t1_im_372_2; + assign Direct_Lookup_Table_n_D_1_t1_im[373] = t1_im_373_2; + assign Direct_Lookup_Table_n_D_1_t1_im[374] = t1_im_374_2; + assign Direct_Lookup_Table_n_D_1_t1_im[375] = t1_im_375_2; + assign Direct_Lookup_Table_n_D_1_t1_im[376] = t1_im_376_2; + assign Direct_Lookup_Table_n_D_1_t1_im[377] = t1_im_377_2; + assign Direct_Lookup_Table_n_D_1_t1_im[378] = t1_im_378_2; + assign Direct_Lookup_Table_n_D_1_t1_im[379] = t1_im_379_2; + assign Direct_Lookup_Table_n_D_1_t1_im[380] = t1_im_380_2; + assign Direct_Lookup_Table_n_D_1_t1_im[381] = t1_im_381_2; + assign Direct_Lookup_Table_n_D_1_t1_im[382] = t1_im_382_2; + assign Direct_Lookup_Table_n_D_1_t1_im[383] = t1_im_383_2; + assign Direct_Lookup_Table_n_D_1_t1_im[384] = t1_im_384_2; + assign Direct_Lookup_Table_n_D_1_t1_im[385] = t1_im_385_2; + assign Direct_Lookup_Table_n_D_1_t1_im[386] = t1_im_386_2; + assign Direct_Lookup_Table_n_D_1_t1_im[387] = t1_im_387_2; + assign Direct_Lookup_Table_n_D_1_t1_im[388] = t1_im_388_2; + assign Direct_Lookup_Table_n_D_1_t1_im[389] = t1_im_389_2; + assign Direct_Lookup_Table_n_D_1_t1_im[390] = t1_im_390_2; + assign Direct_Lookup_Table_n_D_1_t1_im[391] = t1_im_391_2; + assign Direct_Lookup_Table_n_D_1_t1_im[392] = t1_im_392_2; + assign Direct_Lookup_Table_n_D_1_t1_im[393] = t1_im_393_2; + assign Direct_Lookup_Table_n_D_1_t1_im[394] = t1_im_394_2; + assign Direct_Lookup_Table_n_D_1_t1_im[395] = t1_im_395_2; + assign Direct_Lookup_Table_n_D_1_t1_im[396] = t1_im_396_2; + assign Direct_Lookup_Table_n_D_1_t1_im[397] = t1_im_397_2; + assign Direct_Lookup_Table_n_D_1_t1_im[398] = t1_im_398_2; + assign Direct_Lookup_Table_n_D_1_t1_im[399] = t1_im_399_2; + assign Direct_Lookup_Table_n_D_1_t1_im[400] = t1_im_400_2; + assign Direct_Lookup_Table_n_D_1_t1_im[401] = t1_im_401_2; + assign Direct_Lookup_Table_n_D_1_t1_im[402] = t1_im_402_2; + assign Direct_Lookup_Table_n_D_1_t1_im[403] = t1_im_403_2; + assign Direct_Lookup_Table_n_D_1_t1_im[404] = t1_im_404_2; + assign Direct_Lookup_Table_n_D_1_t1_im[405] = t1_im_405_2; + assign Direct_Lookup_Table_n_D_1_t1_im[406] = t1_im_406_2; + assign Direct_Lookup_Table_n_D_1_t1_im[407] = t1_im_407_2; + assign Direct_Lookup_Table_n_D_1_t1_im[408] = t1_im_408_2; + assign Direct_Lookup_Table_n_D_1_t1_im[409] = t1_im_409_2; + assign Direct_Lookup_Table_n_D_1_t1_im[410] = t1_im_410_2; + assign Direct_Lookup_Table_n_D_1_t1_im[411] = t1_im_411_2; + assign Direct_Lookup_Table_n_D_1_t1_im[412] = t1_im_412_2; + assign Direct_Lookup_Table_n_D_1_t1_im[413] = t1_im_413_2; + assign Direct_Lookup_Table_n_D_1_t1_im[414] = t1_im_414_2; + assign Direct_Lookup_Table_n_D_1_t1_im[415] = t1_im_415_2; + assign Direct_Lookup_Table_n_D_1_t1_im[416] = t1_im_416_2; + assign Direct_Lookup_Table_n_D_1_t1_im[417] = t1_im_417_2; + assign Direct_Lookup_Table_n_D_1_t1_im[418] = t1_im_418_2; + assign Direct_Lookup_Table_n_D_1_t1_im[419] = t1_im_419_2; + assign Direct_Lookup_Table_n_D_1_t1_im[420] = t1_im_420_2; + assign Direct_Lookup_Table_n_D_1_t1_im[421] = t1_im_421_2; + assign Direct_Lookup_Table_n_D_1_t1_im[422] = t1_im_422_2; + assign Direct_Lookup_Table_n_D_1_t1_im[423] = t1_im_423_2; + assign Direct_Lookup_Table_n_D_1_t1_im[424] = t1_im_424_2; + assign Direct_Lookup_Table_n_D_1_t1_im[425] = t1_im_425_2; + assign Direct_Lookup_Table_n_D_1_t1_im[426] = t1_im_426_2; + assign Direct_Lookup_Table_n_D_1_t1_im[427] = t1_im_427_2; + assign Direct_Lookup_Table_n_D_1_t1_im[428] = t1_im_428_2; + assign Direct_Lookup_Table_n_D_1_t1_im[429] = t1_im_429_2; + assign Direct_Lookup_Table_n_D_1_t1_im[430] = t1_im_430_2; + assign Direct_Lookup_Table_n_D_1_t1_im[431] = t1_im_431_2; + assign Direct_Lookup_Table_n_D_1_t1_im[432] = t1_im_432_2; + assign Direct_Lookup_Table_n_D_1_t1_im[433] = t1_im_433_2; + assign Direct_Lookup_Table_n_D_1_t1_im[434] = t1_im_434_2; + assign Direct_Lookup_Table_n_D_1_t1_im[435] = t1_im_435_2; + assign Direct_Lookup_Table_n_D_1_t1_im[436] = t1_im_436_2; + assign Direct_Lookup_Table_n_D_1_t1_im[437] = t1_im_437_2; + assign Direct_Lookup_Table_n_D_1_t1_im[438] = t1_im_438_2; + assign Direct_Lookup_Table_n_D_1_t1_im[439] = t1_im_439_2; + assign Direct_Lookup_Table_n_D_1_t1_im[440] = t1_im_440_2; + assign Direct_Lookup_Table_n_D_1_t1_im[441] = t1_im_441_2; + assign Direct_Lookup_Table_n_D_1_t1_im[442] = t1_im_442_2; + assign Direct_Lookup_Table_n_D_1_t1_im[443] = t1_im_443_2; + assign Direct_Lookup_Table_n_D_1_t1_im[444] = t1_im_444_2; + assign Direct_Lookup_Table_n_D_1_t1_im[445] = t1_im_445_2; + assign Direct_Lookup_Table_n_D_1_t1_im[446] = t1_im_446_2; + assign Direct_Lookup_Table_n_D_1_t1_im[447] = t1_im_447_2; + assign Direct_Lookup_Table_n_D_1_t1_im[448] = t1_im_448_2; + assign Direct_Lookup_Table_n_D_1_t1_im[449] = t1_im_449_2; + assign Direct_Lookup_Table_n_D_1_t1_im[450] = t1_im_450_2; + assign Direct_Lookup_Table_n_D_1_t1_im[451] = t1_im_451_2; + assign Direct_Lookup_Table_n_D_1_t1_im[452] = t1_im_452_2; + assign Direct_Lookup_Table_n_D_1_t1_im[453] = t1_im_453_2; + assign Direct_Lookup_Table_n_D_1_t1_im[454] = t1_im_454_2; + assign Direct_Lookup_Table_n_D_1_t1_im[455] = t1_im_455_2; + assign Direct_Lookup_Table_n_D_1_t1_im[456] = t1_im_456_2; + assign Direct_Lookup_Table_n_D_1_t1_im[457] = t1_im_457_2; + assign Direct_Lookup_Table_n_D_1_t1_im[458] = t1_im_458_2; + assign Direct_Lookup_Table_n_D_1_t1_im[459] = t1_im_459_2; + assign Direct_Lookup_Table_n_D_1_t1_im[460] = t1_im_460_2; + assign Direct_Lookup_Table_n_D_1_t1_im[461] = t1_im_461_2; + assign Direct_Lookup_Table_n_D_1_t1_im[462] = t1_im_462_2; + assign Direct_Lookup_Table_n_D_1_t1_im[463] = t1_im_463_2; + assign Direct_Lookup_Table_n_D_1_t1_im[464] = t1_im_464_2; + assign Direct_Lookup_Table_n_D_1_t1_im[465] = t1_im_465_2; + assign Direct_Lookup_Table_n_D_1_t1_im[466] = t1_im_466_2; + assign Direct_Lookup_Table_n_D_1_t1_im[467] = t1_im_467_2; + assign Direct_Lookup_Table_n_D_1_t1_im[468] = t1_im_468_2; + assign Direct_Lookup_Table_n_D_1_t1_im[469] = t1_im_469_2; + assign Direct_Lookup_Table_n_D_1_t1_im[470] = t1_im_470_2; + assign Direct_Lookup_Table_n_D_1_t1_im[471] = t1_im_471_2; + assign Direct_Lookup_Table_n_D_1_t1_im[472] = t1_im_472_2; + assign Direct_Lookup_Table_n_D_1_t1_im[473] = t1_im_473_2; + assign Direct_Lookup_Table_n_D_1_t1_im[474] = t1_im_474_2; + assign Direct_Lookup_Table_n_D_1_t1_im[475] = t1_im_475_2; + assign Direct_Lookup_Table_n_D_1_t1_im[476] = t1_im_476_2; + assign Direct_Lookup_Table_n_D_1_t1_im[477] = t1_im_477_2; + assign Direct_Lookup_Table_n_D_1_t1_im[478] = t1_im_478_2; + assign Direct_Lookup_Table_n_D_1_t1_im[479] = t1_im_479_2; + assign Direct_Lookup_Table_n_D_1_t1_im[480] = t1_im_480_2; + assign Direct_Lookup_Table_n_D_1_t1_im[481] = t1_im_481_2; + assign Direct_Lookup_Table_n_D_1_t1_im[482] = t1_im_482_2; + assign Direct_Lookup_Table_n_D_1_t1_im[483] = t1_im_483_2; + assign Direct_Lookup_Table_n_D_1_t1_im[484] = t1_im_484_2; + assign Direct_Lookup_Table_n_D_1_t1_im[485] = t1_im_485_2; + assign Direct_Lookup_Table_n_D_1_t1_im[486] = t1_im_486_2; + assign Direct_Lookup_Table_n_D_1_t1_im[487] = t1_im_487_2; + assign Direct_Lookup_Table_n_D_1_t1_im[488] = t1_im_488_2; + assign Direct_Lookup_Table_n_D_1_t1_im[489] = t1_im_489_2; + assign Direct_Lookup_Table_n_D_1_t1_im[490] = t1_im_490_2; + assign Direct_Lookup_Table_n_D_1_t1_im[491] = t1_im_491_2; + assign Direct_Lookup_Table_n_D_1_t1_im[492] = t1_im_492_2; + assign Direct_Lookup_Table_n_D_1_t1_im[493] = t1_im_493_2; + assign Direct_Lookup_Table_n_D_1_t1_im[494] = t1_im_494_2; + assign Direct_Lookup_Table_n_D_1_t1_im[495] = t1_im_495_2; + assign Direct_Lookup_Table_n_D_1_t1_im[496] = t1_im_496_2; + assign Direct_Lookup_Table_n_D_1_t1_im[497] = t1_im_497_2; + assign Direct_Lookup_Table_n_D_1_t1_im[498] = t1_im_498_2; + assign Direct_Lookup_Table_n_D_1_t1_im[499] = t1_im_499_2; + assign Direct_Lookup_Table_n_D_1_t1_im[500] = t1_im_500_2; + assign Direct_Lookup_Table_n_D_1_t1_im[501] = t1_im_501_2; + assign Direct_Lookup_Table_n_D_1_t1_im[502] = t1_im_502_2; + assign Direct_Lookup_Table_n_D_1_t1_im[503] = t1_im_503_2; + assign Direct_Lookup_Table_n_D_1_t1_im[504] = t1_im_504_2; + assign Direct_Lookup_Table_n_D_1_t1_im[505] = t1_im_505_2; + assign Direct_Lookup_Table_n_D_1_t1_im[506] = t1_im_506_2; + assign Direct_Lookup_Table_n_D_1_t1_im[507] = t1_im_507_2; + assign Direct_Lookup_Table_n_D_1_t1_im[508] = t1_im_508_2; + assign Direct_Lookup_Table_n_D_1_t1_im[509] = t1_im_509_2; + assign Direct_Lookup_Table_n_D_1_t1_im[510] = t1_im_510_2; + assign Direct_Lookup_Table_n_D_1_t1_im[511] = t1_im_511_2; + assign Direct_Lookup_Table_n_D_1_out1_re = Direct_Lookup_Table_n_D_1_t1_re[Data_Type_Conversion2_out1]; + assign Direct_Lookup_Table_n_D_1_out1_im = Direct_Lookup_Table_n_D_1_t1_im[Data_Type_Conversion2_out1]; + + + + // /Complex_Multiply + velocityControlHdl_Complex_Multiply u_Complex_Multiply (.In1_re(Direct_Lookup_Table_n_D_out1_re), // sfix18_En16 + .In1_im(Direct_Lookup_Table_n_D_out1_im), // sfix18_En16 + .In2_re(Direct_Lookup_Table_n_D_1_out1_re), // sfix18_En16 + .In2_im(Direct_Lookup_Table_n_D_1_out1_im), // sfix18_En16 + .Re(cos_coefficient), // sfix36_En32 + .Im(sin_coefficient) // sfix36_En32 + ); + + // /Data Type Conversion3 + assign sin_coefficient_1 = sin_coefficient[33:16]; + + + + assign sin = sin_coefficient_1; + + // /Data Type Conversion + assign cos_coefficient_1 = cos_coefficient[33:16]; + + + + assign cos = cos_coefficient_1; + +endmodule // velocityControlHdl_Sin_Cos1 + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Space_Vector_Modulation.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Space_Vector_Modulation.v new file mode 100644 index 000000000..052e875fa --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Space_Vector_Modulation.v @@ -0,0 +1,169 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Space_Vector_Modulation.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Space_Vector_Modulation +// Source Path: velocityControlHdl/Space_Vector_Modulation +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Space_Vector_Modulation + ( + Vabc_Raw_0, + Vabc_Raw_1, + Vabc_Raw_2, + phase_voltages_0, + phase_voltages_1, + phase_voltages_2 + ); + + + input signed [17:0] Vabc_Raw_0; // sfix18_En13 + input signed [17:0] Vabc_Raw_1; // sfix18_En13 + input signed [17:0] Vabc_Raw_2; // sfix18_En13 + output signed [19:0] phase_voltages_0; // sfix20_En12 + output signed [19:0] phase_voltages_1; // sfix20_En12 + output signed [19:0] phase_voltages_2; // sfix20_En12 + + + wire signed [17:0] Double_Range_out1_0; // sfix18_En12 + wire signed [17:0] Double_Range_out1_1; // sfix18_En12 + wire signed [17:0] Double_Range_out1_2; // sfix18_En12 + wire signed [17:0] MinMax1_out1; // sfix18_En12 + wire signed [17:0] MinMax_out1; // sfix18_En12 + wire signed [18:0] Add_add_cast; // sfix19_En12 + wire signed [18:0] Add_add_cast_1; // sfix19_En12 + wire signed [18:0] Add_out1; // sfix19_En12 + wire signed [37:0] Gain_cast; // sfix38_En30 + wire signed [18:0] Gain_out1; // sfix19_En12 + wire signed [19:0] Add1_sub_cast; // sfix20_En12 + wire signed [19:0] Add1_sub_cast_1; // sfix20_En12 + wire signed [19:0] Add1_out1; // sfix20_En12 + wire signed [19:0] Add2_sub_cast; // sfix20_En12 + wire signed [19:0] Add2_sub_cast_1; // sfix20_En12 + wire signed [19:0] Add2_out1; // sfix20_En12 + wire signed [19:0] Add3_sub_cast; // sfix20_En12 + wire signed [19:0] Add3_sub_cast_1; // sfix20_En12 + wire signed [19:0] Add3_out1; // sfix20_En12 + + + // /Double_Range + // + // /Demux + // + // /Goto + // + // /From + // + // /Goto1 + // + // /From1 + // + // /Goto2 + // + // /From2 + // + // /Demux + // + // /Goto + // + // /From6 + // + // /Demux + // + // /Goto + // + // /From3 + // + // /Goto1 + // + // /From7 + // + // /Goto1 + // + // /From4 + // + // /Goto2 + // + // /From8 + // + // /Goto2 + // + // /From5 + velocityControlHdl_Double_Range u_Double_Range (.In1_0(Vabc_Raw_0), // sfix18_En13 + .In1_1(Vabc_Raw_1), // sfix18_En13 + .In1_2(Vabc_Raw_2), // sfix18_En13 + .Out1_0(Double_Range_out1_0), // sfix18_En12 + .Out1_1(Double_Range_out1_1), // sfix18_En12 + .Out1_2(Double_Range_out1_2) // sfix18_En12 + ); + + // /MinMax1 + velocityControlHdl_MinMax1 u_MinMax1 (.in0(Double_Range_out1_0), // sfix18_En12 + .in1(Double_Range_out1_1), // sfix18_En12 + .in2(Double_Range_out1_2), // sfix18_En12 + .out0(MinMax1_out1) // sfix18_En12 + ); + + // /MinMax + velocityControlHdl_MinMax u_MinMax (.in0(Double_Range_out1_0), // sfix18_En12 + .in1(Double_Range_out1_1), // sfix18_En12 + .in2(Double_Range_out1_2), // sfix18_En12 + .out0(MinMax_out1) // sfix18_En12 + ); + + // /Add + assign Add_add_cast = MinMax1_out1; + assign Add_add_cast_1 = MinMax_out1; + assign Add_out1 = Add_add_cast + Add_add_cast_1; + + + + // /Gain + assign Gain_cast = {{2{Add_out1[18]}}, {Add_out1, 17'b00000000000000000}}; + assign Gain_out1 = Gain_cast[36:18]; + + + + // /Add1 + // + // /Mux + assign Add1_sub_cast = Double_Range_out1_0; + assign Add1_sub_cast_1 = Gain_out1; + assign Add1_out1 = Add1_sub_cast - Add1_sub_cast_1; + + + + assign phase_voltages_0 = Add1_out1; + + // /Add2 + assign Add2_sub_cast = Double_Range_out1_1; + assign Add2_sub_cast_1 = Gain_out1; + assign Add2_out1 = Add2_sub_cast - Add2_sub_cast_1; + + + + assign phase_voltages_1 = Add2_out1; + + // /Add3 + assign Add3_sub_cast = Double_Range_out1_2; + assign Add3_sub_cast_1 = Gain_out1; + assign Add3_out1 = Add3_sub_cast - Add3_sub_cast_1; + + + + assign phase_voltages_2 = Add3_out1; + +endmodule // velocityControlHdl_Space_Vector_Modulation + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Transform_ABC_to_dq.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Transform_ABC_to_dq.v new file mode 100644 index 000000000..3fd99b3f0 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Transform_ABC_to_dq.v @@ -0,0 +1,67 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Transform_ABC_to_dq.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Transform_ABC_to_dq +// Source Path: velocityControlHdl/Transform_ABC_to_dq +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Transform_ABC_to_dq + ( + phase_currents_0, + phase_currents_1, + sin_coefficient, + cos_coefficient, + d_current, + q_current + ); + + + input signed [17:0] phase_currents_0; // sfix18_En15 + input signed [17:0] phase_currents_1; // sfix18_En15 + input signed [17:0] sin_coefficient; // sfix18_En16 + input signed [17:0] cos_coefficient; // sfix18_En16 + output signed [17:0] d_current; // sfix18_En15 + output signed [17:0] q_current; // sfix18_En15 + + + wire signed [17:0] Clarke_Transform_out1; // sfix18_En13 + wire signed [17:0] Clarke_Transform_out2; // sfix18_En13 + wire signed [17:0] Park_Transform_out1; // sfix18_En15 + wire signed [17:0] Park_Transform_out2; // sfix18_En15 + + + // /Clarke_Transform + velocityControlHdl_Clarke_Transform u_Clarke_Transform (.phase_currents_0(phase_currents_0), // sfix18_En15 + .phase_currents_1(phase_currents_1), // sfix18_En15 + .alpha_current(Clarke_Transform_out1), // sfix18_En13 + .beta_current(Clarke_Transform_out2) // sfix18_En13 + ); + + // /Park_Transform + velocityControlHdl_Park_Transform u_Park_Transform (.sin_coefficient(sin_coefficient), // sfix18_En16 + .cos_coefficient(cos_coefficient), // sfix18_En16 + .alpha_current(Clarke_Transform_out1), // sfix18_En13 + .beta_current(Clarke_Transform_out2), // sfix18_En13 + .direct_current(Park_Transform_out1), // sfix18_En15 + .quadrature_current(Park_Transform_out2) // sfix18_En15 + ); + + assign d_current = Park_Transform_out1; + + assign q_current = Park_Transform_out2; + +endmodule // velocityControlHdl_Transform_ABC_to_dq + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_Transform_dq_to_ABC.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Transform_dq_to_ABC.v new file mode 100644 index 000000000..8b448cffb --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_Transform_dq_to_ABC.v @@ -0,0 +1,73 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Transform_dq_to_ABC.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_Transform_dq_to_ABC +// Source Path: velocityControlHdl/Transform_dq_to_ABC +// Hierarchy Level: 4 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_Transform_dq_to_ABC + ( + d, + q, + sin, + cos, + ABC_0, + ABC_1, + ABC_2 + ); + + + input signed [17:0] d; // sfix18_En12 + input signed [17:0] q; // sfix18_En12 + input signed [17:0] sin; // sfix18_En16 + input signed [17:0] cos; // sfix18_En16 + output signed [17:0] ABC_0; // sfix18_En13 + output signed [17:0] ABC_1; // sfix18_En13 + output signed [17:0] ABC_2; // sfix18_En13 + + + wire signed [17:0] Inverse_Park_Transform_out1; // sfix18_En10 + wire signed [17:0] Inverse_Park_Transform_out2; // sfix18_En10 + wire signed [17:0] Inverse_Clarke_Transform_out1_0; // sfix18_En13 + wire signed [17:0] Inverse_Clarke_Transform_out1_1; // sfix18_En13 + wire signed [17:0] Inverse_Clarke_Transform_out1_2; // sfix18_En13 + + + // /Inverse_Park_Transform + velocityControlHdl_Inverse_Park_Transform u_Inverse_Park_Transform (.direct_voltage(d), // sfix18_En12 + .quadrature_voltage(q), // sfix18_En12 + .sin_coefficient(sin), // sfix18_En16 + .cos_coefficient(cos), // sfix18_En16 + .alpha_voltage(Inverse_Park_Transform_out1), // sfix18_En10 + .beta_voltage(Inverse_Park_Transform_out2) // sfix18_En10 + ); + + // /Inverse_Clarke_Transform + velocityControlHdl_Inverse_Clarke_Transform u_Inverse_Clarke_Transform (.alpha_voltage(Inverse_Park_Transform_out1), // sfix18_En10 + .beta_voltage(Inverse_Park_Transform_out2), // sfix18_En10 + .phase_voltages_0(Inverse_Clarke_Transform_out1_0), // sfix18_En13 + .phase_voltages_1(Inverse_Clarke_Transform_out1_1), // sfix18_En13 + .phase_voltages_2(Inverse_Clarke_Transform_out1_2) // sfix18_En13 + ); + + assign ABC_0 = Inverse_Clarke_Transform_out1_0; + + assign ABC_1 = Inverse_Clarke_Transform_out1_1; + + assign ABC_2 = Inverse_Clarke_Transform_out1_2; + +endmodule // velocityControlHdl_Transform_dq_to_ABC + diff --git a/library/controllerperipheralhdladi_pcore/velocityControlHdl_velocityControlHdl.v b/library/controllerperipheralhdladi_pcore/velocityControlHdl_velocityControlHdl.v new file mode 100644 index 000000000..b14347908 --- /dev/null +++ b/library/controllerperipheralhdladi_pcore/velocityControlHdl_velocityControlHdl.v @@ -0,0 +1,160 @@ +// ------------------------------------------------------------- +// +// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_velocityControlHdl.v +// Created: 2014-08-25 21:11:09 +// +// Generated by MATLAB 8.2 and HDL Coder 3.3 +// +// ------------------------------------------------------------- + + +// ------------------------------------------------------------- +// +// Module: velocityControlHdl_velocityControlHdl +// Source Path: velocityControlHdl +// Hierarchy Level: 3 +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module velocityControlHdl_velocityControlHdl + ( + CLK_IN, + reset, + enb_1_2000_0, + reset_1, + command, + measured, + phase_currents_0, + phase_currents_1, + electrical_position, + param_velocity_p_gain, + param_velocity_i_gain, + param_current_p_gain, + param_current_i_gain, + phase_voltages_0, + phase_voltages_1, + phase_voltages_2, + dq_currents_0, + dq_currents_1 + ); + + + input CLK_IN; + input reset; + input enb_1_2000_0; + input reset_1; + input signed [17:0] command; // sfix18_En8 + input signed [17:0] measured; // sfix18_En8 + input signed [17:0] phase_currents_0; // sfix18_En15 + input signed [17:0] phase_currents_1; // sfix18_En15 + input signed [17:0] electrical_position; // sfix18_En14 + input signed [17:0] param_velocity_p_gain; // sfix18_En16 + input signed [17:0] param_velocity_i_gain; // sfix18_En15 + input signed [17:0] param_current_p_gain; // sfix18_En10 + input signed [17:0] param_current_i_gain; // sfix18_En2 + output signed [19:0] phase_voltages_0; // sfix20_En12 + output signed [19:0] phase_voltages_1; // sfix20_En12 + output signed [19:0] phase_voltages_2; // sfix20_En12 + output signed [17:0] dq_currents_0; // sfix18_En15 + output signed [17:0] dq_currents_1; // sfix18_En15 + + + wire signed [17:0] Control_Velocity_out1; // sfix18_En15 + wire signed [17:0] sin_coefficient; // sfix18_En16 + wire signed [17:0] cos_coefficient; // sfix18_En16 + wire signed [17:0] d_current; // sfix18_En15 + wire signed [17:0] q_current; // sfix18_En15 + wire signed [17:0] d_voltage; // sfix18_En12 + wire signed [17:0] q_voltage; // sfix18_En12 + wire signed [17:0] Transform_dq_to_ABC_out1_0; // sfix18_En13 + wire signed [17:0] Transform_dq_to_ABC_out1_1; // sfix18_En13 + wire signed [17:0] Transform_dq_to_ABC_out1_2; // sfix18_En13 + wire signed [19:0] Space_Vector_Modulation_out1_0; // sfix20_En12 + wire signed [19:0] Space_Vector_Modulation_out1_1; // sfix20_En12 + wire signed [19:0] Space_Vector_Modulation_out1_2; // sfix20_En12 + + // Velocity Control HDL + // + // Outer velocity control with inner loop current control. + + + // /Control_Velocity + velocityControlHdl_Control_Velocity u_Control_Velocity (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(reset_1), + .velocity_command(command), // sfix18_En8 + .velocity_measured(measured), // sfix18_En8 + .param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16 + .param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15 + .q_command(Control_Velocity_out1) // sfix18_En15 + ); + + // /Sin_Cos1 + velocityControlHdl_Sin_Cos1 u_Sin_Cos1 (.x(electrical_position), // sfix18_En14 + .sin(sin_coefficient), // sfix18_En16 + .cos(cos_coefficient) // sfix18_En16 + ); + + // /Transform_ABC_to_dq + // + // /Mux + velocityControlHdl_Transform_ABC_to_dq u_Transform_ABC_to_dq (.phase_currents_0(phase_currents_0), // sfix18_En15 + .phase_currents_1(phase_currents_1), // sfix18_En15 + .sin_coefficient(sin_coefficient), // sfix18_En16 + .cos_coefficient(cos_coefficient), // sfix18_En16 + .d_current(d_current), // sfix18_En15 + .q_current(q_current) // sfix18_En15 + ); + + // Linear Current Controllers + // + // PID Blocks used for Control Design of Current Loop controllers. + // + // /Control_DQ_Currents + velocityControlHdl_Control_DQ_Currents u_Control_DQ_Currents (.CLK_IN(CLK_IN), + .reset(reset), + .enb_1_2000_0(enb_1_2000_0), + .Reset_1(reset_1), + .q_current_command(Control_Velocity_out1), // sfix18_En15 + .d_current_measured(d_current), // sfix18_En15 + .q_current_measured(q_current), // sfix18_En15 + .param_current_p_gain(param_current_p_gain), // sfix18_En10 + .param_current_i_gain(param_current_i_gain), // sfix18_En2 + .d_voltage(d_voltage), // sfix18_En12 + .q_voltage(q_voltage) // sfix18_En12 + ); + + // /Transform_dq_to_ABC + velocityControlHdl_Transform_dq_to_ABC u_Transform_dq_to_ABC (.d(d_voltage), // sfix18_En12 + .q(q_voltage), // sfix18_En12 + .sin(sin_coefficient), // sfix18_En16 + .cos(cos_coefficient), // sfix18_En16 + .ABC_0(Transform_dq_to_ABC_out1_0), // sfix18_En13 + .ABC_1(Transform_dq_to_ABC_out1_1), // sfix18_En13 + .ABC_2(Transform_dq_to_ABC_out1_2) // sfix18_En13 + ); + + // /Space_Vector_Modulation + velocityControlHdl_Space_Vector_Modulation u_Space_Vector_Modulation (.Vabc_Raw_0(Transform_dq_to_ABC_out1_0), // sfix18_En13 + .Vabc_Raw_1(Transform_dq_to_ABC_out1_1), // sfix18_En13 + .Vabc_Raw_2(Transform_dq_to_ABC_out1_2), // sfix18_En13 + .phase_voltages_0(Space_Vector_Modulation_out1_0), // sfix20_En12 + .phase_voltages_1(Space_Vector_Modulation_out1_1), // sfix20_En12 + .phase_voltages_2(Space_Vector_Modulation_out1_2) // sfix20_En12 + ); + + assign phase_voltages_0 = Space_Vector_Modulation_out1_0; + + assign phase_voltages_1 = Space_Vector_Modulation_out1_1; + + assign phase_voltages_2 = Space_Vector_Modulation_out1_2; + + assign dq_currents_0 = d_current; + + assign dq_currents_1 = q_current; + +endmodule // velocityControlHdl_velocityControlHdl + diff --git a/projects/motor_control/common/motor_control_bd.tcl b/projects/motor_control/common/motor_control_bd.tcl index 9fecc3f6c..a248124ab 100755 --- a/projects/motor_control/common/motor_control_bd.tcl +++ b/projects/motor_control/common/motor_control_bd.tcl @@ -54,8 +54,9 @@ # additions to default configuration set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc - set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect + set_property -dict [list CONFIG.NUM_MI {17}] $axi_cpu_interconnect set_property -dict [ list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7 + set_property -dict [ list CONFIG.PCW_EN_CLK2_PORT {1} ] $sys_ps7 # current monitor 1 peripherals @@ -97,7 +98,7 @@ set axi_mc_controller [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 axi_mc_controller ] - set pid_controller [create_bd_cell -type ip -vlnv analog.com:user:ip_pid_controller:1.0 pid_controller] + set foc_controller [ create_bd_cell -type ip -vlnv analog.com:user:controllerperipheralhdladi_pcore:1.0 foc_controller ] set axi_controller_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_controller_dma] set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_controller_dma @@ -105,7 +106,41 @@ set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_controller_dma set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_controller_dma set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_controller_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_controller_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_controller_dma + + # controller ILA + set ila_controller [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_controller ] + set_property -dict [ list CONFIG.C_ADV_TRIGGER {true} ] $ila_controller + set_property -dict [ list CONFIG.C_DATA_DEPTH {8192} ] $ila_controller + set_property -dict [ list CONFIG.C_EN_STRG_QUAL {1} ] $ila_controller + set_property -dict [ list CONFIG.C_NUM_OF_PROBES {10} ] $ila_controller + set_property -dict [ list CONFIG.C_PROBE0_WIDTH {32} ] $ila_controller + set_property -dict [ list CONFIG.C_PROBE1_WIDTH {32} ] $ila_controller + set_property -dict [ list CONFIG.C_PROBE2_WIDTH {32} ] $ila_controller + set_property -dict [ list CONFIG.C_PROBE3_WIDTH {32} ] $ila_controller + set_property -dict [ list CONFIG.C_PROBE4_WIDTH {32} ] $ila_controller + set_property -dict [ list CONFIG.C_PROBE5_WIDTH {32} ] $ila_controller + set_property -dict [ list CONFIG.C_PROBE6_WIDTH {32} ] $ila_controller + set_property -dict [ list CONFIG.C_PROBE7_WIDTH {32} ] $ila_controller + set_property -dict [ list CONFIG.C_PROBE8_WIDTH {32} ] $ila_controller + set_property -dict [ list CONFIG.C_PROBE9_WIDTH {1} ] $ila_controller + set_property -dict [ list CONFIG.C_TRIGIN_EN {false} ] $ila_controller + + #adc_pack + set util_adc_pack_0 [ create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack_0 ] + set_property -dict [ list CONFIG.DATA_WIDTH {32} ] $util_adc_pack_0 + + # slice0 + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] + set_property -dict [ list CONFIG.DIN_FROM {2} CONFIG.DIN_TO {2} CONFIG.DIN_WIDTH {3} ] $xlslice_0 + + # slice1 + set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] + set_property -dict [ list CONFIG.DIN_FROM {1} CONFIG.DIN_TO {1} CONFIG.DIN_WIDTH {3} ] $xlslice_1 + + # slice2 + set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] + set_property -dict [ list CONFIG.DIN_FROM {0} CONFIG.DIN_TO {0} CONFIG.DIN_WIDTH {3} ] $xlslice_2 # xadc @@ -129,27 +164,32 @@ # position - connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i] [get_bd_pins axi_mc_speed_1/bemf_i] + connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i] + connect_bd_net -net position_i_1 [get_bd_pins axi_mc_speed_1/bemf_i] # current monitor 1 connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/ref_clk] $sys_100m_clk_source - connect_bd_net -net adc_ia_dat_i_1 [get_bd_ports adc_ia_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ia_dat_i] - connect_bd_net -net adc_ib_dat_i_1 [get_bd_ports adc_ib_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ib_dat_i] - connect_bd_net -net adc_it_dat_i_1 [get_bd_ports adc_it_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_it_dat_i] + connect_bd_net -net adc_ia_dat_i_1 [get_bd_ports adc_ia_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ia_dat_i] + connect_bd_net -net adc_ib_dat_i_1 [get_bd_ports adc_ib_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ib_dat_i] + connect_bd_net -net adc_it_dat_i_1 [get_bd_ports adc_it_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_it_dat_i] connect_bd_net -net adc_vbus_dat_i_1 [get_bd_ports adc_vbus_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_dat_i] - connect_bd_net -net axi_mc_current_monitor_1_adc_ia_clk_o [get_bd_ports adc_ia_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ia_clk_o] - connect_bd_net -net axi_mc_current_monitor_1_adc_ib_clk_o [get_bd_ports adc_ib_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ib_clk_o] - connect_bd_net -net axi_mc_current_monitor_1_adc_it_clk_o [get_bd_ports adc_it_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_it_clk_o] + connect_bd_net -net axi_mc_current_monitor_1_adc_ia_clk_o [get_bd_ports adc_ia_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ia_clk_o] + connect_bd_net -net axi_mc_current_monitor_1_adc_ib_clk_o [get_bd_ports adc_ib_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ib_clk_o] + connect_bd_net -net axi_mc_current_monitor_1_adc_it_clk_o [get_bd_ports adc_it_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_it_clk_o] connect_bd_net -net axi_mc_current_monitor_1_adc_vbus_clk_o [get_bd_ports adc_vbus_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_clk_o] - connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins axi_mc_current_monitor_1/adc_clk_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_clk] - connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins axi_mc_current_monitor_1/adc_dwr_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_en] - connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins axi_mc_current_monitor_1/adc_ddata_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_din] - connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins axi_mc_current_monitor_1/adc_dsync_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_sync] - connect_bd_net -net axi_mc_current_monitor_1_adc_dovf [get_bd_pins axi_mc_current_monitor_1/adc_dovf_i] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_overflow] + connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins axi_mc_current_monitor_1/adc_clk_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_clk] + connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins axi_mc_current_monitor_1/adc_dwr_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_en] + connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins axi_mc_current_monitor_1/adc_ddata_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_din] + connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins axi_mc_current_monitor_1/adc_dsync_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_sync] + connect_bd_net -net axi_mc_current_monitor_1_adc_dovf [get_bd_pins axi_mc_current_monitor_1/adc_dovf_i] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_overflow] + + connect_bd_net -net axi_mc_current_monitor_1_ia_o [get_bd_pins axi_mc_current_monitor_1/ia_o] [get_bd_pins foc_controller/adc_current1] + connect_bd_net -net axi_mc_current_monitor_1_ib_o [get_bd_pins axi_mc_current_monitor_1/ib_o] [get_bd_pins foc_controller/adc_current2] + connect_bd_net -net axi_mc_current_monitor_1_i_ready_o [get_bd_pins axi_mc_controller/ctrl_data_valid_i] [get_bd_pins axi_mc_current_monitor_1/i_ready_o] # interrupt @@ -166,11 +206,11 @@ connect_bd_net -net adc_it_dat_d_i [get_bd_ports adc_it_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_it_dat_i] connect_bd_net -net axi_mc_current_monitor_2_adc_it_clk_o [get_bd_ports adc_it_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_it_clk_o] - connect_bd_net -net axi_mc_current_monitor_2_adc_clk [get_bd_pins axi_mc_current_monitor_2/adc_clk_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_clk] - connect_bd_net -net axi_mc_current_monitor_2_adc_dwr [get_bd_pins axi_mc_current_monitor_2/adc_dwr_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_en] - connect_bd_net -net axi_mc_current_monitor_2_adc_ddata [get_bd_pins axi_mc_current_monitor_2/adc_ddata_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_din] - connect_bd_net -net axi_mc_current_monitor_2_adc_dsync [get_bd_pins axi_mc_current_monitor_2/adc_dsync_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_sync] - connect_bd_net -net axi_mc_current_monitor_2_adc_dovf [get_bd_pins axi_mc_current_monitor_2/adc_dovf_i] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_overflow] + connect_bd_net -net axi_mc_current_monitor_2_adc_clk [get_bd_pins axi_mc_current_monitor_2/adc_clk_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_clk] + connect_bd_net -net axi_mc_current_monitor_2_adc_dwr [get_bd_pins axi_mc_current_monitor_2/adc_dwr_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_en] + connect_bd_net -net axi_mc_current_monitor_2_adc_ddata [get_bd_pins axi_mc_current_monitor_2/adc_ddata_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_din] + connect_bd_net -net axi_mc_current_monitor_2_adc_dsync [get_bd_pins axi_mc_current_monitor_2/adc_dsync_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_sync] + connect_bd_net -net axi_mc_current_monitor_2_adc_dovf [get_bd_pins axi_mc_current_monitor_2/adc_dovf_i] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_overflow] #interrupt @@ -180,13 +220,10 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/ref_clk] $sys_100m_clk_source - connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o] - connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o] [get_bd_pins axi_mc_controller/position_i] - connect_bd_net -net axi_mc_speed_1_new_speed_o [get_bd_pins axi_mc_speed_1/new_speed_o] - connect_bd_net -net axi_mc_speed_1_new_speed_o [get_bd_pins axi_mc_speed_1/new_speed_o] [get_bd_pins pid_controller/new_motor_speed] - connect_bd_net -net axi_mc_speed_1_speed_o [get_bd_pins axi_mc_speed_1/speed_o] - connect_bd_net -net axi_mc_speed_1_speed_o [get_bd_pins axi_mc_speed_1/speed_o] [get_bd_pins pid_controller/motor_speed] [get_bd_pins axi_mc_controller/new_speed_i] - + connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o] [get_bd_pins axi_mc_controller/position_i] + connect_bd_net -net axi_mc_speed_1_new_speed_o [get_bd_pins axi_mc_speed_1/new_speed_o] + connect_bd_net -net axi_mc_speed_1_speed_o [get_bd_pins axi_mc_speed_1/speed_o] + connect_bd_net -net speed_detector_adc_clk [get_bd_pins axi_mc_speed_1/adc_clk_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_clk] connect_bd_net -net speed_detector_adc_dwr [get_bd_pins axi_mc_speed_1/adc_dwr_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_en] connect_bd_net -net speed_detector_adc_ddata [get_bd_pins axi_mc_speed_1/adc_ddata_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_din] @@ -199,33 +236,83 @@ # controller connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_controller/ref_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_controller/ctrl_data_clk] $sys_100m_clk_source - connect_bd_net -net axi_mc_controller_fmc_m1_en_o [get_bd_ports fmc_m1_en_o] [get_bd_pins axi_mc_controller/fmc_m1_en_o] - connect_bd_net -net axi_mc_controller_pwm_al_o [get_bd_ports pwm_al_o] [get_bd_pins axi_mc_controller/pwm_al_o] - connect_bd_net -net axi_mc_controller_pwm_ah_o [get_bd_ports pwm_ah_o] [get_bd_pins axi_mc_controller/pwm_ah_o] - connect_bd_net -net axi_mc_controller_pwm_cl_o [get_bd_ports pwm_cl_o] [get_bd_pins axi_mc_controller/pwm_cl_o] - connect_bd_net -net axi_mc_controller_pwm_ch_o [get_bd_ports pwm_ch_o] [get_bd_pins axi_mc_controller/pwm_ch_o] - connect_bd_net -net axi_mc_controller_pwm_bl_o [get_bd_ports pwm_bl_o] [get_bd_pins axi_mc_controller/pwm_bl_o] - connect_bd_net -net axi_mc_controller_pwm_bh_o [get_bd_ports pwm_bh_o] [get_bd_pins axi_mc_controller/pwm_bh_o] - connect_bd_net -net axi_mc_controller_gpo_o [get_bd_ports gpo_o] [get_bd_pins axi_mc_controller/gpo_o] - connect_bd_net -net axi_mc_controller_sensors_o [get_bd_pins axi_mc_controller/sensors_o] [get_bd_pins axi_mc_speed_1/hall_bemf_i] - connect_bd_net -net axi_mc_controller_fault [get_bd_pins /axi_mc_controller/fmc_m1_fault_i] [get_bd_ports /fmc_m1_fault_i] + connect_bd_net -net axi_mc_controller_fmc_m1_en_o [get_bd_ports fmc_m1_en_o] [get_bd_pins axi_mc_controller/fmc_m1_en_o] + connect_bd_net -net axi_mc_controller_pwm_al_o [get_bd_ports pwm_al_o] [get_bd_pins axi_mc_controller/pwm_al_o] + connect_bd_net -net axi_mc_controller_pwm_ah_o [get_bd_ports pwm_ah_o] [get_bd_pins axi_mc_controller/pwm_ah_o] + connect_bd_net -net axi_mc_controller_pwm_cl_o [get_bd_ports pwm_cl_o] [get_bd_pins axi_mc_controller/pwm_cl_o] + connect_bd_net -net axi_mc_controller_pwm_ch_o [get_bd_ports pwm_ch_o] [get_bd_pins axi_mc_controller/pwm_ch_o] + connect_bd_net -net axi_mc_controller_pwm_bl_o [get_bd_ports pwm_bl_o] [get_bd_pins axi_mc_controller/pwm_bl_o] + connect_bd_net -net axi_mc_controller_pwm_bh_o [get_bd_ports pwm_bh_o] [get_bd_pins axi_mc_controller/pwm_bh_o] + connect_bd_net -net axi_mc_controller_gpo_o [get_bd_ports gpo_o] [get_bd_pins axi_mc_controller/gpo_o] + connect_bd_net -net axi_mc_controller_sensors_o [get_bd_pins axi_mc_controller/sensors_o] [get_bd_pins axi_mc_speed_1/hall_bemf_i] + connect_bd_net -net axi_mc_controller_fault [get_bd_pins /axi_mc_controller/fmc_m1_fault_i] [get_bd_ports /fmc_m1_fault_i] - connect_bd_net -net axi_mc_controller_adc_clk [get_bd_pins axi_mc_controller/adc_clk_o] [get_bd_pins axi_controller_dma/fifo_wr_clk] - connect_bd_net -net axi_mc_controller_adc_dwr [get_bd_pins axi_mc_controller/adc_dwr_o] [get_bd_pins axi_controller_dma/fifo_wr_en] - connect_bd_net -net axi_mc_controller_adc_ddata [get_bd_pins axi_mc_controller/adc_ddata_o] [get_bd_pins axi_controller_dma/fifo_wr_din] - connect_bd_net -net axi_mc_controller_adc_dovf [get_bd_pins axi_mc_controller/adc_dovf_i] [get_bd_pins axi_controller_dma/fifo_wr_overflow] + connect_bd_net -net axi_mc_controller_adc_clk_o [get_bd_pins axi_mc_controller/adc_clk_o] [get_bd_pins util_adc_pack_0/clk] + connect_bd_net -net axi_mc_controller_adc_data_c0 [get_bd_pins axi_mc_controller/adc_data_c0] [get_bd_pins util_adc_pack_0/chan_data_0] + connect_bd_net -net axi_mc_controller_adc_data_c1 [get_bd_pins axi_mc_controller/adc_data_c1] [get_bd_pins util_adc_pack_0/chan_data_1] + connect_bd_net -net axi_mc_controller_adc_data_c2 [get_bd_pins axi_mc_controller/adc_data_c2] [get_bd_pins util_adc_pack_0/chan_data_2] + connect_bd_net -net axi_mc_controller_adc_data_c3 [get_bd_pins axi_mc_controller/adc_data_c3] [get_bd_pins util_adc_pack_0/chan_data_3] + connect_bd_net -net axi_mc_controller_adc_data_c4 [get_bd_pins axi_mc_controller/adc_data_c4] [get_bd_pins util_adc_pack_0/chan_data_4] + connect_bd_net -net axi_mc_controller_adc_data_c5 [get_bd_pins axi_mc_controller/adc_data_c5] [get_bd_pins util_adc_pack_0/chan_data_5] + connect_bd_net -net axi_mc_controller_adc_data_c6 [get_bd_pins axi_mc_controller/adc_data_c6] [get_bd_pins util_adc_pack_0/chan_data_6] + connect_bd_net -net axi_mc_controller_adc_data_c7 [get_bd_pins axi_mc_controller/adc_data_c7] [get_bd_pins util_adc_pack_0/chan_data_7] + connect_bd_net -net axi_mc_controller_adc_enable_c0 [get_bd_pins axi_mc_controller/adc_enable_c0] [get_bd_pins util_adc_pack_0/chan_enable_0] + connect_bd_net -net axi_mc_controller_adc_enable_c1 [get_bd_pins axi_mc_controller/adc_enable_c1] [get_bd_pins util_adc_pack_0/chan_enable_1] + connect_bd_net -net axi_mc_controller_adc_enable_c2 [get_bd_pins axi_mc_controller/adc_enable_c2] [get_bd_pins util_adc_pack_0/chan_enable_2] + connect_bd_net -net axi_mc_controller_adc_enable_c3 [get_bd_pins axi_mc_controller/adc_enable_c3] [get_bd_pins util_adc_pack_0/chan_enable_3] + connect_bd_net -net axi_mc_controller_adc_enable_c4 [get_bd_pins axi_mc_controller/adc_enable_c4] [get_bd_pins util_adc_pack_0/chan_enable_4] + connect_bd_net -net axi_mc_controller_adc_enable_c5 [get_bd_pins axi_mc_controller/adc_enable_c5] [get_bd_pins util_adc_pack_0/chan_enable_5] + connect_bd_net -net axi_mc_controller_adc_enable_c6 [get_bd_pins axi_mc_controller/adc_enable_c6] [get_bd_pins util_adc_pack_0/chan_enable_6] + connect_bd_net -net axi_mc_controller_adc_enable_c7 [get_bd_pins axi_mc_controller/adc_enable_c7] [get_bd_pins util_adc_pack_0/chan_enable_7] + connect_bd_net -net axi_mc_controller_adc_valid_c0 [get_bd_pins axi_mc_controller/adc_valid_c0] [get_bd_pins util_adc_pack_0/chan_valid_0] + connect_bd_net -net axi_mc_controller_adc_valid_c1 [get_bd_pins axi_mc_controller/adc_valid_c1] [get_bd_pins util_adc_pack_0/chan_valid_1] + connect_bd_net -net axi_mc_controller_adc_valid_c2 [get_bd_pins axi_mc_controller/adc_valid_c2] [get_bd_pins util_adc_pack_0/chan_valid_2] + connect_bd_net -net axi_mc_controller_adc_valid_c3 [get_bd_pins axi_mc_controller/adc_valid_c3] [get_bd_pins util_adc_pack_0/chan_valid_3] + connect_bd_net -net axi_mc_controller_adc_valid_c4 [get_bd_pins axi_mc_controller/adc_valid_c4] [get_bd_pins util_adc_pack_0/chan_valid_4] + connect_bd_net -net axi_mc_controller_adc_valid_c5 [get_bd_pins axi_mc_controller/adc_valid_c5] [get_bd_pins util_adc_pack_0/chan_valid_5] + connect_bd_net -net axi_mc_controller_adc_valid_c6 [get_bd_pins axi_mc_controller/adc_valid_c6] [get_bd_pins util_adc_pack_0/chan_valid_6] + connect_bd_net -net axi_mc_controller_adc_valid_c7 [get_bd_pins axi_mc_controller/adc_valid_c7] [get_bd_pins util_adc_pack_0/chan_valid_7] - connect_bd_net -net sys_100m_clk [get_bd_pins pid_controller/clk] + connect_bd_net -net axi_mc_controller_adc_clk_o [get_bd_pins axi_controller_dma/fifo_wr_clk] + connect_bd_net -net axi_mc_controller_adc_ddata [get_bd_pins axi_controller_dma/fifo_wr_din] [get_bd_pins util_adc_pack_0/ddata] + connect_bd_net -net axi_mc_controller_adc_dovf [get_bd_pins axi_controller_dma/fifo_wr_overflow] [get_bd_pins axi_mc_controller/adc_dovf_i] + connect_bd_net -net axi_mc_controller_adc_dwr [get_bd_pins axi_controller_dma/fifo_wr_en] [get_bd_pins util_adc_pack_0/dvalid] + connect_bd_net -net util_adc_pack_0_dsync [get_bd_pins axi_controller_dma/fifo_wr_sync] [get_bd_pins util_adc_pack_0/dsync] - connect_bd_net -net axi_mc_controller_ctrl_rst_o [get_bd_pins axi_mc_controller/ctrl_rst_o] [get_bd_pins pid_controller/rst] - connect_bd_net -net axi_mc_controller_err_i [get_bd_pins axi_mc_controller/err_i] [get_bd_pins pid_controller/err] - connect_bd_net -net axi_mc_controller_pwm_i [get_bd_pins axi_mc_controller/pwm_i] [get_bd_pins pid_controller/pwm] - connect_bd_net -net axi_mc_controller_speed_rpm_i [get_bd_pins axi_mc_controller/speed_rpm_i] [get_bd_pins pid_controller/speed] - connect_bd_net -net axi_mc_controller_ref_speed_o [get_bd_pins axi_mc_controller/ref_speed_o] [get_bd_pins pid_controller/ref_speed] - connect_bd_net -net axi_mc_controller_kp_o [get_bd_pins axi_mc_controller/kp_o] [get_bd_pins pid_controller/kp] - connect_bd_net -net axi_mc_controller_ki_o [get_bd_pins axi_mc_controller/ki_o] [get_bd_pins pid_controller/ki] - connect_bd_net -net axi_mc_controller_kd_o [get_bd_pins axi_mc_controller/kd_o] [get_bd_pins pid_controller/kd] + #foc_controller + connect_bd_net -net sys_100m_clk [get_bd_pins foc_controller/AXI_Lite_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_ps7_FCLK_CLK2 [get_bd_pins foc_controller/IPCORE_CLK] [get_bd_pins sys_ps7/FCLK_CLK2] + + connect_bd_net -net sys_100m_resetn [get_bd_pins foc_controller/AXI_Lite_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins foc_controller/IPCORE_RESETN] $sys_100m_resetn_source + + connect_bd_net -net foc_controller_mon_d_current [get_bd_pins axi_mc_controller/ctrl_data6_i] + connect_bd_net -net foc_controller_mon_d_current [get_bd_pins foc_controller/mon_d_current] + + connect_bd_net -net foc_controller_pwm_a [get_bd_pins axi_mc_controller/pwm_a_i] [get_bd_pins foc_controller/pwm_a] + connect_bd_net -net foc_controller_pwm_b [get_bd_pins axi_mc_controller/pwm_b_i] [get_bd_pins foc_controller/pwm_b] + connect_bd_net -net foc_controller_pwm_c [get_bd_pins axi_mc_controller/pwm_c_i] [get_bd_pins foc_controller/pwm_c] + connect_bd_net -net xlslice_0_Dout [get_bd_pins foc_controller/encoder_a] [get_bd_pins xlslice_0/Dout] + connect_bd_net -net xlslice_1_Dout [get_bd_pins foc_controller/encoder_b] [get_bd_pins xlslice_1/Dout] + connect_bd_net -net xlslice_2_Dout [get_bd_pins foc_controller/encoder_index] [get_bd_pins xlslice_2/Dout] + connect_bd_net -net position_i_1 [get_bd_pins xlslice_1/Din] + connect_bd_net -net position_i_1 [get_bd_pins xlslice_0/Din] + connect_bd_net -net position_i_1 [get_bd_pins xlslice_2/Din] + + #ILA + connect_bd_net -net sys_100m_clk [get_bd_pins ila_controller/clk] $sys_100m_clk_source + connect_bd_net -net foc_controller_mon_phase_voltage_a [get_bd_pins axi_mc_controller/ctrl_data0_i] [get_bd_pins foc_controller/mon_phase_voltage_a] [get_bd_pins ila_controller/probe0] + connect_bd_net -net foc_controller_mon_phase_voltage_b [get_bd_pins axi_mc_controller/ctrl_data1_i] [get_bd_pins foc_controller/mon_phase_voltage_b] [get_bd_pins ila_controller/probe1] + connect_bd_net -net foc_controller_mon_phase_current_a [get_bd_pins axi_mc_controller/ctrl_data2_i] [get_bd_pins foc_controller/mon_phase_current_a] [get_bd_pins ila_controller/probe2] + connect_bd_net -net foc_controller_mon_phase_current_b [get_bd_pins axi_mc_controller/ctrl_data3_i] [get_bd_pins foc_controller/mon_phase_current_b] [get_bd_pins ila_controller/probe3] + connect_bd_net -net foc_controller_mon_rotor_position [get_bd_pins foc_controller/mon_rotor_position] [get_bd_pins ila_controller/probe4] + connect_bd_net -net foc_controller_mon_electrical_position [get_bd_pins axi_mc_controller/ctrl_data4_i] [get_bd_pins foc_controller/mon_electrical_position] [get_bd_pins ila_controller/probe5] + connect_bd_net -net foc_controller_mon_rotor_velocity [get_bd_pins axi_mc_controller/ctrl_data5_i] [get_bd_pins foc_controller/mon_rotor_velocity] [get_bd_pins ila_controller/probe6] + connect_bd_net -net foc_controller_mon_d_current [get_bd_pins ila_controller/probe7] + connect_bd_net -net foc_controller_mon_q_current [get_bd_pins axi_mc_controller/ctrl_data7_i] [get_bd_pins foc_controller/mon_q_current] [get_bd_pins ila_controller/probe8] + connect_bd_net -net axi_mc_current_monitor_1_i_ready_o [get_bd_pins ila_controller/probe9] # interrupt @@ -255,6 +342,7 @@ connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_controller_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m16_axi [get_bd_intf_pins axi_cpu_interconnect/M16_AXI] [get_bd_intf_pins foc_controller/AXI_Lite] connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source @@ -265,6 +353,7 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M16_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source @@ -275,6 +364,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M16_ARESETN] $sys_100m_resetn_source #inteconnects (current monitor 1) @@ -345,15 +435,16 @@ # address map - create_bd_addr_seg -range 0x10000 -offset 0x40400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_1_dma/s_axi/axi_lite] SEG_data_c_m_1_dma - create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs axi_speed_detector_dma/s_axi/axi_lite] SEG_data_s_d_dma - create_bd_addr_seg -range 0x10000 -offset 0x40420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_controller_dma/s_axi/axi_lite] SEG_data_t_c_dma - create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_2_dma/s_axi/axi_lite] SEG_data_c_m_2_dma - create_bd_addr_seg -range 0x10000 -offset 0x40500000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_1/s_axi/axi_lite] SEG_data_c_m_1 - create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d - create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c - create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2 - create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc + create_bd_addr_seg -range 0x10000 -offset 0x40400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_1_dma/s_axi/axi_lite] SEG_data_c_m_1_dma + create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs axi_speed_detector_dma/s_axi/axi_lite] SEG_data_s_d_dma + create_bd_addr_seg -range 0x10000 -offset 0x40420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_controller_dma/s_axi/axi_lite] SEG_data_t_c_dma + create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_2_dma/s_axi/axi_lite] SEG_data_c_m_2_dma + create_bd_addr_seg -range 0x10000 -offset 0x40500000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_1/s_axi/axi_lite] SEG_data_c_m_1 + create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d + create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c + create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2 + create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc + create_bd_addr_seg -range 0x4000000 -offset 0x7C000000 $sys_addr_cntrl_space [get_bd_addr_segs foc_controller/AXI_Lite/reg0] SEG_foc_controller_reg0 create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_speed_detector_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm diff --git a/projects/motor_control/zed/system_constr.xdc b/projects/motor_control/zed/system_constr.xdc index 9b1e7f2b7..e122d9f3f 100755 --- a/projects/motor_control/zed/system_constr.xdc +++ b/projects/motor_control/zed/system_constr.xdc @@ -110,3 +110,10 @@ set_property PACKAGE_PIN M12 [get_ports vn_in] set_property IOSTANDARD LVCMOS25 [get_ports vn_in] set_property PACKAGE_PIN L11 [get_ports vp_in] set_property IOSTANDARD LVCMOS25 [get_ports vp_in] + + +create_clock -name ctrl_clk -period 20.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] +create_clock -name ps7_clk_2 -period 20.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]] + +set_clock_groups -asynchronous -group {ctrl_clk} +set_clock_groups -asynchronous -group {ps7_clk_2}