fmcomms1: Commit AC701 and VC707 projects
Adrian Costina
parent
c718169f27
commit
d0f04fd788
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source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl
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source ../common/fmcomms1_bd.tcl
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# reference
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set_property IOSTANDARD LVDS_25 [get_ports ref_clk_out_p]
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set_property DIFF_TERM TRUE [get_ports ref_clk_out_p]
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set_property PACKAGE_PIN J21 [get_ports ref_clk_out_n]
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set_property IOSTANDARD LVDS_25 [get_ports ref_clk_out_n]
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set_property DIFF_TERM TRUE [get_ports ref_clk_out_n]
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# dac
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set_property IOSTANDARD LVDS_25 [get_ports dac_clk_in_p]
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set_property DIFF_TERM TRUE [get_ports dac_clk_in_p]
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set_property PACKAGE_PIN C19 [get_ports dac_clk_in_n]
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set_property IOSTANDARD LVDS_25 [get_ports dac_clk_in_n]
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set_property DIFF_TERM TRUE [get_ports dac_clk_in_n]
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set_property IOSTANDARD LVDS_25 [get_ports dac_clk_out_p]
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set_property PACKAGE_PIN H19 [get_ports dac_clk_out_n]
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set_property IOSTANDARD LVDS_25 [get_ports dac_clk_out_n]
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set_property IOSTANDARD LVDS_25 [get_ports dac_frame_out_p]
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set_property PACKAGE_PIN A19 [get_ports dac_frame_out_n]
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set_property IOSTANDARD LVDS_25 [get_ports dac_frame_out_n]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[0]}]
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set_property PACKAGE_PIN G26 [get_ports {dac_data_out_n[0]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[0]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[1]}]
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set_property PACKAGE_PIN F25 [get_ports {dac_data_out_n[1]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[1]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[2]}]
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set_property PACKAGE_PIN D25 [get_ports {dac_data_out_n[2]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[2]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[3]}]
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set_property PACKAGE_PIN K23 [get_ports {dac_data_out_n[3]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[3]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[4]}]
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set_property PACKAGE_PIN D26 [get_ports {dac_data_out_n[4]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[4]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[5]}]
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set_property PACKAGE_PIN F24 [get_ports {dac_data_out_n[5]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[5]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[6]}]
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set_property PACKAGE_PIN H18 [get_ports {dac_data_out_n[6]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[6]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[7]}]
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set_property PACKAGE_PIN F22 [get_ports {dac_data_out_n[7]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[7]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[8]}]
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set_property PACKAGE_PIN L18 [get_ports {dac_data_out_n[8]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[8]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[9]}]
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set_property PACKAGE_PIN E23 [get_ports {dac_data_out_n[9]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[9]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[10]}]
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set_property PACKAGE_PIN H24 [get_ports {dac_data_out_n[10]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[10]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[11]}]
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set_property PACKAGE_PIN J20 [get_ports {dac_data_out_n[11]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[11]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[12]}]
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set_property PACKAGE_PIN L14 [get_ports {dac_data_out_n[12]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[12]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[13]}]
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set_property PACKAGE_PIN M17 [get_ports {dac_data_out_n[13]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[13]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[14]}]
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set_property PACKAGE_PIN A22 [get_ports {dac_data_out_n[14]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[14]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[15]}]
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set_property PACKAGE_PIN D21 [get_ports {dac_data_out_n[15]}]
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set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[15]}]
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# adc
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set_property IOSTANDARD LVDS_25 [get_ports adc_clk_in_p]
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set_property DIFF_TERM TRUE [get_ports adc_clk_in_p]
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set_property PACKAGE_PIN H22 [get_ports adc_clk_in_n]
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set_property IOSTANDARD LVDS_25 [get_ports adc_clk_in_n]
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set_property DIFF_TERM TRUE [get_ports adc_clk_in_n]
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set_property IOSTANDARD LVDS_25 [get_ports adc_or_in_p]
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set_property DIFF_TERM TRUE [get_ports adc_or_in_p]
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set_property PACKAGE_PIN C18 [get_ports adc_or_in_n]
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set_property IOSTANDARD LVDS_25 [get_ports adc_or_in_n]
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set_property DIFF_TERM TRUE [get_ports adc_or_in_n]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[0]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[0]}]
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set_property PACKAGE_PIN G21 [get_ports {adc_data_in_n[0]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[0]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[0]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[1]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[1]}]
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set_property PACKAGE_PIN B21 [get_ports {adc_data_in_n[1]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[1]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[1]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[2]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[2]}]
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set_property PACKAGE_PIN A20 [get_ports {adc_data_in_n[2]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[2]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[2]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[3]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[3]}]
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set_property PACKAGE_PIN F17 [get_ports {adc_data_in_n[3]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[3]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[3]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[4]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[4]}]
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set_property PACKAGE_PIN F15 [get_ports {adc_data_in_n[4]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[4]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[4]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[5]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[5]}]
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set_property PACKAGE_PIN A18 [get_ports {adc_data_in_n[5]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[5]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[5]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[6]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[6]}]
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set_property PACKAGE_PIN D20 [get_ports {adc_data_in_n[6]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[6]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[6]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[7]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[7]}]
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set_property PACKAGE_PIN G16 [get_ports {adc_data_in_n[7]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[7]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[7]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[8]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[8]}]
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set_property PACKAGE_PIN H15 [get_ports {adc_data_in_n[8]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[8]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[8]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[9]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[9]}]
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set_property PACKAGE_PIN F19 [get_ports {adc_data_in_n[9]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[9]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[9]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[10]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[10]}]
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set_property PACKAGE_PIN D16 [get_ports {adc_data_in_n[10]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[10]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[10]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[11]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[11]}]
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set_property PACKAGE_PIN B17 [get_ports {adc_data_in_n[11]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[11]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[11]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[12]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[12]}]
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set_property PACKAGE_PIN F20 [get_ports {adc_data_in_n[12]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[12]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[12]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[13]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[13]}]
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set_property PACKAGE_PIN E18 [get_ports {adc_data_in_n[13]}]
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set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[13]}]
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set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[13]}]
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# clocks
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create_clock -period 2.000 -name dac_clk_in [get_ports dac_clk_in_p]
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create_clock -period 4.000 -name adc_clk_in [get_ports adc_clk_in_p]
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create_clock -period 8.000 -name dac_div_clk [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
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create_clock -period 4.000 -name adc_clk [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
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create_clock -period 33.33 -name ref_clk [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out2]
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create_clock -period 8.000 -name ila_clk [get_pins i_system_wrapper/system_i/ila_clkgen/clk_out1]
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set_clock_groups -asynchronous -group dac_div_clk
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set_clock_groups -asynchronous -group adc_clk
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set_clock_groups -asynchronous -group ref_clk
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set_clock_groups -asynchronous -group ila_clk
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@ -0,0 +1,15 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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adi_project_create fmcomms1_ac701
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adi_project_files fmcomms1_ac701 [list \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ]
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adi_project_run fmcomms1_ac701
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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uart_sin,
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uart_sout,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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ddr3_ras_n,
|
||||||
|
ddr3_reset_n,
|
||||||
|
ddr3_we_n,
|
||||||
|
|
||||||
|
phy_reset_n,
|
||||||
|
phy_mdc,
|
||||||
|
phy_mdio,
|
||||||
|
phy_tx_clk,
|
||||||
|
phy_tx_ctrl,
|
||||||
|
phy_tx_data,
|
||||||
|
phy_rx_clk,
|
||||||
|
phy_rx_ctrl,
|
||||||
|
phy_rx_data,
|
||||||
|
|
||||||
|
fan_pwm,
|
||||||
|
|
||||||
|
gpio_lcd,
|
||||||
|
gpio_led,
|
||||||
|
gpio_sw,
|
||||||
|
|
||||||
|
iic_rstn,
|
||||||
|
iic_scl,
|
||||||
|
iic_sda,
|
||||||
|
|
||||||
|
dac_clk_in_p,
|
||||||
|
dac_clk_in_n,
|
||||||
|
dac_clk_out_p,
|
||||||
|
dac_clk_out_n,
|
||||||
|
dac_frame_out_p,
|
||||||
|
dac_frame_out_n,
|
||||||
|
dac_data_out_p,
|
||||||
|
dac_data_out_n,
|
||||||
|
|
||||||
|
adc_clk_in_p,
|
||||||
|
adc_clk_in_n,
|
||||||
|
adc_or_in_p,
|
||||||
|
adc_or_in_n,
|
||||||
|
adc_data_in_p,
|
||||||
|
adc_data_in_n,
|
||||||
|
|
||||||
|
ref_clk_out_p,
|
||||||
|
ref_clk_out_n,
|
||||||
|
|
||||||
|
hdmi_out_clk,
|
||||||
|
hdmi_hsync,
|
||||||
|
hdmi_vsync,
|
||||||
|
hdmi_data_e,
|
||||||
|
hdmi_data,
|
||||||
|
|
||||||
|
spdif);
|
||||||
|
|
||||||
|
input sys_rst;
|
||||||
|
input sys_clk_p;
|
||||||
|
input sys_clk_n;
|
||||||
|
|
||||||
|
input uart_sin;
|
||||||
|
output uart_sout;
|
||||||
|
|
||||||
|
output [13:0] ddr3_addr;
|
||||||
|
output [ 2:0] ddr3_ba;
|
||||||
|
output ddr3_cas_n;
|
||||||
|
output [ 0:0] ddr3_ck_n;
|
||||||
|
output [ 0:0] ddr3_ck_p;
|
||||||
|
output [ 0:0] ddr3_cke;
|
||||||
|
output [ 0:0] ddr3_cs_n;
|
||||||
|
output [ 7:0] ddr3_dm;
|
||||||
|
inout [63:0] ddr3_dq;
|
||||||
|
inout [ 7:0] ddr3_dqs_n;
|
||||||
|
inout [ 7:0] ddr3_dqs_p;
|
||||||
|
output [ 0:0] ddr3_odt;
|
||||||
|
output ddr3_ras_n;
|
||||||
|
output ddr3_reset_n;
|
||||||
|
output ddr3_we_n;
|
||||||
|
|
||||||
|
output phy_reset_n;
|
||||||
|
output phy_mdc;
|
||||||
|
inout phy_mdio;
|
||||||
|
output phy_tx_clk;
|
||||||
|
output phy_tx_ctrl;
|
||||||
|
output [ 3:0] phy_tx_data;
|
||||||
|
input phy_rx_clk;
|
||||||
|
input phy_rx_ctrl;
|
||||||
|
input [ 3:0] phy_rx_data;
|
||||||
|
|
||||||
|
output fan_pwm;
|
||||||
|
|
||||||
|
inout [ 6:0] gpio_lcd;
|
||||||
|
inout [ 3:0] gpio_led;
|
||||||
|
inout [ 8:0] gpio_sw;
|
||||||
|
|
||||||
|
output iic_rstn;
|
||||||
|
inout iic_scl;
|
||||||
|
inout iic_sda;
|
||||||
|
|
||||||
|
input dac_clk_in_p;
|
||||||
|
input dac_clk_in_n;
|
||||||
|
output dac_clk_out_p;
|
||||||
|
output dac_clk_out_n;
|
||||||
|
output dac_frame_out_p;
|
||||||
|
output dac_frame_out_n;
|
||||||
|
output [15:0] dac_data_out_p;
|
||||||
|
output [15:0] dac_data_out_n;
|
||||||
|
|
||||||
|
input adc_clk_in_p;
|
||||||
|
input adc_clk_in_n;
|
||||||
|
input adc_or_in_p;
|
||||||
|
input adc_or_in_n;
|
||||||
|
input [13:0] adc_data_in_p;
|
||||||
|
input [13:0] adc_data_in_n;
|
||||||
|
|
||||||
|
output ref_clk_out_p;
|
||||||
|
output ref_clk_out_n;
|
||||||
|
|
||||||
|
output hdmi_out_clk;
|
||||||
|
output hdmi_hsync;
|
||||||
|
output hdmi_vsync;
|
||||||
|
output hdmi_data_e;
|
||||||
|
output [23:0] hdmi_data;
|
||||||
|
|
||||||
|
output spdif;
|
||||||
|
|
||||||
|
wire ref_clk;
|
||||||
|
wire oddr_ref_clk;
|
||||||
|
// assignments
|
||||||
|
|
||||||
|
assign mgt_clk_sel = 2'd0;
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
ODDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE"),
|
||||||
|
.INIT (1'b0),
|
||||||
|
.SRTYPE ("ASYNC"))
|
||||||
|
i_oddr_ref_clk (
|
||||||
|
.S (1'b0),
|
||||||
|
.CE (1'b1),
|
||||||
|
.R (1'b0),
|
||||||
|
.C (ref_clk),
|
||||||
|
.D1 (1'b1),
|
||||||
|
.D2 (1'b0),
|
||||||
|
.Q (oddr_ref_clk));
|
||||||
|
|
||||||
|
OBUFDS i_obufds_ref_clk (
|
||||||
|
.I (oddr_ref_clk),
|
||||||
|
.O (ref_clk_out_p),
|
||||||
|
.OB (ref_clk_out_n));
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.ddr3_addr (ddr3_addr),
|
||||||
|
.ddr3_ba (ddr3_ba),
|
||||||
|
.ddr3_cas_n (ddr3_cas_n),
|
||||||
|
.ddr3_ck_n (ddr3_ck_n),
|
||||||
|
.ddr3_ck_p (ddr3_ck_p),
|
||||||
|
.ddr3_cke (ddr3_cke),
|
||||||
|
.ddr3_cs_n (ddr3_cs_n),
|
||||||
|
.ddr3_dm (ddr3_dm),
|
||||||
|
.ddr3_dq (ddr3_dq),
|
||||||
|
.ddr3_dqs_n (ddr3_dqs_n),
|
||||||
|
.ddr3_dqs_p (ddr3_dqs_p),
|
||||||
|
.ddr3_odt (ddr3_odt),
|
||||||
|
.ddr3_ras_n (ddr3_ras_n),
|
||||||
|
.ddr3_reset_n (ddr3_reset_n),
|
||||||
|
.ddr3_we_n (ddr3_we_n),
|
||||||
|
.fan_pwm (fan_pwm),
|
||||||
|
.gpio_lcd_tri_io (gpio_lcd),
|
||||||
|
.gpio_led_tri_io (gpio_led),
|
||||||
|
.gpio_sw_tri_io (gpio_sw),
|
||||||
|
.hdmi_data (hdmi_data),
|
||||||
|
.hdmi_data_e (hdmi_data_e),
|
||||||
|
.hdmi_hsync (hdmi_hsync),
|
||||||
|
.hdmi_out_clk (hdmi_out_clk),
|
||||||
|
.hdmi_vsync (hdmi_vsync),
|
||||||
|
.iic_main_scl_io (iic_scl),
|
||||||
|
.iic_main_sda_io (iic_sda),
|
||||||
|
.iic_rstn (iic_rstn),
|
||||||
|
.adc_clk_in_n (adc_clk_in_n),
|
||||||
|
.adc_clk_in_p (adc_clk_in_p),
|
||||||
|
.adc_data_in_n (adc_data_in_n),
|
||||||
|
.adc_data_in_p (adc_data_in_p),
|
||||||
|
.adc_or_in_n (adc_or_in_n),
|
||||||
|
.adc_or_in_p (adc_or_in_p),
|
||||||
|
.dac_clk_in_n (dac_clk_in_n),
|
||||||
|
.dac_clk_in_p (dac_clk_in_p),
|
||||||
|
.dac_clk_out_n (dac_clk_out_n),
|
||||||
|
.dac_clk_out_p (dac_clk_out_p),
|
||||||
|
.dac_data_out_n (dac_data_out_n),
|
||||||
|
.dac_data_out_p (dac_data_out_p),
|
||||||
|
.dac_frame_out_n (dac_frame_out_n),
|
||||||
|
.dac_frame_out_p (dac_frame_out_p),
|
||||||
|
.ref_clk (ref_clk),
|
||||||
|
.mdio_io (phy_mdio),
|
||||||
|
.mdio_mdc (phy_mdc),
|
||||||
|
.phy_rst_n (phy_reset_n),
|
||||||
|
.rgmii_rd (phy_rx_data),
|
||||||
|
.rgmii_rx_ctl (phy_rx_ctrl),
|
||||||
|
.rgmii_rxc (phy_rx_clk),
|
||||||
|
.rgmii_td (phy_tx_data),
|
||||||
|
.rgmii_tx_ctl (phy_tx_ctrl),
|
||||||
|
.rgmii_txc (phy_tx_clk),
|
||||||
|
.spdif (spdif),
|
||||||
|
.sys_clk_n (sys_clk_n),
|
||||||
|
.sys_clk_p (sys_clk_p),
|
||||||
|
.sys_rst (sys_rst),
|
||||||
|
.uart_sin (uart_sin),
|
||||||
|
.uart_sout (uart_sout),
|
||||||
|
.unc_int0 (1'b0),
|
||||||
|
.unc_int1 (1'b0),
|
||||||
|
.unc_int4 (1'b0));
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
@ -0,0 +1,4 @@
|
||||||
|
|
||||||
|
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
|
||||||
|
source ../common/fmcomms1_bd.tcl
|
||||||
|
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
|
||||||
|
# reference
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN U37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC_LPC_LA17_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN U38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC_LPC_LA17_CC_N
|
||||||
|
|
||||||
|
# dac
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AF39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN AF40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N
|
||||||
|
set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS} [get_ports dac_clk_out_p] ; ## FMC_LPC_LA21_P
|
||||||
|
set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS} [get_ports dac_clk_out_n] ; ## FMC_LPC_LA21_N
|
||||||
|
set_property -dict {PACKAGE_PIN Y42 IOSTANDARD LVDS} [get_ports dac_frame_out_p] ; ## FMC_LPC_LA11_P
|
||||||
|
set_property -dict {PACKAGE_PIN AA42 IOSTANDARD LVDS} [get_ports dac_frame_out_n] ; ## FMC_LPC_LA11_N
|
||||||
|
set_property -dict {PACKAGE_PIN P37 IOSTANDARD LVDS} [get_ports dac_data_out_p[0]] ; ## FMC_LPC_LA32_P
|
||||||
|
set_property -dict {PACKAGE_PIN P38 IOSTANDARD LVDS} [get_ports dac_data_out_n[0]] ; ## FMC_LPC_LA32_N
|
||||||
|
set_property -dict {PACKAGE_PIN T36 IOSTANDARD LVDS} [get_ports dac_data_out_p[1]] ; ## FMC_LPC_LA33_P
|
||||||
|
set_property -dict {PACKAGE_PIN R37 IOSTANDARD LVDS} [get_ports dac_data_out_n[1]] ; ## FMC_LPC_LA33_N
|
||||||
|
set_property -dict {PACKAGE_PIN T32 IOSTANDARD LVDS} [get_ports dac_data_out_p[2]] ; ## FMC_LPC_LA30_P
|
||||||
|
set_property -dict {PACKAGE_PIN R32 IOSTANDARD LVDS} [get_ports dac_data_out_n[2]] ; ## FMC_LPC_LA30_N
|
||||||
|
set_property -dict {PACKAGE_PIN V35 IOSTANDARD LVDS} [get_ports dac_data_out_p[3]] ; ## FMC_LPC_LA28_P
|
||||||
|
set_property -dict {PACKAGE_PIN V36 IOSTANDARD LVDS} [get_ports dac_data_out_n[3]] ; ## FMC_LPC_LA28_N
|
||||||
|
set_property -dict {PACKAGE_PIN V39 IOSTANDARD LVDS} [get_ports dac_data_out_p[4]] ; ## FMC_LPC_LA31_P
|
||||||
|
set_property -dict {PACKAGE_PIN V40 IOSTANDARD LVDS} [get_ports dac_data_out_n[4]] ; ## FMC_LPC_LA31_N
|
||||||
|
set_property -dict {PACKAGE_PIN W36 IOSTANDARD LVDS} [get_ports dac_data_out_p[5]] ; ## FMC_LPC_LA29_P
|
||||||
|
set_property -dict {PACKAGE_PIN W37 IOSTANDARD LVDS} [get_ports dac_data_out_n[5]] ; ## FMC_LPC_LA29_N
|
||||||
|
set_property -dict {PACKAGE_PIN U34 IOSTANDARD LVDS} [get_ports dac_data_out_p[6]] ; ## FMC_LPC_LA24_P
|
||||||
|
set_property -dict {PACKAGE_PIN T35 IOSTANDARD LVDS} [get_ports dac_data_out_n[6]] ; ## FMC_LPC_LA24_N
|
||||||
|
set_property -dict {PACKAGE_PIN R33 IOSTANDARD LVDS} [get_ports dac_data_out_p[7]] ; ## FMC_LPC_LA25_P
|
||||||
|
set_property -dict {PACKAGE_PIN R34 IOSTANDARD LVDS} [get_ports dac_data_out_n[7]] ; ## FMC_LPC_LA25_N
|
||||||
|
set_property -dict {PACKAGE_PIN W32 IOSTANDARD LVDS} [get_ports dac_data_out_p[8]] ; ## FMC_LPC_LA22_P
|
||||||
|
set_property -dict {PACKAGE_PIN W33 IOSTANDARD LVDS} [get_ports dac_data_out_n[8]] ; ## FMC_LPC_LA22_N
|
||||||
|
set_property -dict {PACKAGE_PIN P32 IOSTANDARD LVDS} [get_ports dac_data_out_p[9]] ; ## FMC_LPC_LA27_P
|
||||||
|
set_property -dict {PACKAGE_PIN P33 IOSTANDARD LVDS} [get_ports dac_data_out_n[9]] ; ## FMC_LPC_LA27_N
|
||||||
|
set_property -dict {PACKAGE_PIN N33 IOSTANDARD LVDS} [get_ports dac_data_out_p[10]] ; ## FMC_LPC_LA26_P
|
||||||
|
set_property -dict {PACKAGE_PIN N34 IOSTANDARD LVDS} [get_ports dac_data_out_n[10]] ; ## FMC_LPC_LA26_N
|
||||||
|
set_property -dict {PACKAGE_PIN R38 IOSTANDARD LVDS} [get_ports dac_data_out_p[11]] ; ## FMC_LPC_LA23_P
|
||||||
|
set_property -dict {PACKAGE_PIN R39 IOSTANDARD LVDS} [get_ports dac_data_out_n[11]] ; ## FMC_LPC_LA23_N
|
||||||
|
set_property -dict {PACKAGE_PIN U32 IOSTANDARD LVDS} [get_ports dac_data_out_p[12]] ; ## FMC_LPC_LA19_P
|
||||||
|
set_property -dict {PACKAGE_PIN U33 IOSTANDARD LVDS} [get_ports dac_data_out_n[12]] ; ## FMC_LPC_LA19_N
|
||||||
|
set_property -dict {PACKAGE_PIN V33 IOSTANDARD LVDS} [get_ports dac_data_out_p[13]] ; ## FMC_LPC_LA20_P
|
||||||
|
set_property -dict {PACKAGE_PIN V34 IOSTANDARD LVDS} [get_ports dac_data_out_n[13]] ; ## FMC_LPC_LA20_N
|
||||||
|
set_property -dict {PACKAGE_PIN AC38 IOSTANDARD LVDS} [get_ports dac_data_out_p[14]] ; ## FMC_LPC_LA15_P
|
||||||
|
set_property -dict {PACKAGE_PIN AC39 IOSTANDARD LVDS} [get_ports dac_data_out_n[14]] ; ## FMC_LPC_LA15_N
|
||||||
|
set_property -dict {PACKAGE_PIN AJ40 IOSTANDARD LVDS} [get_ports dac_data_out_p[15]] ; ## FMC_LPC_LA16_P
|
||||||
|
set_property -dict {PACKAGE_PIN AJ41 IOSTANDARD LVDS} [get_ports dac_data_out_n[15]] ; ## FMC_LPC_LA16_N
|
||||||
|
|
||||||
|
# adc
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN U39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC_LPC_CLK1_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN T39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC_LPC_CLK1_M2C_N
|
||||||
|
set_property -dict {PACKAGE_PIN AD40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC_LPC_LA00_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN AD41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC_LPC_LA00_CC_N
|
||||||
|
set_property -dict {PACKAGE_PIN U36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC_LPC_LA18_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN T37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC_LPC_LA18_CC_N
|
||||||
|
set_property -dict {PACKAGE_PIN AB38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC_LPC_LA14_P
|
||||||
|
set_property -dict {PACKAGE_PIN AB39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC_LPC_LA14_N
|
||||||
|
set_property -dict {PACKAGE_PIN W40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC_LPC_LA13_P
|
||||||
|
set_property -dict {PACKAGE_PIN Y40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC_LPC_LA13_N
|
||||||
|
set_property -dict {PACKAGE_PIN AJ42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC_LPC_LA03_P
|
||||||
|
set_property -dict {PACKAGE_PIN AK42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC_LPC_LA03_N
|
||||||
|
set_property -dict {PACKAGE_PIN AF42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC_LPC_LA05_P
|
||||||
|
set_property -dict {PACKAGE_PIN AG42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC_LPC_LA05_N
|
||||||
|
set_property -dict {PACKAGE_PIN AB41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC_LPC_LA10_P
|
||||||
|
set_property -dict {PACKAGE_PIN AB42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC_LPC_LA10_N
|
||||||
|
set_property -dict {PACKAGE_PIN Y39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC_LPC_LA12_P
|
||||||
|
set_property -dict {PACKAGE_PIN AA39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC_LPC_LA12_N
|
||||||
|
set_property -dict {PACKAGE_PIN AC40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC_LPC_LA07_P
|
||||||
|
set_property -dict {PACKAGE_PIN AC41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC_LPC_LA07_N
|
||||||
|
set_property -dict {PACKAGE_PIN AK39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC_LPC_LA02_P
|
||||||
|
set_property -dict {PACKAGE_PIN AL39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC_LPC_LA02_N
|
||||||
|
set_property -dict {PACKAGE_PIN AL41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC_LPC_LA04_P
|
||||||
|
set_property -dict {PACKAGE_PIN AL42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC_LPC_LA04_N
|
||||||
|
set_property -dict {PACKAGE_PIN AJ38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC_LPC_LA09_P
|
||||||
|
set_property -dict {PACKAGE_PIN AK38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC_LPC_LA09_N
|
||||||
|
set_property -dict {PACKAGE_PIN AD42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC_LPC_LA08_P
|
||||||
|
set_property -dict {PACKAGE_PIN AE42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC_LPC_LA08_N
|
||||||
|
set_property -dict {PACKAGE_PIN AD38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC_LPC_LA06_P
|
||||||
|
set_property -dict {PACKAGE_PIN AE38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC_LPC_LA06_N
|
||||||
|
set_property -dict {PACKAGE_PIN AF41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC_LPC_LA01_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN AG41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC_LPC_LA01_CC_N
|
||||||
|
|
||||||
|
# clocks
|
||||||
|
|
||||||
|
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
|
||||||
|
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]
|
||||||
|
create_clock -name dac_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
|
||||||
|
create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
|
||||||
|
create_clock -name ref_clk -period 33.33 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out2]
|
||||||
|
create_clock -name ila_clk -period 8.00 [get_pins i_system_wrapper/system_i/ila_clkgen/clk_out1]
|
||||||
|
|
||||||
|
set_clock_groups -asynchronous -group {dac_div_clk}
|
||||||
|
set_clock_groups -asynchronous -group {adc_clk}
|
||||||
|
set_clock_groups -asynchronous -group {ref_clk}
|
||||||
|
set_clock_groups -asynchronous -group {ila_clk}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,15 @@
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
source ../../scripts/adi_env.tcl
|
||||||
|
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||||
|
|
||||||
|
adi_project_create fmcomms1_vc707
|
||||||
|
adi_project_files fmcomms1_vc707 [list \
|
||||||
|
"system_top.v" \
|
||||||
|
"system_constr.xdc"\
|
||||||
|
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
|
||||||
|
|
||||||
|
adi_project_run fmcomms1_vc707
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,273 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2011(c) Analog Devices, Inc.
|
||||||
|
//
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
// are permitted provided that the following conditions are met:
|
||||||
|
// - Redistributions of source code must retain the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer.
|
||||||
|
// - Redistributions in binary form must reproduce the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer in
|
||||||
|
// the documentation and/or other materials provided with the
|
||||||
|
// distribution.
|
||||||
|
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||||
|
// contributors may be used to endorse or promote products derived
|
||||||
|
// from this software without specific prior written permission.
|
||||||
|
// - The use of this software may or may not infringe the patent rights
|
||||||
|
// of one or more patent holders. This license does not release you
|
||||||
|
// from the requirement that you obtain separate licenses from these
|
||||||
|
// patent holders to use this software.
|
||||||
|
// - Use of the software either in source or binary form, must be run
|
||||||
|
// on or directly connected to an Analog Devices Inc. component.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||||
|
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||||
|
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
//
|
||||||
|
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||||
|
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||||
|
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||||
|
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||||
|
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||||
|
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
module system_top (
|
||||||
|
|
||||||
|
sys_rst,
|
||||||
|
sys_clk_p,
|
||||||
|
sys_clk_n,
|
||||||
|
|
||||||
|
uart_sin,
|
||||||
|
uart_sout,
|
||||||
|
|
||||||
|
ddr3_addr,
|
||||||
|
ddr3_ba,
|
||||||
|
ddr3_cas_n,
|
||||||
|
ddr3_ck_n,
|
||||||
|
ddr3_ck_p,
|
||||||
|
ddr3_cke,
|
||||||
|
ddr3_cs_n,
|
||||||
|
ddr3_dm,
|
||||||
|
ddr3_dq,
|
||||||
|
ddr3_dqs_n,
|
||||||
|
ddr3_dqs_p,
|
||||||
|
ddr3_odt,
|
||||||
|
ddr3_ras_n,
|
||||||
|
ddr3_reset_n,
|
||||||
|
ddr3_we_n,
|
||||||
|
|
||||||
|
sgmii_rxp,
|
||||||
|
sgmii_rxn,
|
||||||
|
sgmii_txp,
|
||||||
|
sgmii_txn,
|
||||||
|
|
||||||
|
phy_rstn,
|
||||||
|
mgt_clk_p,
|
||||||
|
mgt_clk_n,
|
||||||
|
mdio_mdc,
|
||||||
|
mdio_mdio,
|
||||||
|
|
||||||
|
fan_pwm,
|
||||||
|
|
||||||
|
gpio_lcd,
|
||||||
|
gpio_led,
|
||||||
|
gpio_sw,
|
||||||
|
|
||||||
|
iic_rstn,
|
||||||
|
iic_scl,
|
||||||
|
iic_sda,
|
||||||
|
|
||||||
|
dac_clk_in_p,
|
||||||
|
dac_clk_in_n,
|
||||||
|
dac_clk_out_p,
|
||||||
|
dac_clk_out_n,
|
||||||
|
dac_frame_out_p,
|
||||||
|
dac_frame_out_n,
|
||||||
|
dac_data_out_p,
|
||||||
|
dac_data_out_n,
|
||||||
|
|
||||||
|
adc_clk_in_p,
|
||||||
|
adc_clk_in_n,
|
||||||
|
adc_or_in_p,
|
||||||
|
adc_or_in_n,
|
||||||
|
adc_data_in_p,
|
||||||
|
adc_data_in_n,
|
||||||
|
|
||||||
|
ref_clk_out_p,
|
||||||
|
ref_clk_out_n,
|
||||||
|
|
||||||
|
hdmi_out_clk,
|
||||||
|
hdmi_hsync,
|
||||||
|
hdmi_vsync,
|
||||||
|
hdmi_data_e,
|
||||||
|
hdmi_data,
|
||||||
|
|
||||||
|
spdif);
|
||||||
|
|
||||||
|
input sys_rst;
|
||||||
|
input sys_clk_p;
|
||||||
|
input sys_clk_n;
|
||||||
|
|
||||||
|
input uart_sin;
|
||||||
|
output uart_sout;
|
||||||
|
|
||||||
|
output [13:0] ddr3_addr;
|
||||||
|
output [ 2:0] ddr3_ba;
|
||||||
|
output ddr3_cas_n;
|
||||||
|
output [ 0:0] ddr3_ck_n;
|
||||||
|
output [ 0:0] ddr3_ck_p;
|
||||||
|
output [ 0:0] ddr3_cke;
|
||||||
|
output [ 0:0] ddr3_cs_n;
|
||||||
|
output [ 7:0] ddr3_dm;
|
||||||
|
inout [63:0] ddr3_dq;
|
||||||
|
inout [ 7:0] ddr3_dqs_n;
|
||||||
|
inout [ 7:0] ddr3_dqs_p;
|
||||||
|
output [ 0:0] ddr3_odt;
|
||||||
|
output ddr3_ras_n;
|
||||||
|
output ddr3_reset_n;
|
||||||
|
output ddr3_we_n;
|
||||||
|
|
||||||
|
input sgmii_rxp;
|
||||||
|
input sgmii_rxn;
|
||||||
|
output sgmii_txp;
|
||||||
|
output sgmii_txn;
|
||||||
|
|
||||||
|
output phy_rstn;
|
||||||
|
input mgt_clk_p;
|
||||||
|
input mgt_clk_n;
|
||||||
|
output mdio_mdc;
|
||||||
|
inout mdio_mdio;
|
||||||
|
|
||||||
|
output fan_pwm;
|
||||||
|
|
||||||
|
output [ 6:0] gpio_lcd;
|
||||||
|
output [ 7:0] gpio_led;
|
||||||
|
input [12:0] gpio_sw;
|
||||||
|
|
||||||
|
output iic_rstn;
|
||||||
|
inout iic_scl;
|
||||||
|
inout iic_sda;
|
||||||
|
|
||||||
|
input dac_clk_in_p;
|
||||||
|
input dac_clk_in_n;
|
||||||
|
output dac_clk_out_p;
|
||||||
|
output dac_clk_out_n;
|
||||||
|
output dac_frame_out_p;
|
||||||
|
output dac_frame_out_n;
|
||||||
|
output [15:0] dac_data_out_p;
|
||||||
|
output [15:0] dac_data_out_n;
|
||||||
|
|
||||||
|
input adc_clk_in_p;
|
||||||
|
input adc_clk_in_n;
|
||||||
|
input adc_or_in_p;
|
||||||
|
input adc_or_in_n;
|
||||||
|
input [13:0] adc_data_in_p;
|
||||||
|
input [13:0] adc_data_in_n;
|
||||||
|
|
||||||
|
output ref_clk_out_p;
|
||||||
|
output ref_clk_out_n;
|
||||||
|
output hdmi_out_clk;
|
||||||
|
output hdmi_hsync;
|
||||||
|
output hdmi_vsync;
|
||||||
|
output hdmi_data_e;
|
||||||
|
output [35:0] hdmi_data;
|
||||||
|
|
||||||
|
output spdif;
|
||||||
|
|
||||||
|
wire ref_clk;
|
||||||
|
wire oddr_ref_clk;
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
ODDR #(
|
||||||
|
.DDR_CLK_EDGE ("SAME_EDGE"),
|
||||||
|
.INIT (1'b0),
|
||||||
|
.SRTYPE ("ASYNC"))
|
||||||
|
i_oddr_ref_clk (
|
||||||
|
.S (1'b0),
|
||||||
|
.CE (1'b1),
|
||||||
|
.R (1'b0),
|
||||||
|
.C (ref_clk),
|
||||||
|
.D1 (1'b1),
|
||||||
|
.D2 (1'b0),
|
||||||
|
.Q (oddr_ref_clk));
|
||||||
|
|
||||||
|
OBUFDS i_obufds_ref_clk (
|
||||||
|
.I (oddr_ref_clk),
|
||||||
|
.O (ref_clk_out_p),
|
||||||
|
.OB (ref_clk_out_n));
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.ddr3_addr (ddr3_addr),
|
||||||
|
.ddr3_ba (ddr3_ba),
|
||||||
|
.ddr3_cas_n (ddr3_cas_n),
|
||||||
|
.ddr3_ck_n (ddr3_ck_n),
|
||||||
|
.ddr3_ck_p (ddr3_ck_p),
|
||||||
|
.ddr3_cke (ddr3_cke),
|
||||||
|
.ddr3_cs_n (ddr3_cs_n),
|
||||||
|
.ddr3_dm (ddr3_dm),
|
||||||
|
.ddr3_dq (ddr3_dq),
|
||||||
|
.ddr3_dqs_n (ddr3_dqs_n),
|
||||||
|
.ddr3_dqs_p (ddr3_dqs_p),
|
||||||
|
.ddr3_odt (ddr3_odt),
|
||||||
|
.ddr3_ras_n (ddr3_ras_n),
|
||||||
|
.ddr3_reset_n (ddr3_reset_n),
|
||||||
|
.ddr3_we_n (ddr3_we_n),
|
||||||
|
.fan_pwm (fan_pwm),
|
||||||
|
.gpio_lcd_tri_o (gpio_lcd),
|
||||||
|
.gpio_led_tri_o (gpio_led),
|
||||||
|
.gpio_sw_tri_i (gpio_sw),
|
||||||
|
.hdmi_data (hdmi_data),
|
||||||
|
.hdmi_data_e (hdmi_data_e),
|
||||||
|
.hdmi_hsync (hdmi_hsync),
|
||||||
|
.hdmi_out_clk (hdmi_out_clk),
|
||||||
|
.hdmi_vsync (hdmi_vsync),
|
||||||
|
.adc_clk_in_n (adc_clk_in_n),
|
||||||
|
.adc_clk_in_p (adc_clk_in_p),
|
||||||
|
.adc_data_in_n (adc_data_in_n),
|
||||||
|
.adc_data_in_p (adc_data_in_p),
|
||||||
|
.adc_or_in_n (adc_or_in_n),
|
||||||
|
.adc_or_in_p (adc_or_in_p),
|
||||||
|
.dac_clk_in_n (dac_clk_in_n),
|
||||||
|
.dac_clk_in_p (dac_clk_in_p),
|
||||||
|
.dac_clk_out_n (dac_clk_out_n),
|
||||||
|
.dac_clk_out_p (dac_clk_out_p),
|
||||||
|
.dac_data_out_n (dac_data_out_n),
|
||||||
|
.dac_data_out_p (dac_data_out_p),
|
||||||
|
.dac_frame_out_n (dac_frame_out_n),
|
||||||
|
.dac_frame_out_p (dac_frame_out_p),
|
||||||
|
.ref_clk (ref_clk),
|
||||||
|
.iic_main_scl_io (iic_scl),
|
||||||
|
.iic_main_sda_io (iic_sda),
|
||||||
|
.iic_rstn (iic_rstn),
|
||||||
|
.mdio_mdc (mdio_mdc),
|
||||||
|
.mdio_mdio_io (mdio_mdio),
|
||||||
|
.mgt_clk_clk_n (mgt_clk_n),
|
||||||
|
.mgt_clk_clk_p (mgt_clk_p),
|
||||||
|
.phy_rstn (phy_rstn),
|
||||||
|
.sgmii_rxn (sgmii_rxn),
|
||||||
|
.sgmii_rxp (sgmii_rxp),
|
||||||
|
.sgmii_txn (sgmii_txn),
|
||||||
|
.sgmii_txp (sgmii_txp),
|
||||||
|
.spdif (spdif),
|
||||||
|
.sys_clk_n (sys_clk_n),
|
||||||
|
.sys_clk_p (sys_clk_p),
|
||||||
|
.sys_rst (sys_rst),
|
||||||
|
.uart_sin (uart_sin),
|
||||||
|
.uart_sout (uart_sout),
|
||||||
|
.unc_int0 (1'b0),
|
||||||
|
.unc_int1 (1'b0),
|
||||||
|
.unc_int4 (1'b0));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
Loading…
Reference in New Issue