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ad9081_fmca_ebz: Np 12 support 

204B functional
204C functional
main
Laszlo Nagy 2020-11-06 14:49:05 +00:00 committed by Laszlo Nagy
parent 5678e72653
commit d0f8a81b2f
4 changed files with 91 additions and 30 deletions
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106
projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
View File

@ -14,7 +14,7 @@
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode # REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported # [RX/TX]_JESD_NP : Number of bits per sample
# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices # [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
# #
@ -23,10 +23,12 @@ set JESD_MODE $ad_project_params(JESD_MODE)
if {$JESD_MODE == "8B10B"} { if {$JESD_MODE == "8B10B"} {
set DATAPATH_WIDTH 4 set DATAPATH_WIDTH 4
set NP12_DATAPATH_WIDTH 6
set ENCODER_SEL 1 set ENCODER_SEL 1
set ADI_PHY_SEL 1 set ADI_PHY_SEL 1
} else { } else {
set DATAPATH_WIDTH 8 set DATAPATH_WIDTH 8
set NP12_DATAPATH_WIDTH 12
set ENCODER_SEL 2 set ENCODER_SEL 2
set ADI_PHY_SEL 0 set ADI_PHY_SEL 0
} }
@ -53,7 +55,20 @@ set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS]
set RX_SAMPLES_PER_FRAME $RX_JESD_S set RX_SAMPLES_PER_FRAME $RX_JESD_S
set RX_SAMPLE_WIDTH $RX_JESD_NP set RX_SAMPLE_WIDTH $RX_JESD_NP
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8*$DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] set RX_DMA_SAMPLE_WIDTH $RX_JESD_NP
if {$RX_DMA_SAMPLE_WIDTH == 12} {
set RX_DMA_SAMPLE_WIDTH 16
}
set RX_JESD_F [expr ($RX_JESD_M*$RX_JESD_S*$RX_JESD_NP)/(8*$RX_JESD_L)]
# For F=3,6,12 use dual clock
if {$RX_JESD_F % 3 == 0} {
set RX_DATAPATH_WIDTH [expr max($RX_JESD_F,$NP12_DATAPATH_WIDTH)]
} else {
set RX_DATAPATH_WIDTH $DATAPATH_WIDTH
}
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8* $RX_DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
# TX parameters # TX parameters
set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS) set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS)
@ -69,19 +84,32 @@ set TX_NUM_OF_CONVERTERS [expr $TX_JESD_M * $TX_NUM_LINKS]
set TX_SAMPLES_PER_FRAME $TX_JESD_S set TX_SAMPLES_PER_FRAME $TX_JESD_S
set TX_SAMPLE_WIDTH $TX_JESD_NP set TX_SAMPLE_WIDTH $TX_JESD_NP
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8*$DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] set TX_DMA_SAMPLE_WIDTH $TX_JESD_NP
if {$TX_DMA_SAMPLE_WIDTH == 12} {
set TX_DMA_SAMPLE_WIDTH 16
}
set TX_JESD_F [expr ($TX_JESD_M*$TX_JESD_S*$TX_JESD_NP)/(8*$TX_JESD_L)]
# For F=3,6,12 use dual clock
if {$TX_JESD_F % 3 == 0} {
set TX_DATAPATH_WIDTH [expr max($TX_JESD_F,$NP12_DATAPATH_WIDTH)]
} else {
set TX_DATAPATH_WIDTH $DATAPATH_WIDTH
}
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8* $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
set adc_fifo_name mxfe_adc_fifo set adc_fifo_name mxfe_adc_fifo
set adc_data_width [expr 8*$DATAPATH_WIDTH*$RX_NUM_OF_LANES] set adc_data_width [expr $RX_DMA_SAMPLE_WIDTH*$RX_NUM_OF_CONVERTERS*$RX_SAMPLES_PER_CHANNEL]
set adc_dma_data_width [expr 8*$DATAPATH_WIDTH*$RX_NUM_OF_LANES] set adc_dma_data_width $adc_data_width
set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_SAMPLE_WIDTH))/log(2)))] set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_DMA_SAMPLE_WIDTH))/log(2)))]
set dac_fifo_name mxfe_dac_fifo set dac_fifo_name mxfe_dac_fifo
set dac_data_width [expr 8*$DATAPATH_WIDTH*$TX_NUM_OF_LANES] set dac_data_width [expr $TX_DMA_SAMPLE_WIDTH*$TX_NUM_OF_CONVERTERS*$TX_SAMPLES_PER_CHANNEL]
set dac_dma_data_width [expr 8*$DATAPATH_WIDTH*$TX_NUM_OF_LANES] set dac_dma_data_width $dac_data_width
set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_SAMPLE_WIDTH))/log(2)))] set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))]
create_bd_port -dir I rx_device_clk create_bd_port -dir I rx_device_clk
create_bd_port -dir I tx_device_clk create_bd_port -dir I tx_device_clk
@ -184,6 +212,7 @@ ad_ip_instance jesd204_phy jesd204_phy_126 [list \
# adc peripherals # adc peripherals
adi_axi_jesd204_rx_create axi_mxfe_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL adi_axi_jesd204_rx_create axi_mxfe_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $RX_DATAPATH_WIDTH
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.SYSREF_IOB false ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.SYSREF_IOB false
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 1 ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 1
@ -192,12 +221,13 @@ adi_tpl_jesd204_rx_create rx_mxfe_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \ $RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \ $RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH \ $RX_SAMPLE_WIDTH \
$DATAPATH_WIDTH $RX_DATAPATH_WIDTH \
$RX_DMA_SAMPLE_WIDTH
ad_ip_instance util_cpack2 util_mxfe_cpack [list \ ad_ip_instance util_cpack2 util_mxfe_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \ NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \ SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \ SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH \
] ]
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
@ -219,6 +249,7 @@ ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width
# dac peripherals # dac peripherals
adi_axi_jesd204_tx_create axi_mxfe_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL adi_axi_jesd204_tx_create axi_mxfe_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.TPL_DATA_PATH_WIDTH $TX_DATAPATH_WIDTH
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.SYSREF_IOB false ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.SYSREF_IOB false
#ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 #ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1
@ -227,7 +258,8 @@ adi_tpl_jesd204_tx_create tx_mxfe_tpl_core $TX_NUM_OF_LANES \
$TX_NUM_OF_CONVERTERS \ $TX_NUM_OF_CONVERTERS \
$TX_SAMPLES_PER_FRAME \ $TX_SAMPLES_PER_FRAME \
$TX_SAMPLE_WIDTH \ $TX_SAMPLE_WIDTH \
$DATAPATH_WIDTH $TX_DATAPATH_WIDTH \
$TX_DMA_SAMPLE_WIDTH
ad_ip_parameter tx_mxfe_tpl_core/dac_tpl_core CONFIG.IQCORRECTION_DISABLE 0 ad_ip_parameter tx_mxfe_tpl_core/dac_tpl_core CONFIG.IQCORRECTION_DISABLE 0
ad_ip_parameter tx_mxfe_tpl_core/dac_tpl_core CONFIG.XBAR_ENABLE 1 ad_ip_parameter tx_mxfe_tpl_core/dac_tpl_core CONFIG.XBAR_ENABLE 1
@ -235,7 +267,7 @@ ad_ip_parameter tx_mxfe_tpl_core/dac_tpl_core CONFIG.XBAR_ENABLE 1
ad_ip_instance util_upack2 util_mxfe_upack [list \ ad_ip_instance util_upack2 util_mxfe_upack [list \
NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \ NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \ SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \ SAMPLE_DATA_WIDTH $TX_DMA_SAMPLE_WIDTH \
] ]
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
@ -275,10 +307,10 @@ ad_connect $sys_cpu_clk util_mxfe_xcvr/up_clk
# connections (adc) # connections (adc)
ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} rx_device_clk ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} {} rx_device_clk
# connections (dac) # connections (dac)
ad_xcvrcon util_mxfe_xcvr axi_mxfe_tx_xcvr axi_mxfe_tx_jesd {} tx_device_clk ad_xcvrcon util_mxfe_xcvr axi_mxfe_tx_xcvr axi_mxfe_tx_jesd {} {} tx_device_clk
} else { } else {
ad_connect ref_clk_q0 jesd204_phy_121/cpll_refclk ad_connect ref_clk_q0 jesd204_phy_121/cpll_refclk
ad_connect ref_clk_q0 jesd204_phy_121/qpll0_refclk ad_connect ref_clk_q0 jesd204_phy_121/qpll0_refclk
@ -287,15 +319,41 @@ ad_connect ref_clk_q1 jesd204_phy_126/cpll_refclk
ad_connect ref_clk_q1 jesd204_phy_126/qpll0_refclk ad_connect ref_clk_q1 jesd204_phy_126/qpll0_refclk
ad_connect ref_clk_q1 jesd204_phy_126/qpll1_refclk ad_connect ref_clk_q1 jesd204_phy_126/qpll1_refclk
# device clock domain # link clock domain
ad_connect tx_device_clk jesd204_phy_121/tx_core_clk
ad_connect tx_device_clk jesd204_phy_126/tx_core_clk ad_ip_instance util_ds_buf txoutclk_BUFG_GT
ad_ip_parameter txoutclk_BUFG_GT CONFIG.C_BUF_TYPE {BUFG_GT}
ad_connect txoutclk_BUFG_GT/BUFG_GT_CE VCC
ad_connect txoutclk_BUFG_GT/BUFG_GT_CEMASK GND
ad_connect txoutclk_BUFG_GT/BUFG_GT_CLR GND
ad_connect txoutclk_BUFG_GT/BUFG_GT_CLRMASK GND
ad_connect txoutclk_BUFG_GT/BUFG_GT_DIV GND
ad_connect jesd204_phy_121/txoutclk txoutclk_BUFG_GT/BUFG_GT_I
set tx_link_clock txoutclk_BUFG_GT/BUFG_GT_O
ad_ip_instance util_ds_buf rxoutclk_BUFG_GT
ad_ip_parameter rxoutclk_BUFG_GT CONFIG.C_BUF_TYPE {BUFG_GT}
ad_connect rxoutclk_BUFG_GT/BUFG_GT_CE VCC
ad_connect rxoutclk_BUFG_GT/BUFG_GT_CEMASK GND
ad_connect rxoutclk_BUFG_GT/BUFG_GT_CLR GND
ad_connect rxoutclk_BUFG_GT/BUFG_GT_CLRMASK GND
ad_connect rxoutclk_BUFG_GT/BUFG_GT_DIV GND
ad_connect jesd204_phy_121/rxoutclk rxoutclk_BUFG_GT/BUFG_GT_I
set rx_link_clock rxoutclk_BUFG_GT/BUFG_GT_O
ad_connect $tx_link_clock jesd204_phy_121/tx_core_clk
ad_connect $tx_link_clock jesd204_phy_126/tx_core_clk
ad_connect $tx_link_clock axi_mxfe_tx_jesd/link_clk
ad_connect tx_device_clk axi_mxfe_tx_jesd/device_clk ad_connect tx_device_clk axi_mxfe_tx_jesd/device_clk
ad_connect rx_device_clk jesd204_phy_121/rx_core_clk ad_connect $rx_link_clock jesd204_phy_121/rx_core_clk
ad_connect rx_device_clk jesd204_phy_126/rx_core_clk ad_connect $rx_link_clock jesd204_phy_126/rx_core_clk
ad_connect $rx_link_clock axi_mxfe_rx_jesd/link_clk
ad_connect rx_device_clk axi_mxfe_rx_jesd/device_clk ad_connect rx_device_clk axi_mxfe_rx_jesd/device_clk
} }
# device clock domain # device clock domain
ad_connect rx_device_clk rx_mxfe_tpl_core/link_clk ad_connect rx_device_clk rx_mxfe_tpl_core/link_clk
ad_connect rx_device_clk util_mxfe_cpack/clk ad_connect rx_device_clk util_mxfe_cpack/clk
@ -328,10 +386,10 @@ ad_connect tx_device_clk_rstgen/peripheral_reset jesd204_phy_126/tx_sys_reset
ad_connect rx_device_clk_rstgen/peripheral_reset jesd204_phy_121/rx_sys_reset ad_connect rx_device_clk_rstgen/peripheral_reset jesd204_phy_121/rx_sys_reset
ad_connect rx_device_clk_rstgen/peripheral_reset jesd204_phy_126/rx_sys_reset ad_connect rx_device_clk_rstgen/peripheral_reset jesd204_phy_126/rx_sys_reset
ad_connect axi_mxfe_tx_jesd/tx_axi/core_reset jesd204_phy_121/tx_reset_gt ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy_121/tx_reset_gt
ad_connect axi_mxfe_rx_jesd/rx_axi/core_reset jesd204_phy_121/rx_reset_gt ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy_121/rx_reset_gt
ad_connect axi_mxfe_tx_jesd/tx_axi/core_reset jesd204_phy_126/tx_reset_gt ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy_126/tx_reset_gt
ad_connect axi_mxfe_rx_jesd/rx_axi/core_reset jesd204_phy_126/rx_reset_gt ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy_126/rx_reset_gt
} }
# #
# connect adc dataflow # connect adc dataflow

5
projects/ad9081_fmca_ebz/vcu118/system_bd.tcl
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@ -1,9 +1,8 @@
## ADC FIFO depth in samples per converter ## ADC FIFO depth in samples per converter
set adc_fifo_samples_per_converter [expr 64*1024] set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024]
## DAC FIFO depth in samples per converter ## DAC FIFO depth in samples per converter
set dac_fifo_samples_per_converter [expr 64*1024] set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024]
source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl

7
projects/ad9081_fmca_ebz/vcu118/system_project.tcl
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@ -11,6 +11,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# e.g. # e.g.
# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 # make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
# make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 # make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=24.75 REF_CLK_RATE=250 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12
# make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8 # make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
# RX_RATE,TX_RATE,REF_CLK_RATE used only in 64B66B mode # RX_RATE,TX_RATE,REF_CLK_RATE used only in 64B66B mode
@ -31,8 +32,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode # REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported # [RX/TX]_JESD_NP : Number of bits per sample
# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices # [RX/TX]_NUM_LINKS : Number of links
# #
adi_project ad9081_fmca_ebz_vcu118 0 [list \ adi_project ad9081_fmca_ebz_vcu118 0 [list \
@ -52,6 +53,8 @@ adi_project ad9081_fmca_ebz_vcu118 0 [list \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \ TX_JESD_S [get_env_param TX_JESD_S 1 ] \
TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \
TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \
] ]
adi_project_files ad9081_fmca_ebz_vcu118 [list \ adi_project_files ad9081_fmca_ebz_vcu118 [list \

3
projects/ad9081_fmca_ebz/zc706/system_project.tcl
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@ -10,6 +10,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# e.g. # e.g.
# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1 # make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1
# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 # make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1
# make RX_JESD_L=2 RX_JESD_M=8 RX_JESD_S=1 RX_JESD_NP=12 TX_JESD_L=2 TX_JESD_M=8 TX_JESD_S=1 TX_JESD_NP=12
# #
# Parameter description: # Parameter description:
@ -27,7 +28,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode # REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported # [RX/TX]_JESD_NP : Number of bits per sample
# [RX/TX]_NUM_LINKS : Number of links # [RX/TX]_NUM_LINKS : Number of links
# #
# #