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arradio- timing violations fix

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Rejeesh Kutty 2017-07-20 15:08:21 -04:00
parent 36a9ea40b1
commit d132ed45cd
2 changed files with 6 additions and 1 deletions
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2
library/axi_ad9361/altera/axi_ad9361_lvds_if_c5.v
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@ -93,7 +93,7 @@ module axi_ad9361_lvds_if_c5 (
// internal registers
reg pll_rst = 'd0;
reg pll_rst = 1'd1;
reg locked_int = 'd0;
reg tx_core_enable_int = 'd0;
reg tx_core_txnrx_int = 'd0;

5
projects/arradio/c5soc/system_constr.sdc
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@ -66,6 +66,11 @@ set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_dat
set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
# locked is async- most likely clock won't be running when deasserted
set_false_path -to [get_registers *axi_ad9361_lvds_if:i_dev_if|up_drp_locked_m1*]
# frame reader seems to use the wrong reset!
set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]