add: softspan support in adc_channel regmap (#1081)
docs/regmap/adi_regmap_adc.txt: - add softspan to regmap library/common/up_adc_channel.v - update copyright year header - add softspan to regmap library/common/up_adc_common.v - update minor version Signed-off-by: John Erasmus Mari Geronimo <Johnerasmusmari.Geronimo@analog.com>main
parent
4dee04f9c8
commit
d152ad1e9d
|
@ -955,6 +955,29 @@ ENDFIELD
|
|||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x010A
|
||||
REG_CHAN_CNTRL_4
|
||||
ADC Interface Control & Status
|
||||
ENDREG
|
||||
|
||||
FIELD
|
||||
[31:3] 0x00000000
|
||||
RESERVED[28:0]
|
||||
RO
|
||||
Reserved for backward compatibility.
|
||||
ENDFIELD
|
||||
|
||||
FIELD
|
||||
[2:0] 0x7
|
||||
SOFTSPAN [2:0]
|
||||
RW
|
||||
Softspan configuration register.
|
||||
ENDFIELD
|
||||
|
||||
############################################################################################
|
||||
############################################################################################
|
||||
|
||||
REG
|
||||
0x0110
|
||||
REG_*
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
|
@ -69,6 +69,7 @@ module up_adc_channel #(
|
|||
input [31:0] adc_read_data,
|
||||
input [ 7:0] adc_status_header,
|
||||
input adc_crc_err,
|
||||
output [ 2:0] adc_softspan,
|
||||
output up_adc_crc_err,
|
||||
output up_adc_pn_err,
|
||||
output up_adc_pn_oos,
|
||||
|
@ -140,6 +141,7 @@ module up_adc_channel #(
|
|||
reg [15:0] up_adc_iqcor_coeff_tc_2 = 'd0;
|
||||
reg [ 3:0] up_adc_pnseq_sel_m = 'd0;
|
||||
reg [ 3:0] up_adc_data_sel_m = 'd0;
|
||||
reg [ 2:0] up_adc_softspan_int = 3'h7;
|
||||
|
||||
// internal signals
|
||||
|
||||
|
@ -151,6 +153,7 @@ module up_adc_channel #(
|
|||
wire up_adc_or_s;
|
||||
wire [31:0] up_adc_read_data_s;
|
||||
wire [ 7:0] up_adc_status_header_s;
|
||||
wire [ 2:0] up_adc_softspan_s;
|
||||
|
||||
// 2's complement function
|
||||
|
||||
|
@ -179,6 +182,7 @@ module up_adc_channel #(
|
|||
assign up_usr_datatype_bits = up_usr_datatype_bits_int;
|
||||
assign up_usr_decimation_m = up_usr_decimation_m_int;
|
||||
assign up_usr_decimation_n = up_usr_decimation_n_int;
|
||||
assign up_adc_softspan_s = up_adc_softspan_int;
|
||||
|
||||
// decode block select
|
||||
|
||||
|
@ -391,6 +395,16 @@ module up_adc_channel #(
|
|||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_adc_softspan_int <= 3'd7;
|
||||
end else begin
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hA)) begin
|
||||
up_adc_softspan_int <= up_wdata[2:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// processor read interface
|
||||
|
||||
assign up_rack = up_rack_int;
|
||||
|
@ -417,6 +431,7 @@ module up_adc_channel #(
|
|||
adc_usr_datatype_shift, adc_usr_datatype_total_bits,
|
||||
adc_usr_datatype_bits};
|
||||
4'h9: up_rdata_int <= { adc_usr_decimation_m, adc_usr_decimation_n};
|
||||
4'hA: up_rdata_int <= { 29'd0, up_adc_softspan_int};
|
||||
default: up_rdata_int <= 0;
|
||||
endcase
|
||||
end else begin
|
||||
|
@ -460,7 +475,7 @@ module up_adc_channel #(
|
|||
// adc control & status
|
||||
|
||||
up_xfer_cntrl #(
|
||||
.DATA_WIDTH(78)
|
||||
.DATA_WIDTH(81)
|
||||
) i_xfer_cntrl (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
|
@ -475,7 +490,8 @@ module up_adc_channel #(
|
|||
up_adc_iqcor_coeff_tc_1,
|
||||
up_adc_iqcor_coeff_tc_2,
|
||||
up_adc_pnseq_sel_m,
|
||||
up_adc_data_sel_m}),
|
||||
up_adc_data_sel_m,
|
||||
up_adc_softspan_s}),
|
||||
.up_xfer_done (),
|
||||
.d_rst (adc_rst),
|
||||
.d_clk (adc_clk),
|
||||
|
@ -490,7 +506,8 @@ module up_adc_channel #(
|
|||
adc_iqcor_coeff_1,
|
||||
adc_iqcor_coeff_2,
|
||||
adc_pnseq_sel,
|
||||
adc_data_sel}));
|
||||
adc_data_sel,
|
||||
adc_softspan}));
|
||||
|
||||
up_xfer_status #(
|
||||
.DATA_WIDTH(44)
|
||||
|
|
|
@ -131,7 +131,7 @@ module up_adc_common #(
|
|||
|
||||
// parameters
|
||||
|
||||
localparam VERSION = 32'h000a0262;
|
||||
localparam VERSION = 32'h000a0300;
|
||||
|
||||
// internal registers
|
||||
|
||||
|
|
Loading…
Reference in New Issue