diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v b/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
index b468ee659..f561d979e 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
@@ -101,7 +101,7 @@ i_cdc_sync (
   .out_resetn(1'b1),
   .out(status_sync)
 );
-assign status_sync_masked = status_sync ^ cfg_links_disable;
+assign status_sync_masked = status_sync | cfg_links_disable;
 
 always @(posedge clk) begin
   if (reset == 1'b1) begin
diff --git a/library/jesd204/tb/tx_tb.v b/library/jesd204/tb/tx_tb.v
index 9ddbdea7d..84bc009e3 100644
--- a/library/jesd204/tb/tx_tb.v
+++ b/library/jesd204/tb/tx_tb.v
@@ -44,36 +44,19 @@
 
 module tx_tb;
   parameter VCD_FILE = "tx_tb.vcd";
-  parameter NUM_LANES = 1;
-  parameter NUM_LINKS = 1;
+  parameter NUM_LANES = 4;
+  parameter NUM_LINKS = 2;
   parameter OCTETS_PER_FRAME = 4;
   parameter FRAMES_PER_MULTIFRAME = 32;
 
   `include "tb_base.v"
 
-  reg [31:0] tx_data = 'h00000000;
-  wire tx_ready;
-
-  always @(posedge clk) begin
-    if (reset == 1'b1) begin
-      tx_data <= 'h00000000;
-    end else if (tx_ready == 1'b1) begin
-      tx_data <= tx_data + 1'b1;
-    end
-  end
 
   reg [NUM_LINKS-1:0] sync = {NUM_LINKS{1'b1}};
   reg [31:0] counter = 'h00;
+  reg [31:0] tx_data = 'h00000000;
 
-  always @(posedge clk) begin
-    counter <= counter + 1'b1;
-    if (counter >= 'h10 && counter <= 'h30) begin
-      sync <= {NUM_LINKS{1'b0}};
-    end else begin
-      sync <= {NUM_LINKS{1'b1}};
-    end
-  end
-
+  wire tx_ready;
   wire [NUM_LANES-1:0] cfg_lanes_disable;
   wire [NUM_LINKS-1:0] cfg_links_disable;
   wire [7:0] cfg_beats_per_multiframe;
@@ -87,11 +70,42 @@ module tx_tb;
   wire [7:0] cfg_mframes_per_ilas;
   wire cfg_disable_char_replacement;
   wire cfg_disable_scrambler;
-
   wire tx_ilas_config_rd;
   wire [1:0] tx_ilas_config_addr;
   wire [32*NUM_LANES-1:0] tx_ilas_config_data;
 
+  always @(posedge clk) begin
+    if (reset == 1'b1) begin
+      tx_data <= 'h00000000;
+    end else if (tx_ready == 1'b1) begin
+      tx_data <= tx_data + 1'b1;
+    end
+  end
+
+  /* Generate independent SYNCs
+  *
+  *  Each SYNC will be asserted/deasserted at different clock edges.
+  *  The assertion/deassertion order: first SYNC[0], ..., last SYNC[NUM_LINKS-1]
+  */
+  always @(posedge clk) begin
+    counter <= counter + 1'b1;
+  end
+
+  genvar i;
+  generate
+    for (i=1; i<=NUM_LINKS; i=i+1) begin: SYNC_GENERATOR
+      always @(posedge clk) begin
+        if (counter >= (32'h100 | (i << 4)) && counter <= (32'h300 | (i << 4))) begin
+          sync[i-1] <= 1'b0;
+        end else begin
+          sync[i-1] <= 1'b1;
+        end
+      end
+    end
+  endgenerate
+
+  // DUT with static configuration
+
   jesd204_tx_static_config #(
     .NUM_LANES(NUM_LANES),
     .NUM_LINKS(NUM_LINKS),
@@ -142,6 +156,8 @@ module tx_tb;
     .ilas_config_addr(tx_ilas_config_addr),
     .ilas_config_data(tx_ilas_config_data),
 
+    .ctrl_manual_sync_request (1'b0),
+
     .tx_ready(tx_ready),
     .tx_data({NUM_LANES{tx_data}}),