From d1e638349b129d324b4f15e7b99a3084cfbace0b Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 19 Jan 2016 11:18:00 +0200 Subject: [PATCH] ad_serdes_clk : The reference clock selection line should by tied to 1 Just the CLKIN1 is used in the MMCM. --- library/common/ad_serdes_clk.v | 1 + 1 file changed, 1 insertion(+) diff --git a/library/common/ad_serdes_clk.v b/library/common/ad_serdes_clk.v index 6adb1811f..7022ae785 100644 --- a/library/common/ad_serdes_clk.v +++ b/library/common/ad_serdes_clk.v @@ -115,6 +115,7 @@ module ad_serdes_clk ( .MMCM_CLK1_DIV (MMCM_CLK1_DIV)) i_mmcm_drp ( .clk (clk_in_s), + .clk_sel (1'b1), .mmcm_rst (mmcm_rst), .mmcm_clk_0 (clk), .mmcm_clk_1 (div_clk),