ad_serdes_clk : The reference clock selection line should by tied to 1
Just the CLKIN1 is used in the MMCM.main
parent
c6cfd1a2b6
commit
d1e638349b
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@ -115,6 +115,7 @@ module ad_serdes_clk (
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.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
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.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
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i_mmcm_drp (
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i_mmcm_drp (
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.clk (clk_in_s),
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.clk (clk_in_s),
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.clk_sel (1'b1),
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.mmcm_rst (mmcm_rst),
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.mmcm_rst (mmcm_rst),
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.mmcm_clk_0 (clk),
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.mmcm_clk_0 (clk),
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.mmcm_clk_1 (div_clk),
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.mmcm_clk_1 (div_clk),
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