diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl index 2844d5a5d..eb28df04f 100755 --- a/library/axi_ad9144/axi_ad9144_hw.tcl +++ b/library/axi_ad9144/axi_ad9144_hw.tcl @@ -90,18 +90,24 @@ ad_alt_intf signal tx_data output 128*(QUAD_OR_DUAL_N+1) data ad_alt_intf clock dac_clk output 1 -add_interface fifo_ch_0_out conduit end -add_interface_port fifo_ch_0_out dac_enable_0 enable Output 1 -add_interface_port fifo_ch_0_out dac_valid_0 valid Output 1 -add_interface_port fifo_ch_0_out dac_data_0 data Input 64 +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_enable_0 enable Output 1 +add_interface_port dac_ch_0 dac_valid_0 valid Output 1 +add_interface_port dac_ch_0 dac_ddata_0 data Input 64 -add_interface fifo_ch_1_out conduit end -add_interface_port fifo_ch_1_out dac_enable_1 enable Output 1 -add_interface_port fifo_ch_1_out dac_valid_1 valid Output 1 -add_interface_port fifo_ch_1_out dac_data_1 data Input 64 +set_interface_property dac_ch_0 associatedClock if_tx_clk +set_interface_property dac_ch_0 associatedReset none -ad_alt_intf signal dac_dovf input 1 -ad_alt_intf signal dac_dunf input 1 +add_interface dac_ch_1 conduit end +add_interface_port dac_ch_1 dac_enable_1 enable Output 1 +add_interface_port dac_ch_1 dac_valid_1 valid Output 1 +add_interface_port dac_ch_1 dac_ddata_1 data Input 64 + +set_interface_property dac_ch_1 associatedClock if_tx_clk +set_interface_property dac_ch_1 associatedReset none + +ad_alt_intf signal dac_dovf input 1 ovf +ad_alt_intf signal dac_dunf input 1 unf proc p_axi_ad9144 {} { @@ -109,15 +115,20 @@ proc p_axi_ad9144 {} { if {[get_parameter_value QUAD_OR_DUAL_N] == 1} { - add_interface fifo_ch_2_out conduit end - add_interface_port fifo_ch_2_out dac_enable_2 enable Output 1 - add_interface_port fifo_ch_2_out dac_valid_2 valid Output 1 - add_interface_port fifo_ch_2_out dac_data_2 data Input 64 + add_interface dac_ch_2 conduit end + add_interface_port dac_ch_2 dac_enable_2 enable Output 1 + add_interface_port dac_ch_2 dac_valid_2 valid Output 1 + add_interface_port dac_ch_2 dac_ddata_2 data Input 64 - add_interface fifo_ch_3_out conduit end - add_interface_port fifo_ch_3_out dac_enable_3 enable Output 1 - add_interface_port fifo_ch_3_out dac_valid_3 valid Output 1 - add_interface_port fifo_ch_3_out dac_data_3 data Input 64 + set_interface_property dac_ch_2 associatedClock if_tx_clk + set_interface_property dac_ch_2 associatedReset none + add_interface dac_ch_3 conduit end + add_interface_port dac_ch_3 dac_enable_3 enable Output 1 + add_interface_port dac_ch_3 dac_valid_3 valid Output 1 + add_interface_port dac_ch_3 dac_ddata_3 data Input 64 + + set_interface_property dac_ch_3 associatedClock if_tx_clk + set_interface_property dac_ch_3 associatedReset none } } diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl index 4a91fa68c..b103f2d9c 100755 --- a/library/axi_ad9680/axi_ad9680_hw.tcl +++ b/library/axi_ad9680/axi_ad9680_hw.tcl @@ -80,16 +80,22 @@ ad_alt_intf signal rx_data input 128 data ad_alt_intf clock adc_clock output 1 -add_interface fifo_ch_0 conduit end -add_interface_port fifo_ch_0 adc_enable_0 enable Output 1 -add_interface_port fifo_ch_0 adc_valid_0 valid Output 1 -add_interface_port fifo_ch_0 adc_data_0 data Output 64 +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_enable_0 enable Output 1 +add_interface_port adc_ch_0 adc_valid_0 valid Output 1 +add_interface_port adc_ch_0 adc_data_0 data Output 64 -add_interface fifo_ch_1 conduit end -add_interface_port fifo_ch_1 adc_enable_1 enable Output 1 -add_interface_port fifo_ch_1 adc_valid_1 valid Output 1 -add_interface_port fifo_ch_1 adc_data_1 data Output 64 +set_interface_property adc_ch_0 associatedClock if_rx_clk +set_interface_property adc_ch_0 associatedReset none -ad_alt_intf signal adc_dovf input 1 -ad_alt_intf signal adc_dunf input 1 +add_interface adc_ch_1 conduit end +add_interface_port adc_ch_1 adc_enable_1 enable Output 1 +add_interface_port adc_ch_1 adc_valid_1 valid Output 1 +add_interface_port adc_ch_1 adc_data_1 data Output 64 + +set_interface_property adc_ch_1 associatedClock if_rx_clk +set_interface_property adc_ch_1 associatedReset none + +ad_alt_intf signal adc_dovf input 1 ovf +ad_alt_intf signal adc_dunf input 1 unf diff --git a/library/util_adcfifo/util_adcfifo_hw.tcl b/library/util_adcfifo/util_adcfifo_hw.tcl index 95cc93bcc..73784bf58 100755 --- a/library/util_adcfifo/util_adcfifo_hw.tcl +++ b/library/util_adcfifo/util_adcfifo_hw.tcl @@ -57,7 +57,7 @@ ad_alt_intf clock adc_clk input 1 adc_clk ad_alt_intf reset adc_rst input 1 if_adc_clk ad_alt_intf signal adc_wr input 1 valid ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data -ad_alt_intf signal adc_wovf output 1 adc_dovf +ad_alt_intf signal adc_wovf output 1 ovf ad_alt_intf clock dma_clk input 1 clk ad_alt_intf signal dma_wr output 1 valid