diff --git a/library/axi_ad9152/Makefile b/library/axi_ad9152/Makefile index aa24c9a38..2a6473e3f 100644 --- a/library/axi_ad9152/Makefile +++ b/library/axi_ad9152/Makefile @@ -5,33 +5,32 @@ LIBRARY_NAME := axi_ad9152 -GENERIC_DEPS += ../common/ad_dds.v -GENERIC_DEPS += ../common/ad_dds_1.v -GENERIC_DEPS += ../common/ad_dds_sine.v -GENERIC_DEPS += ../common/ad_rst.v -GENERIC_DEPS += ../common/up_axi.v -GENERIC_DEPS += ../common/up_clock_mon.v -GENERIC_DEPS += ../common/up_dac_channel.v -GENERIC_DEPS += ../common/up_dac_common.v -GENERIC_DEPS += ../common/up_xfer_cntrl.v -GENERIC_DEPS += ../common/up_xfer_status.v GENERIC_DEPS += axi_ad9152.v -GENERIC_DEPS += axi_ad9152_channel.v -GENERIC_DEPS += axi_ad9152_core.v -GENERIC_DEPS += axi_ad9152_if.v -XILINX_DEPS += ../xilinx/common/ad_mul.v -XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc -XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc -XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc -XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc XILINX_DEPS += axi_ad9152_ip.tcl +XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac + ALTERA_DEPS += ../altera/common/ad_mul.v ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc ALTERA_DEPS += ../altera/common/up_rst_constr.sdc ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc +ALTERA_DEPS += ../common/ad_dds.v +ALTERA_DEPS += ../common/ad_dds_1.v +ALTERA_DEPS += ../common/ad_dds_sine.v +ALTERA_DEPS += ../common/ad_rst.v +ALTERA_DEPS += ../common/up_axi.v +ALTERA_DEPS += ../common/up_clock_mon.v +ALTERA_DEPS += ../common/up_dac_channel.v +ALTERA_DEPS += ../common/up_dac_common.v +ALTERA_DEPS += ../common/up_xfer_cntrl.v +ALTERA_DEPS += ../common/up_xfer_status.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v ALTERA_DEPS += axi_ad9152_hw.tcl include ../scripts/library.mk diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v index 516dd39d1..b584f7494 100644 --- a/library/axi_ad9152/axi_ad9152.v +++ b/library/axi_ad9152/axi_ad9152.v @@ -83,117 +83,46 @@ module axi_ad9152 #( output [ 1:0] s_axi_rresp, input s_axi_rready); + assign dac_clk = tx_clk; - // internal clocks and resets + ad_ip_jesd204_tpl_dac #( + .ID(ID), + .NUM_LANES(4), + .NUM_CHANNELS(2), + .DAC_DATAPATH_DISABLE(DAC_DATAPATH_DISABLE) + ) i_dac_jesd204 ( + .link_clk (tx_clk), - wire dac_rst; - wire up_clk; - wire up_rstn; + .link_valid (tx_valid), + .link_data (tx_data), + .link_ready (tx_ready), - // internal signals - - wire [ 15:0] dac_data_0_0_s; - wire [ 15:0] dac_data_0_1_s; - wire [ 15:0] dac_data_0_2_s; - wire [ 15:0] dac_data_0_3_s; - wire [ 15:0] dac_data_1_0_s; - wire [ 15:0] dac_data_1_1_s; - wire [ 15:0] dac_data_1_2_s; - wire [ 15:0] dac_data_1_3_s; - wire up_wreq_s; - wire [ 13:0] up_waddr_s; - wire [ 31:0] up_wdata_s; - wire up_wack_s; - wire up_rreq_s; - wire [ 13:0] up_raddr_s; - wire [ 31:0] up_rdata_s; - wire up_rack_s; - - // signal name changes - - assign up_clk = s_axi_aclk; - assign up_rstn = s_axi_aresetn; - assign tx_valid = 1'b1; - - // device interface - - axi_ad9152_if i_if ( - .tx_clk (tx_clk), - .tx_data (tx_data), - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_data_0_0 (dac_data_0_0_s), - .dac_data_0_1 (dac_data_0_1_s), - .dac_data_0_2 (dac_data_0_2_s), - .dac_data_0_3 (dac_data_0_3_s), - .dac_data_1_0 (dac_data_1_0_s), - .dac_data_1_1 (dac_data_1_1_s), - .dac_data_1_2 (dac_data_1_2_s), - .dac_data_1_3 (dac_data_1_3_s)); - - // core - - axi_ad9152_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core ( - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_data_0_0 (dac_data_0_0_s), - .dac_data_0_1 (dac_data_0_1_s), - .dac_data_0_2 (dac_data_0_2_s), - .dac_data_0_3 (dac_data_0_3_s), - .dac_data_1_0 (dac_data_1_0_s), - .dac_data_1_1 (dac_data_1_1_s), - .dac_data_1_2 (dac_data_1_2_s), - .dac_data_1_3 (dac_data_1_3_s), - .dac_valid_0 (dac_valid_0), - .dac_enable_0 (dac_enable_0), - .dac_ddata_0 (dac_ddata_0), - .dac_valid_1 (dac_valid_1), - .dac_enable_1 (dac_enable_1), - .dac_ddata_1 (dac_ddata_1), + .enable ({dac_enable_1,dac_enable_0}), + .dac_valid ({dac_valid_1,dac_valid_0}), + .dac_ddata ({dac_ddata_1,dac_ddata_0}), .dac_dunf (dac_dunf), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s), - .up_rack (up_rack_s)); - // up bus interface - - up_axi i_up_axi ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_axi_awvalid (s_axi_awvalid), - .up_axi_awaddr (s_axi_awaddr), - .up_axi_awready (s_axi_awready), - .up_axi_wvalid (s_axi_wvalid), - .up_axi_wdata (s_axi_wdata), - .up_axi_wstrb (s_axi_wstrb), - .up_axi_wready (s_axi_wready), - .up_axi_bvalid (s_axi_bvalid), - .up_axi_bresp (s_axi_bresp), - .up_axi_bready (s_axi_bready), - .up_axi_arvalid (s_axi_arvalid), - .up_axi_araddr (s_axi_araddr), - .up_axi_arready (s_axi_arready), - .up_axi_rvalid (s_axi_rvalid), - .up_axi_rresp (s_axi_rresp), - .up_axi_rdata (s_axi_rdata), - .up_axi_rready (s_axi_rready), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s), - .up_rack (up_rack_s)); + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awprot (s_axi_awprot), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + .s_axi_bresp (s_axi_bresp), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arprot (s_axi_arprot), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp) + ); endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad9152/axi_ad9152_channel.v b/library/axi_ad9152/axi_ad9152_channel.v deleted file mode 100644 index ceb67d9ab..000000000 --- a/library/axi_ad9152/axi_ad9152_channel.v +++ /dev/null @@ -1,432 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_ad9152_channel #( - - parameter CHANNEL_ID = 32'h0, - parameter DATAPATH_DISABLE = 0) ( - - // dac interface - - input dac_clk, - input dac_rst, - output reg dac_enable, - output reg [63:0] dac_data, - input [63:0] dma_data, - - // processor interface - - input dac_data_sync, - input dac_dds_format, - - // bus interface - - input up_rstn, - input up_clk, - input up_wreq, - input [13:0] up_waddr, - input [31:0] up_wdata, - output up_wack, - input up_rreq, - input [13:0] up_raddr, - output [31:0] up_rdata, - output up_rack); - - - // internal registers - - reg [63:0] dac_pn7_data = 'd0; - reg [63:0] dac_pn15_data = 'd0; - reg [15:0] dac_dds_phase_0_0 = 'd0; - reg [15:0] dac_dds_phase_0_1 = 'd0; - reg [15:0] dac_dds_phase_1_0 = 'd0; - reg [15:0] dac_dds_phase_1_1 = 'd0; - reg [15:0] dac_dds_phase_2_0 = 'd0; - reg [15:0] dac_dds_phase_2_1 = 'd0; - reg [15:0] dac_dds_phase_3_0 = 'd0; - reg [15:0] dac_dds_phase_3_1 = 'd0; - reg [15:0] dac_dds_incr_0 = 'd0; - reg [15:0] dac_dds_incr_1 = 'd0; - reg [63:0] dac_dds_data = 'd0; - - // internal signals - - wire [15:0] dac_dds_data_0_s; - wire [15:0] dac_dds_data_1_s; - wire [15:0] dac_dds_data_2_s; - wire [15:0] dac_dds_data_3_s; - wire [15:0] dac_dds_scale_1_s; - wire [15:0] dac_dds_init_1_s; - wire [15:0] dac_dds_incr_1_s; - wire [15:0] dac_dds_scale_2_s; - wire [15:0] dac_dds_init_2_s; - wire [15:0] dac_dds_incr_2_s; - wire [15:0] dac_pat_data_1_s; - wire [15:0] dac_pat_data_2_s; - wire [ 3:0] dac_data_sel_s; - wire [63:0] dac_pn7_data_i_s; - wire [63:0] dac_pn15_data_i_s; - wire [63:0] dac_pn7_data_s; - wire [63:0] dac_pn15_data_s; - - // PN7 function - - function [63:0] pn7; - input [7:0] din; - reg [63:0] dout; - begin - dout[15] = din[ 6] ^ din[ 5]; - dout[14] = din[ 5] ^ din[ 4]; - dout[13] = din[ 4] ^ din[ 3]; - dout[12] = din[ 3] ^ din[ 2]; - dout[11] = din[ 2] ^ din[ 1]; - dout[10] = din[ 1] ^ din[ 0]; - dout[ 9] = din[ 0] ^ din[ 6] ^ din[ 5]; - dout[ 8] = din[ 6] ^ din[ 4]; - dout[ 7] = din[ 5] ^ din[ 3]; - dout[ 6] = din[ 4] ^ din[ 2]; - dout[ 5] = din[ 3] ^ din[ 1]; - dout[ 4] = din[ 2] ^ din[ 0]; - dout[ 3] = din[ 1] ^ din[ 6] ^ din[ 5]; - dout[ 2] = din[ 0] ^ din[ 5] ^ din[ 4]; - dout[ 1] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; - dout[ 0] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; - dout[31] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; - dout[30] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; - dout[29] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5]; - dout[28] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4]; - dout[27] = din[ 0] ^ din[ 6] ^ din[ 3]; - dout[26] = din[ 6] ^ din[ 2]; - dout[25] = din[ 5] ^ din[ 1]; - dout[24] = din[ 4] ^ din[ 0]; - dout[23] = din[ 3] ^ din[ 6] ^ din[ 5]; - dout[22] = din[ 2] ^ din[ 5] ^ din[ 4]; - dout[21] = din[ 1] ^ din[ 4] ^ din[ 3]; - dout[20] = din[ 0] ^ din[ 3] ^ din[ 2]; - dout[19] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1]; - dout[18] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0]; - dout[17] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5]; - dout[16] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4]; - dout[47] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3]; - dout[46] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2]; - dout[45] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1]; - dout[44] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; - dout[43] = din[ 1] ^ din[ 3] ^ din[ 6]; - dout[42] = din[ 0] ^ din[ 5] ^ din[ 2]; - dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1]; - dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0]; - dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5]; - dout[38] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4]; - dout[37] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3]; - dout[36] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2]; - dout[35] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1]; - dout[34] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0]; - dout[33] = din[ 0] ^ din[ 2] ^ din[ 6]; - dout[32] = din[ 6] ^ din[ 1]; - dout[63] = din[ 5] ^ din[ 0]; - dout[62] = din[ 4] ^ din[ 6] ^ din[ 5]; - dout[61] = din[ 3] ^ din[ 5] ^ din[ 4]; - dout[60] = din[ 2] ^ din[ 4] ^ din[ 3]; - dout[59] = din[ 1] ^ din[ 3] ^ din[ 2]; - dout[58] = din[ 0] ^ din[ 2] ^ din[ 1]; - dout[57] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0]; - dout[56] = din[ 0] ^ din[ 4] ^ din[ 6]; - dout[55] = din[ 6] ^ din[ 3]; - dout[54] = din[ 5] ^ din[ 2]; - dout[53] = din[ 4] ^ din[ 1]; - dout[52] = din[ 3] ^ din[ 0]; - dout[51] = din[ 2] ^ din[ 6] ^ din[ 5]; - dout[50] = din[ 1] ^ din[ 5] ^ din[ 4]; - dout[49] = din[ 0] ^ din[ 4] ^ din[ 3]; - dout[48] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2]; - pn7 = dout; - end - endfunction - - // PN15 function - - function [63:0] pn15; - input [15:0] din; - reg [63:0] dout; - begin - dout[15] = din[14] ^ din[13]; - dout[14] = din[13] ^ din[12]; - dout[13] = din[12] ^ din[11]; - dout[12] = din[11] ^ din[10]; - dout[11] = din[10] ^ din[ 9]; - dout[10] = din[ 9] ^ din[ 8]; - dout[ 9] = din[ 8] ^ din[ 7]; - dout[ 8] = din[ 7] ^ din[ 6]; - dout[ 7] = din[ 6] ^ din[ 5]; - dout[ 6] = din[ 5] ^ din[ 4]; - dout[ 5] = din[ 4] ^ din[ 3]; - dout[ 4] = din[ 3] ^ din[ 2]; - dout[ 3] = din[ 2] ^ din[ 1]; - dout[ 2] = din[ 1] ^ din[ 0]; - dout[ 1] = din[ 0] ^ din[14] ^ din[13]; - dout[ 0] = din[14] ^ din[12]; - dout[31] = din[13] ^ din[11]; - dout[30] = din[12] ^ din[10]; - dout[29] = din[11] ^ din[ 9]; - dout[28] = din[10] ^ din[ 8]; - dout[27] = din[ 9] ^ din[ 7]; - dout[26] = din[ 8] ^ din[ 6]; - dout[25] = din[ 7] ^ din[ 5]; - dout[24] = din[ 6] ^ din[ 4]; - dout[23] = din[ 5] ^ din[ 3]; - dout[22] = din[ 4] ^ din[ 2]; - dout[21] = din[ 3] ^ din[ 1]; - dout[20] = din[ 2] ^ din[ 0]; - dout[19] = din[ 1] ^ din[14] ^ din[13]; - dout[18] = din[ 0] ^ din[13] ^ din[12]; - dout[17] = din[14] ^ din[12] ^ din[13] ^ din[11]; - dout[16] = din[13] ^ din[11] ^ din[12] ^ din[10]; - dout[47] = din[12] ^ din[10] ^ din[11] ^ din[ 9]; - dout[46] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8]; - dout[45] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7]; - dout[44] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6]; - dout[43] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5]; - dout[42] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; - dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; - dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; - dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; - dout[38] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; - dout[37] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13]; - dout[36] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12]; - dout[35] = din[ 0] ^ din[14] ^ din[11]; - dout[34] = din[14] ^ din[10]; - dout[33] = din[13] ^ din[ 9]; - dout[32] = din[12] ^ din[ 8]; - dout[63] = din[11] ^ din[ 7]; - dout[62] = din[10] ^ din[ 6]; - dout[61] = din[ 9] ^ din[ 5]; - dout[60] = din[ 8] ^ din[ 4]; - dout[59] = din[ 7] ^ din[ 3]; - dout[58] = din[ 6] ^ din[ 2]; - dout[57] = din[ 5] ^ din[ 1]; - dout[56] = din[ 4] ^ din[ 0]; - dout[55] = din[ 3] ^ din[14] ^ din[13]; - dout[54] = din[ 2] ^ din[13] ^ din[12]; - dout[53] = din[ 1] ^ din[12] ^ din[11]; - dout[52] = din[ 0] ^ din[11] ^ din[10]; - dout[51] = din[14] ^ din[10] ^ din[13] ^ din[ 9]; - dout[50] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8]; - dout[49] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7]; - dout[48] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6]; - pn15 = dout; - end - endfunction - - assign dac_pn7_data_i_s = ~dac_pn7_data; - assign dac_pn15_data_i_s = ~dac_pn15_data; - - assign dac_pn7_data_s = dac_pn7_data; - assign dac_pn15_data_s = dac_pn15_data; - - // dac data select - - always @(posedge dac_clk) begin - dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; - case (dac_data_sel_s) - 4'h7: dac_data <= dac_pn15_data_s; - 4'h6: dac_data <= dac_pn7_data_s; - 4'h5: dac_data <= dac_pn15_data_i_s; - 4'h4: dac_data <= dac_pn7_data_i_s; - 4'h3: dac_data <= 64'd0; - 4'h2: dac_data <= dma_data; - 4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s, - dac_pat_data_2_s, dac_pat_data_1_s}; - default: dac_data <= dac_dds_data; - endcase - end - - // pn registers - - always @(posedge dac_clk) begin - if (dac_data_sync == 1'b1) begin - dac_pn7_data <= {64{1'd1}}; - dac_pn15_data <= {64{1'd1}}; - end else begin - dac_pn7_data <= pn7(dac_pn7_data[55:48]); - dac_pn15_data <= pn15(dac_pn15_data[63:48]); - end - end - - // dds - - always @(posedge dac_clk) begin - if (dac_data_sync == 1'b1) begin - dac_dds_phase_0_0 <= dac_dds_init_1_s; - dac_dds_phase_0_1 <= dac_dds_init_2_s; - dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s; - dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s; - dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s; - dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s; - dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s; - dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s; - dac_dds_incr_0 <= {dac_dds_incr_1_s[13:0], 2'd0}; - dac_dds_incr_1 <= {dac_dds_incr_2_s[13:0], 2'd0}; - dac_dds_data <= 64'd0; - end else begin - dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0; - dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1; - dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0; - dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1; - dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0; - dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1; - dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0; - dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1; - dac_dds_incr_0 <= dac_dds_incr_0; - dac_dds_incr_1 <= dac_dds_incr_1; - dac_dds_data <= { dac_dds_data_3_s, dac_dds_data_2_s, - dac_dds_data_1_s, dac_dds_data_0_s}; - end - end - - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_0_s = 16'd0; - end else begin - ad_dds i_dds_0 ( - .clk (dac_clk), - .dds_format (dac_dds_format), - .dds_phase_0 (dac_dds_phase_0_0), - .dds_scale_0 (dac_dds_scale_1_s), - .dds_phase_1 (dac_dds_phase_0_1), - .dds_scale_1 (dac_dds_scale_2_s), - .dds_data (dac_dds_data_0_s)); - end - endgenerate - - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_1_s = 16'd0; - end else begin - ad_dds i_dds_1 ( - .clk (dac_clk), - .dds_format (dac_dds_format), - .dds_phase_0 (dac_dds_phase_1_0), - .dds_scale_0 (dac_dds_scale_1_s), - .dds_phase_1 (dac_dds_phase_1_1), - .dds_scale_1 (dac_dds_scale_2_s), - .dds_data (dac_dds_data_1_s)); - end - endgenerate - - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_2_s = 16'd0; - end else begin - ad_dds i_dds_2 ( - .clk (dac_clk), - .dds_format (dac_dds_format), - .dds_phase_0 (dac_dds_phase_2_0), - .dds_scale_0 (dac_dds_scale_1_s), - .dds_phase_1 (dac_dds_phase_2_1), - .dds_scale_1 (dac_dds_scale_2_s), - .dds_data (dac_dds_data_2_s)); - end - endgenerate - - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_3_s = 16'd0; - end else begin - ad_dds i_dds_3 ( - .clk (dac_clk), - .dds_format (dac_dds_format), - .dds_phase_0 (dac_dds_phase_3_0), - .dds_scale_0 (dac_dds_scale_1_s), - .dds_phase_1 (dac_dds_phase_3_1), - .dds_scale_1 (dac_dds_scale_2_s), - .dds_data (dac_dds_data_3_s)); - end - endgenerate - - // single channel processor - - up_dac_channel #( - .COMMON_ID (6'h11), - .CHANNEL_ID(CHANNEL_ID), - .DDS_DISABLE (0), - .USERPORTS_DISABLE (0), - .IQCORRECTION_DISABLE (0)) - i_up_dac_channel ( - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_dds_scale_1 (dac_dds_scale_1_s), - .dac_dds_init_1 (dac_dds_init_1_s), - .dac_dds_incr_1 (dac_dds_incr_1_s), - .dac_dds_scale_2 (dac_dds_scale_2_s), - .dac_dds_init_2 (dac_dds_init_2_s), - .dac_dds_incr_2 (dac_dds_incr_2_s), - .dac_pat_data_1 (dac_pat_data_1_s), - .dac_pat_data_2 (dac_pat_data_2_s), - .dac_data_sel (dac_data_sel_s), - .dac_iq_mode (), - .dac_iqcor_enb (), - .dac_iqcor_coeff_1 (), - .dac_iqcor_coeff_2 (), - .up_usr_datatype_be (), - .up_usr_datatype_signed (), - .up_usr_datatype_shift (), - .up_usr_datatype_total_bits (), - .up_usr_datatype_bits (), - .up_usr_interpolation_m (), - .up_usr_interpolation_n (), - .dac_usr_datatype_be (1'b0), - .dac_usr_datatype_signed (1'b1), - .dac_usr_datatype_shift (8'd0), - .dac_usr_datatype_total_bits (8'd16), - .dac_usr_datatype_bits (8'd16), - .dac_usr_interpolation_m (16'd1), - .dac_usr_interpolation_n (16'd1), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata), - .up_rack (up_rack)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad9152/axi_ad9152_core.v b/library/axi_ad9152/axi_ad9152_core.v deleted file mode 100644 index fdbee9924..000000000 --- a/library/axi_ad9152/axi_ad9152_core.v +++ /dev/null @@ -1,213 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_ad9152_core #( - - parameter ID = 0, - parameter DATAPATH_DISABLE = 0) ( - - // dac interface - - input dac_clk, - output dac_rst, - output [15:0] dac_data_0_0, - output [15:0] dac_data_0_1, - output [15:0] dac_data_0_2, - output [15:0] dac_data_0_3, - output [15:0] dac_data_1_0, - output [15:0] dac_data_1_1, - output [15:0] dac_data_1_2, - output [15:0] dac_data_1_3, - - // dma interface - - output dac_valid_0, - output dac_enable_0, - input [63:0] dac_ddata_0, - output dac_valid_1, - output dac_enable_1, - input [63:0] dac_ddata_1, - input dac_dunf, - - // processor interface - - input up_rstn, - input up_clk, - input up_wreq, - input [13:0] up_waddr, - input [31:0] up_wdata, - output reg up_wack, - input up_rreq, - input [13:0] up_raddr, - output reg [31:0] up_rdata, - output reg up_rack); - - - // internal registers - - // internal signals - - wire dac_sync_s; - wire dac_datafmt_s; - wire [31:0] up_rdata_0_s; - wire up_rack_0_s; - wire up_wack_0_s; - wire [31:0] up_rdata_1_s; - wire up_rack_1_s; - wire up_wack_1_s; - wire [31:0] up_rdata_s; - wire up_rack_s; - wire up_wack_s; - - // dac valid - - assign dac_valid_0 = 1'b1; - assign dac_valid_1 = 1'b1; - assign dac_valid_2 = 1'b1; - assign dac_valid_3 = 1'b1; - - // processor read interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rdata <= 'd0; - up_rack <= 'd0; - up_wack <= 'd0; - end else begin - up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s; - up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s; - up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s; - end - end - - // dac channel - - axi_ad9152_channel #(.CHANNEL_ID(0), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_0 ( - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_enable (dac_enable_0), - .dac_data ({dac_data_0_3, dac_data_0_2, dac_data_0_1, dac_data_0_0}), - .dma_data (dac_ddata_0), - .dac_data_sync (dac_sync_s), - .dac_dds_format (dac_datafmt_s), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack_0_s), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata_0_s), - .up_rack (up_rack_0_s)); - - // dac channel - - axi_ad9152_channel #(.CHANNEL_ID(1), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_1 ( - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_enable (dac_enable_1), - .dac_data ({dac_data_1_3, dac_data_1_2, dac_data_1_1, dac_data_1_0}), - .dma_data (dac_ddata_1), - .dac_data_sync (dac_sync_s), - .dac_dds_format (dac_datafmt_s), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack_1_s), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata_1_s), - .up_rack (up_rack_1_s)); - - // dac common processor interface - - up_dac_common #( - .ID(ID), - .CONFIG (0), - .CLK_EDGE_SEL (0), - .COMMON_ID (6'h10), - .DRP_DISABLE (6'h00), - .USERPORTS_DISABLE (0), - .GPIO_DISABLE (0)) - i_up_dac_common ( - .mmcm_rst (), - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_sync (dac_sync_s), - .dac_frame (), - .dac_clksel (), - .dac_par_type (), - .dac_par_enb (), - .dac_r1_mode (), - .dac_datafmt (dac_datafmt_s), - .dac_datarate (), - .dac_status (1'b1), - .dac_status_unf (dac_dunf), - .dac_clk_ratio (32'd4), - .up_dac_ce (), - .up_pps_rcounter(32'd0), - .up_pps_status(1'd0), - .up_pps_irq_mask(), - .up_drp_sel (), - .up_drp_wr (), - .up_drp_addr (), - .up_drp_wdata (), - .up_drp_rdata (32'd0), - .up_drp_ready (1'd0), - .up_drp_locked (1'd1), - .up_usr_chanmax (), - .dac_usr_chanmax (8'd3), - .up_dac_gpio_in (32'd0), - .up_dac_gpio_out (), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack_s), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata_s), - .up_rack (up_rack_s)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl index b99e091ab..d72a239c2 100644 --- a/library/axi_ad9152/axi_ad9152_hw.tcl +++ b/library/axi_ad9152/axi_ad9152_hw.tcl @@ -12,27 +12,31 @@ set_module_property DISPLAY_NAME axi_ad9152 # files -add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" -set_fileset_property quartus_synth TOP_LEVEL axi_ad9152 -add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v -add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v -add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v -add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v -add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v -add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v -add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v -add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v -add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v -add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v -add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v -add_fileset_file axi_ad9152_channel.v VERILOG PATH axi_ad9152_channel.v -add_fileset_file axi_ad9152_core.v VERILOG PATH axi_ad9152_core.v -add_fileset_file axi_ad9152_if.v VERILOG PATH axi_ad9152_if.v -add_fileset_file axi_ad9152.v VERILOG PATH axi_ad9152.v TOP_LEVEL_FILE -add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc -add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc -add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc -add_fileset_file up_rst_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_rst_constr.sdc +ad_ip_files axi_ad9152 [list \ + $ad_hdl_dir/library/altera/common/ad_mul.v \ + $ad_hdl_dir/library/common/ad_dds_sine.v \ + $ad_hdl_dir/library/common/ad_dds_1.v \ + $ad_hdl_dir/library/common/ad_dds.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_dac_common.v \ + $ad_hdl_dir/library/common/up_dac_channel.v \ + \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v \ + \ + axi_ad9152.v \ + $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc \ + $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc \ + $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc \ + $ad_hdl_dir/library/altera/common/up_rst_constr.sdc \ +] # parameters diff --git a/library/axi_ad9152/axi_ad9152_if.v b/library/axi_ad9152/axi_ad9152_if.v deleted file mode 100644 index 14fce7521..000000000 --- a/library/axi_ad9152/axi_ad9152_if.v +++ /dev/null @@ -1,91 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** -// This is the dac physical interface (drives samples from the low speed clock to the -// dac clock domain. - -`timescale 1ns/100ps - -module axi_ad9152_if ( - - // jesd interface - // tx_clk is (line-rate/40) - - input tx_clk, - output reg [127:0] tx_data, - - // dac interface - - output dac_clk, - input dac_rst, - input [15:0] dac_data_0_0, - input [15:0] dac_data_0_1, - input [15:0] dac_data_0_2, - input [15:0] dac_data_0_3, - input [15:0] dac_data_1_0, - input [15:0] dac_data_1_1, - input [15:0] dac_data_1_2, - input [15:0] dac_data_1_3); - - // reorder data for the jesd links - - assign dac_clk = tx_clk; - - always @(posedge dac_clk) begin - if (dac_rst == 1'b1) begin - tx_data <= 128'd0; - end else begin - tx_data[127:120] <= dac_data_1_3[ 7: 0]; - tx_data[119:112] <= dac_data_1_2[ 7: 0]; - tx_data[111:104] <= dac_data_1_1[ 7: 0]; - tx_data[103: 96] <= dac_data_1_0[ 7: 0]; - tx_data[ 95: 88] <= dac_data_1_3[15: 8]; - tx_data[ 87: 80] <= dac_data_1_2[15: 8]; - tx_data[ 79: 72] <= dac_data_1_1[15: 8]; - tx_data[ 71: 64] <= dac_data_1_0[15: 8]; - tx_data[ 63: 56] <= dac_data_0_3[ 7: 0]; - tx_data[ 55: 48] <= dac_data_0_2[ 7: 0]; - tx_data[ 47: 40] <= dac_data_0_1[ 7: 0]; - tx_data[ 39: 32] <= dac_data_0_0[ 7: 0]; - tx_data[ 31: 24] <= dac_data_0_3[15: 8]; - tx_data[ 23: 16] <= dac_data_0_2[15: 8]; - tx_data[ 15: 8] <= dac_data_0_1[15: 8]; - tx_data[ 7: 0] <= dac_data_0_0[15: 8]; - end - end - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad9152/axi_ad9152_ip.tcl b/library/axi_ad9152/axi_ad9152_ip.tcl index 317634bda..43bda11da 100644 --- a/library/axi_ad9152/axi_ad9152_ip.tcl +++ b/library/axi_ad9152/axi_ad9152_ip.tcl @@ -5,28 +5,14 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9152 adi_ip_files axi_ad9152 [list \ - "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ - "$ad_hdl_dir/library/common/ad_dds_sine.v" \ - "$ad_hdl_dir/library/common/ad_dds_1.v" \ - "$ad_hdl_dir/library/common/ad_dds.v" \ - "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/up_axi.v" \ - "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ - "$ad_hdl_dir/library/common/up_xfer_status.v" \ - "$ad_hdl_dir/library/common/up_clock_mon.v" \ - "$ad_hdl_dir/library/common/up_dac_common.v" \ - "$ad_hdl_dir/library/common/up_dac_channel.v" \ - "axi_ad9152_channel.v" \ - "axi_ad9152_core.v" \ - "axi_ad9152_if.v" \ "axi_ad9152.v" ] adi_ip_properties axi_ad9152 +adi_ip_add_core_dependencies { \ + analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \ +} + set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] @@ -34,4 +20,3 @@ ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_co ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::save_core [ipx::current_core] -