util_dacfifo: Simplify the write into buffer validation

2018-09-05 09:30:49 +01:00 · 2018-09-05 09:30:49 +01:00 · d2939f2a44
parent fa32ea8f1f
commit d2939f2a44
1 changed files with 1 additions and 1 deletions
--- a/library/util_dacfifo/util_dacfifo_bypass.v
+++ b/library/util_dacfifo/util_dacfifo_bypass.v
@ -131,7 +131,7 @@ module util_dacfifo_bypass #(

  // write address generation for the asymmetric FIFO

-  assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
+  assign dma_mem_wea_s = dma_valid & dma_ready;

  always @(posedge dma_clk) begin
    if (dma_rst == 1'b1) begin