diff --git a/library/util_dacfifo/util_dacfifo_bypass.v b/library/util_dacfifo/util_dacfifo_bypass.v
index 62d99a460..042e3941d 100644
--- a/library/util_dacfifo/util_dacfifo_bypass.v
+++ b/library/util_dacfifo/util_dacfifo_bypass.v
@@ -131,7 +131,7 @@ module util_dacfifo_bypass #(
 
   // write address generation for the asymmetric FIFO
 
-  assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
+  assign dma_mem_wea_s = dma_valid & dma_ready;
 
   always @(posedge dma_clk) begin
     if (dma_rst == 1'b1) begin