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axi_fmcadc5_sync: add a calibration signal generation

main
Rejeesh Kutty 2017-04-28 11:13:12 -04:00
parent 7a53b99b8b
commit d29f420ffa
3 changed files with 45 additions and 2 deletions
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39
library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
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@ -55,6 +55,11 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
output rx_sync_1_p,
output rx_sync_1_n,
// calibration signal
output vcal,
output vcal_enable,
// switching regulator clocks
output psync,
@ -107,6 +112,10 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
reg [ 7:0] up_psync_count = 'd0;
reg up_psync = 'd0;
reg [ 7:0] up_vcal_8 = 'd0;
reg up_vcal = 'd0;
reg [ 7:0] up_vcal_cnt = 'd0;
reg [ 1:0] up_vcal_enable = 'd0;
reg up_sysref_ack_t_m1 = 'd0;
reg up_sysref_ack_t_m2 = 'd0;
reg up_sysref_ack_t_m3 = 'd0;
@ -217,6 +226,34 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
end
end
// calibration signal register(s)
assign vcal = up_vcal;
assign vcal_enable = up_vcal_enable[0];
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_vcal_8 <= 8'd0;
up_vcal <= 1'd0;
up_vcal_cnt <= 8'd0;
up_vcal_enable <= 2'd0;
end else begin
if (up_vcal_8 >= up_vcal_cnt) begin
up_vcal_8 <= 8'd0;
up_vcal <= ~up_vcal & up_vcal_enable[1];
end else begin
up_vcal_8 <= up_vcal_8 + 1'b1;
up_vcal <= up_vcal;
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0050)) begin
up_vcal_cnt <= up_wdata_s[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0051)) begin
up_vcal_enable <= up_wdata_s[1:0];
end
end
end
// sysref register(s)
assign up_sysref_ack_t_s = up_sysref_ack_t_m3 ^ up_sysref_ack_t_m2;
@ -442,6 +479,8 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
14'h0031: up_rdata <= {30'd0, up_sync_status_1, up_sync_status_0};
14'h0040: up_rdata <= {26'd0, up_sysref_mode_e, 3'b0, up_sysref_mode_i};
14'h0041: up_rdata <= {31'd0, up_sysref_status};
14'h0050: up_rdata <= {24'd0, up_vcal_cnt};
14'h0051: up_rdata <= {30'd0, up_vcal_enable};
default: up_rdata <= 0;
endcase
end else begin

2
projects/fmcadc5/common/fmcadc5_bd.tcl
View File

@ -204,6 +204,7 @@ create_bd_port -dir O spi_clk
create_bd_port -dir O spi_mosi
create_bd_port -dir I spi_miso
create_bd_port -dir O psync
create_bd_port -dir O vcal
ad_connect axi_fmcadc5_sync/rx_sysref_p rx_sysref_p
ad_connect axi_fmcadc5_sync/rx_sysref_n rx_sysref_n
@ -212,6 +213,7 @@ ad_connect axi_fmcadc5_sync/rx_sync_0_n rx_sync_0_n
ad_connect axi_fmcadc5_sync/rx_sync_1_p rx_sync_1_p
ad_connect axi_fmcadc5_sync/rx_sync_1_n rx_sync_1_n
ad_connect axi_fmcadc5_sync/psync psync
ad_connect axi_fmcadc5_sync/vcal vcal
ad_connect axi_fmcadc5_sync/spi_csn spi_csn
ad_connect axi_fmcadc5_sync/spi_clk spi_clk
ad_connect axi_fmcadc5_sync/spi_mosi spi_mosi

6
projects/fmcadc5/vc707/system_top.v
View File

@ -146,6 +146,7 @@ module system_top (
wire rx_ref_clk_0;
wire rx_ref_clk_1;
wire psync;
wire vcal;
// spi & misc
@ -186,7 +187,7 @@ module system_top (
.O (gpio_i[46]));
OBUFDS i_obufds_vdither (
.I (gpio_o[45]),
.I (vcal),
.O (vdither_p),
.OB (vdither_n));
@ -327,7 +328,8 @@ module system_top (
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
.uart_sout (uart_sout),
.vcal (vcal));
endmodule