diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index 6142a0c10..aca494653 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -113,9 +113,8 @@ module axi_ad9361 ( enable, txnrx, - tdd_sync_i, - tdd_sync_o, - tdd_sync_t, + tdd_sync_req, + tdd_sync_ack, // axi interface @@ -233,9 +232,8 @@ module axi_ad9361 ( output enable; output txnrx; - input tdd_sync_i; - output tdd_sync_o; - output tdd_sync_t; + inout tdd_sync_req; + inout tdd_sync_ack; // axi interface @@ -270,7 +268,7 @@ module axi_ad9361 ( // chipscope signals - output [34:0] tdd_dbg; + output [40:0] tdd_dbg; // internal registers @@ -411,9 +409,8 @@ module axi_ad9361 ( .tdd_tx_rf_en(tdd_tx_rf_en_s), .tdd_enable (tdd_enable), .tdd_status(tdd_status_s), - .tdd_sync_i(tdd_sync_i), - .tdd_sync_o(tdd_sync_o), - .tdd_sync_t(tdd_sync_t), + .tdd_sync_req(tdd_sync_req), + .tdd_sync_ack(tdd_sync_ack), .tx_valid_i0(dac_valid_i0_s), .tx_valid_q0(dac_valid_q0_s), .tx_valid_i1(dac_valid_i1_s), diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl index 23ae104c1..607631e9a 100755 --- a/library/axi_ad9361/axi_ad9361_ip.tcl +++ b/library/axi_ad9361/axi_ad9361_ip.tcl @@ -19,6 +19,8 @@ adi_ip_files axi_ad9361 [list \ "$ad_hdl_dir/library/common/ad_iqcor.v" \ "$ad_hdl_dir/library/common/ad_addsub.v" \ "$ad_hdl_dir/library/common/ad_tdd_control.v" \ + "$ad_hdl_dir/library/common/ad_tdd_sync.v" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_xfer_status.v" \ diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v index 7c73504a4..73c52a83b 100644 --- a/library/axi_ad9361/axi_ad9361_tdd.v +++ b/library/axi_ad9361/axi_ad9361_tdd.v @@ -60,9 +60,8 @@ module axi_ad9361_tdd ( // sync signals - tdd_sync_i, - tdd_sync_o, - tdd_sync_t, + tdd_sync_req, + tdd_sync_ack, // tx/rx data flow control @@ -115,9 +114,8 @@ module axi_ad9361_tdd ( output tdd_enable; input [ 7:0] tdd_status; - input tdd_sync_i; - output tdd_sync_o; - output tdd_sync_t; + inout tdd_sync_req; + inout tdd_sync_ack; // tx data flow control @@ -156,7 +154,7 @@ module axi_ad9361_tdd ( output [31:0] up_rdata; output up_rack; - output [34:0] tdd_dbg; + output [41:0] tdd_dbg; reg tdd_enable = 1'b0; reg tdd_slave_synced = 1'b0; @@ -166,6 +164,7 @@ module axi_ad9361_tdd ( wire rst; wire tdd_enable_s; + wire tdd_enable_synced_s; wire tdd_secondary_s; wire [ 7:0] tdd_burst_count_s; wire tdd_rx_only_s; @@ -175,6 +174,7 @@ module axi_ad9361_tdd ( wire [23:0] tdd_counter_init_s; wire [23:0] tdd_frame_length_s; wire tdd_terminal_type_s; + wire tdd_sync_enable_s; wire [23:0] tdd_vco_rx_on_1_s; wire [23:0] tdd_vco_rx_off_1_s; wire [23:0] tdd_vco_tx_on_1_s; @@ -205,64 +205,24 @@ module axi_ad9361_tdd ( // tx/rx data flow control - assign tdd_tx_valid_i0 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ? + assign tdd_tx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ? (tx_valid_i0 & tdd_tx_dp_en_s) : tx_valid_i0; - assign tdd_tx_valid_q0 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ? + assign tdd_tx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ? (tx_valid_q0 & tdd_tx_dp_en_s) : tx_valid_q0; - assign tdd_tx_valid_i1 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ? + assign tdd_tx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ? (tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1; - assign tdd_tx_valid_q1 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ? + assign tdd_tx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ? (tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1; - assign tdd_rx_valid_i0 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ? + assign tdd_rx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ? (rx_valid_i0 & tdd_rx_rf_en) : rx_valid_i0; - assign tdd_rx_valid_q0 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ? + assign tdd_rx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ? (rx_valid_q0 & tdd_rx_rf_en) : rx_valid_q0; - assign tdd_rx_valid_i1 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ? + assign tdd_rx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ? (rx_valid_i1 & tdd_rx_rf_en) : rx_valid_i1; - assign tdd_rx_valid_q1 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ? + assign tdd_rx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ? (rx_valid_q1 & tdd_rx_rf_en) : rx_valid_q1; - // assign tdd_enable = tdd_enable_s; - - assign tdd_sync_t = tdd_terminal_type_s; - - // catch generated sync signal - always @(posedge clk) begin - if (rst == 1'b1) begin - tdd_slave_synced <= 1'b0; - end else begin - if(tdd_sync_i == 1) begin - tdd_slave_synced <= 1'b1; - end else begin - tdd_slave_synced <= tdd_slave_synced & tdd_enable_s; - end - end - end - - // generate sync signal - always @(posedge clk) begin - if (rst == 1'b1) begin - tdd_sync_o <= 1'b0; - end else begin - if(~tdd_enable & tdd_enable_s == 1'b1) begin - tdd_sync_o <= 1'b1; - end else begin - tdd_sync_o <= 1'b0; - end - end - end - - // generate tdd enable in function of the terminal type - always @(posedge clk) begin - if (rst == 1'b1) begin - tdd_enable <= 1'b0; - end else begin - tdd_enable <= (tdd_terminal_type_s == 1'b1) ? tdd_enable_s : - (tdd_enable_s & tdd_slave_synced); - end - end - // instantiations up_tdd_cntrl i_up_tdd_cntrl( @@ -278,6 +238,7 @@ module axi_ad9361_tdd ( .tdd_counter_init(tdd_counter_init_s), .tdd_frame_length(tdd_frame_length_s), .tdd_terminal_type(tdd_terminal_type_s), + .tdd_sync_enable(tdd_sync_enable_s), .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), @@ -313,7 +274,7 @@ module axi_ad9361_tdd ( ad_tdd_control i_tdd_control( .clk(clk), .rst(rst), - .tdd_enable(tdd_enable_s), + .tdd_enable(tdd_enable_synced_s), .tdd_secondary(tdd_secondary_s), .tdd_counter_init(tdd_counter_init_s), .tdd_frame_length(tdd_frame_length_s), @@ -347,4 +308,16 @@ module axi_ad9361_tdd ( .tdd_tx_rf_en(tdd_tx_rf_en), .tdd_counter_status(tdd_counter_status)); + ad_tdd_sync i_tdd_sync ( + .clk(clk), + .rst(rst), + .tdd_sync_en(tdd_sync_enable_s), + .tdd_term_type(tdd_terminal_type_s), + .tdd_enable_in(tdd_enable_s), + .tdd_enable_out(tdd_enable_synced_s), + .sync_req(tdd_sync_req), + .sync_ack(tdd_sync_ack), + .sync_dbg(tdd_sync_dbg) + ); + endmodule diff --git a/library/common/ad_tdd_sync.v b/library/common/ad_tdd_sync.v new file mode 100644 index 000000000..86265a2e9 --- /dev/null +++ b/library/common/ad_tdd_sync.v @@ -0,0 +1,169 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2015(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/1ps + +module ad_tdd_sync ( + + // clock & reset + + clk, + rst, + + // control signals + + tdd_sync_en, // synchronization enabled + tdd_term_type, // master or slave + tdd_enable_in, // tdd_enable signal asserted by software + tdd_enable_out, // synchronized tdd_enable + + // sync interface + + sync_req, // sync request generated by master + sync_ack, // sync acknowledge generated by slave + + // debug + sync_dbg + +); + + input clk; + input rst; + + input tdd_sync_en; + input tdd_term_type; + input tdd_enable_in; + output tdd_enable_out; + + inout sync_req; + inout sync_ack; + + output [5:0] sync_dbg; + + reg tdd_enable_out = 1'b0; + reg tdd_enable_synced = 1'b0; + reg tdd_enable_d = 1'b0; + reg sync_req_i = 1'b0; + reg sync_ack_i = 1'b0; + + reg [2:0] pulse_width = 3'h7; + + wire sync_ack_o_s; + wire sync_req_o_s; + wire sync_req_t_s; + wire sync_ack_t_s; + + // the sync module can be bypassed + + always @(posedge clk) begin + if (rst == 1) begin + tdd_enable_out <= 1'b0; + end else begin + tdd_enable_out <= (tdd_sync_en) ? tdd_enable_synced : tdd_enable_in; + end + end + + // iobuffers for the syncronization lines + + assign sync_req_t_s = ~tdd_term_type; + assign sync_ack_t_s = tdd_term_type; + + assign sync_dbg = {sync_ack_i_s, + sync_ack_o_s, + sync_ack_t_s, + sync_req_i, + sync_req_o_s, + sync_req_t_s}; + + ad_iobuf #( + .DATA_WIDTH(1) + ) i_sync_req_iobuf ( + .dio_t (sync_req_t_s), + .dio_i (sync_req_i), + .dio_o (sync_req_o_s), + .dio_p (sync_req) + ); + + ad_iobuf #( + .DATA_WIDTH(1) + ) i_sync_ack_iobuf ( + .dio_t (sync_ack_i_s), + .dio_i (sync_ack_i), + .dio_o (sync_ack_o_s), + .dio_p (sync_ack) + ); + + always @(posedge clk) begin + if (rst == 1) begin + tdd_enable_d <= 1'b0; + sync_req_i <= 1'b0; + sync_ack_i <= 1'b0; + pulse_width <= 3'h7; + end else begin + + tdd_enable_d <= tdd_enable_in; + // device is master + if (tdd_term_type == 1) begin + + if (~tdd_enable_d & tdd_enable_in == 1'b1) begin // generate sync request + sync_req_i <= 1'b1; + pulse_width <= 1'b0; + end else begin + pulse_width <= (pulse_width < 3'h7) ? pulse_width + 1 : pulse_width; + sync_req_i <= (pulse_width == 3'h7) ? 1'b0 : 1'b1; + end + + if (sync_ack_o_s == 1'b1) begin // sync acknowledge arrived + tdd_enable_synced <= tdd_enable_in; + end else begin + tdd_enable_synced <= (tdd_enable_in == 1'b0) ? 1'b0 : tdd_enable_synced; + end + // device is slave + end else begin + if (sync_req_o_s == 1'b1) begin + tdd_enable_synced <= tdd_enable_in; + sync_ack_i <= 1'b1; + end else begin + tdd_enable_synced <= (tdd_enable_in == 1'b0) ? 1'b0 : tdd_enable_synced; + sync_ack_i <= 1'b0; + end + end + end + end + +endmodule diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v index 555d0483b..342caf79d 100644 --- a/library/common/up_tdd_cntrl.v +++ b/library/common/up_tdd_cntrl.v @@ -55,6 +55,7 @@ module up_tdd_cntrl ( tdd_counter_init, tdd_frame_length, tdd_terminal_type, + tdd_sync_enable, tdd_vco_rx_on_1, tdd_vco_rx_off_1, tdd_vco_tx_on_1, @@ -109,6 +110,7 @@ module up_tdd_cntrl ( output [23:0] tdd_counter_init; output [23:0] tdd_frame_length; output tdd_terminal_type; + output tdd_sync_enable; output [23:0] tdd_vco_rx_on_1; output [23:0] tdd_vco_rx_off_1; output [23:0] tdd_vco_tx_on_1; @@ -159,6 +161,7 @@ module up_tdd_cntrl ( reg up_tdd_gated_tx_dmapath = 1'h0; reg up_tdd_gated_rx_dmapath = 1'h0; reg up_tdd_terminal_type = 1'h0; + reg up_tdd_sync_enable = 1'h0; reg [ 7:0] up_tdd_burst_count = 8'h0; reg [23:0] up_tdd_counter_init = 24'h0; @@ -210,6 +213,7 @@ module up_tdd_cntrl ( up_tdd_gated_tx_dmapath <= 1'h0; up_tdd_gated_rx_dmapath <= 1'h0; up_tdd_terminal_type <= 1'h0; + up_tdd_sync_enable <= 1'h0; up_tdd_counter_init <= 24'h0; up_tdd_frame_length <= 24'h0; up_tdd_burst_count <= 8'h0; @@ -251,7 +255,8 @@ module up_tdd_cntrl ( up_tdd_frame_length <= up_wdata[23:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin - up_tdd_terminal_type <= up_wdata[0]; + up_tdd_terminal_type <= up_wdata[1]; + up_tdd_sync_enable <= up_wdata[0]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin up_tdd_vco_rx_on_1 <= up_wdata[23:0]; @@ -335,7 +340,8 @@ module up_tdd_cntrl ( 8'h11: up_rdata <= {24'h0, up_tdd_burst_count}; 8'h12: up_rdata <= { 8'h0, up_tdd_counter_init}; 8'h13: up_rdata <= { 8'h0, up_tdd_frame_length}; - 8'h14: up_rdata <= {31'h0, up_tdd_terminal_type}; + 8'h14: up_rdata <= {30'h0, up_tdd_terminal_type, + up_tdd_sync_enable}; 8'h18: up_rdata <= {24'h0, up_tdd_status_s}; 8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1}; 8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1}; @@ -375,7 +381,8 @@ module up_tdd_cntrl ( up_tdd_gated_rx_dmapath, up_tdd_gated_tx_dmapath, up_tdd_burst_count, - up_tdd_terminal_type + up_tdd_terminal_type, + up_tdd_sync_enable }), .up_xfer_done(), .d_rst(rst), @@ -387,7 +394,8 @@ module up_tdd_cntrl ( tdd_gated_rx_dmapath, tdd_gated_tx_dmapath, tdd_burst_count, - tdd_terminal_type + tdd_terminal_type, + tdd_sync_enable })); up_xfer_cntrl #(.DATA_WIDTH(528)) i_tdd_counter_values ( diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 0b8836664..03977f205 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -19,9 +19,8 @@ create_bd_port -dir O enable create_bd_port -dir O txnrx create_bd_port -dir O tdd_enable -create_bd_port -dir I tdd_sync_i -create_bd_port -dir O tdd_sync_o -create_bd_port -dir O tdd_sync_t +create_bd_port -dir IO tdd_sync_req +create_bd_port -dir IO tdd_sync_ack # ad9361 core @@ -140,9 +139,8 @@ ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1 ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf -ad_connect tdd_sync_i axi_ad9361/tdd_sync_i -ad_connect tdd_sync_o axi_ad9361/tdd_sync_o -ad_connect tdd_sync_t axi_ad9361/tdd_sync_t +ad_connect tdd_sync_req axi_ad9361/tdd_sync_req +ad_connect tdd_sync_ack axi_ad9361/tdd_sync_ack ad_connect tdd_enable axi_ad9361/tdd_enable diff --git a/projects/fmcomms2/rfsom/system_constr.xdc b/projects/fmcomms2/rfsom/system_constr.xdc index 7546cd04a..9b59442cc 100644 --- a/projects/fmcomms2/rfsom/system_constr.xdc +++ b/projects/fmcomms2/rfsom/system_constr.xdc @@ -36,7 +36,9 @@ set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_o set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35 set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35 set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35 -set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## IO_L24_13_JX2_N +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports tdd_sync_req] ; ## IO_L24_13_JX2_N +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tdd_sync_ack] ; ## IO_L23_13_JX2_N + set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35 set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35 diff --git a/projects/fmcomms2/rfsom/system_top.v b/projects/fmcomms2/rfsom/system_top.v index 27f46e868..b4e877274 100644 --- a/projects/fmcomms2/rfsom/system_top.v +++ b/projects/fmcomms2/rfsom/system_top.v @@ -109,7 +109,8 @@ module system_top ( tx_data_out_n, enable, txnrx, - tdd_sync, + tdd_sync_req, + tdd_sync_ack, gpio_rf0, gpio_rf1, @@ -197,7 +198,8 @@ module system_top ( output [ 5:0] tx_data_out_n; output enable; output txnrx; - inout tdd_sync; + inout tdd_sync_req; + inout tdd_sync_ack; inout gpio_rf0; inout gpio_rf1; @@ -229,10 +231,6 @@ module system_top ( wire enable_s; wire txnrx_s; - wire tdd_sync_t_s; - wire tdd_sync_o_s; - wire tdd_sync_i_s; - // assignments assign hdmi_pd = 1'b0; @@ -265,12 +263,6 @@ module system_top ( .dio_o (gpio_i[11:0]), .dio_p (gpio_bd)); - ad_iobuf #(.DATA_WIDTH(1)) i_tdd_sync ( - .dio_t (tdd_sync_t_s), - .dio_i (tdd_sync_o_s), - .dio_o (tdd_sync_i_s), - .dio_p (tdd_sync)); - system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), @@ -372,9 +364,8 @@ module system_top ( .tx_frame_out_p (tx_frame_out_p), .txnrx (txnrx_s), .tdd_enable (tdd_enable_s), - .tdd_sync_i (tdd_sync_i_s), - .tdd_sync_o (tdd_sync_o_s), - .tdd_sync_t (tdd_sync_t_s)); + .tdd_sync_req (tdd_sync_req), + .tdd_sync_ack (tdd_sync_ack)); endmodule diff --git a/projects/fmcomms2/zc706/system_constr.xdc b/projects/fmcomms2/zc706/system_constr.xdc index b272eba01..b7bf5f3b2 100644 --- a/projects/fmcomms2/zc706/system_constr.xdc +++ b/projects/fmcomms2/zc706/system_constr.xdc @@ -36,7 +36,8 @@ set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_o set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N -set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## PMOD1_7_LS +set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports tdd_sync_req] ; ## PMOD1_7_LS +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports tdd_sync_ack] ; ## PMOD1_5_LS set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N diff --git a/projects/fmcomms2/zc706/system_top.v b/projects/fmcomms2/zc706/system_top.v index 142f918d7..f0c926355 100644 --- a/projects/fmcomms2/zc706/system_top.v +++ b/projects/fmcomms2/zc706/system_top.v @@ -92,7 +92,8 @@ module system_top ( enable, txnrx, - tdd_sync, + tdd_sync_req, + tdd_sync_ack, gpio_muxout_tx, gpio_muxout_rx, @@ -163,7 +164,8 @@ module system_top ( output enable; output txnrx; - inout tdd_sync; + inout tdd_sync_req; + inout tdd_sync_ack; inout gpio_muxout_tx; inout gpio_muxout_rx; @@ -215,9 +217,6 @@ module system_top ( wire gpio_txnrx; wire enable_s; wire txnrx_s; - wire tdd_sync_t_s; - wire tdd_sync_o_s; - wire tdd_sync_i_s; assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable; assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx; @@ -244,12 +243,6 @@ module system_top ( .dio_o (gpio_i[14:0]), .dio_p (gpio_bd)); - ad_iobuf #(.DATA_WIDTH(1)) i_tdd_sync ( - .dio_t (tdd_sync_t_s), - .dio_i (tdd_sync_o_s), - .dio_o (tdd_sync_i_s), - .dio_p (tdd_sync)); - system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), @@ -328,9 +321,8 @@ module system_top ( .tx_frame_out_p (tx_frame_out_p), .txnrx (txnrx_s), .tdd_enable (tdd_enable_s), - .tdd_sync_i (tdd_sync_i_s), - .tdd_sync_o (tdd_sync_o_s), - .tdd_sync_t (tdd_sync_t_s)); + .tdd_sync_req(tdd_sync_req), + .tdd_sync_ack(tdd_sync_ack)); endmodule