fmcomms2/TDD: Update synchronization interface
Synchronization is done by a simple req/ack interface between a master and slave terminal.main
Istvan Csomortani
parent
8e631e56d6
commit
d2c99acae8
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@ -113,9 +113,8 @@ module axi_ad9361 (
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enable,
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txnrx,
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tdd_sync_i,
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tdd_sync_o,
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tdd_sync_t,
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tdd_sync_req,
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tdd_sync_ack,
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// axi interface
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@ -233,9 +232,8 @@ module axi_ad9361 (
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output enable;
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output txnrx;
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input tdd_sync_i;
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output tdd_sync_o;
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output tdd_sync_t;
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inout tdd_sync_req;
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inout tdd_sync_ack;
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// axi interface
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@ -270,7 +268,7 @@ module axi_ad9361 (
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// chipscope signals
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output [34:0] tdd_dbg;
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output [40:0] tdd_dbg;
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// internal registers
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@ -411,9 +409,8 @@ module axi_ad9361 (
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.tdd_tx_rf_en(tdd_tx_rf_en_s),
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.tdd_enable (tdd_enable),
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.tdd_status(tdd_status_s),
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.tdd_sync_i(tdd_sync_i),
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.tdd_sync_o(tdd_sync_o),
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.tdd_sync_t(tdd_sync_t),
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.tdd_sync_req(tdd_sync_req),
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.tdd_sync_ack(tdd_sync_ack),
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.tx_valid_i0(dac_valid_i0_s),
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.tx_valid_q0(dac_valid_q0_s),
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.tx_valid_i1(dac_valid_i1_s),
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@ -19,6 +19,8 @@ adi_ip_files axi_ad9361 [list \
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"$ad_hdl_dir/library/common/ad_iqcor.v" \
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"$ad_hdl_dir/library/common/ad_addsub.v" \
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"$ad_hdl_dir/library/common/ad_tdd_control.v" \
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"$ad_hdl_dir/library/common/ad_tdd_sync.v" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_status.v" \
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@ -60,9 +60,8 @@ module axi_ad9361_tdd (
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// sync signals
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tdd_sync_i,
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tdd_sync_o,
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tdd_sync_t,
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tdd_sync_req,
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tdd_sync_ack,
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// tx/rx data flow control
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@ -115,9 +114,8 @@ module axi_ad9361_tdd (
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output tdd_enable;
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input [ 7:0] tdd_status;
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input tdd_sync_i;
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output tdd_sync_o;
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output tdd_sync_t;
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inout tdd_sync_req;
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inout tdd_sync_ack;
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// tx data flow control
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@ -156,7 +154,7 @@ module axi_ad9361_tdd (
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output [31:0] up_rdata;
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output up_rack;
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output [34:0] tdd_dbg;
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output [41:0] tdd_dbg;
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reg tdd_enable = 1'b0;
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reg tdd_slave_synced = 1'b0;
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@ -166,6 +164,7 @@ module axi_ad9361_tdd (
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wire rst;
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wire tdd_enable_s;
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wire tdd_enable_synced_s;
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wire tdd_secondary_s;
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wire [ 7:0] tdd_burst_count_s;
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wire tdd_rx_only_s;
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@ -175,6 +174,7 @@ module axi_ad9361_tdd (
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wire [23:0] tdd_counter_init_s;
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wire [23:0] tdd_frame_length_s;
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wire tdd_terminal_type_s;
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wire tdd_sync_enable_s;
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wire [23:0] tdd_vco_rx_on_1_s;
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wire [23:0] tdd_vco_rx_off_1_s;
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wire [23:0] tdd_vco_tx_on_1_s;
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@ -205,64 +205,24 @@ module axi_ad9361_tdd (
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// tx/rx data flow control
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assign tdd_tx_valid_i0 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
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assign tdd_tx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
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(tx_valid_i0 & tdd_tx_dp_en_s) : tx_valid_i0;
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assign tdd_tx_valid_q0 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
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assign tdd_tx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
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(tx_valid_q0 & tdd_tx_dp_en_s) : tx_valid_q0;
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assign tdd_tx_valid_i1 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
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assign tdd_tx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
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(tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1;
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assign tdd_tx_valid_q1 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
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assign tdd_tx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
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(tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1;
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assign tdd_rx_valid_i0 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
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assign tdd_rx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
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(rx_valid_i0 & tdd_rx_rf_en) : rx_valid_i0;
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assign tdd_rx_valid_q0 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
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assign tdd_rx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
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(rx_valid_q0 & tdd_rx_rf_en) : rx_valid_q0;
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assign tdd_rx_valid_i1 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
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assign tdd_rx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
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(rx_valid_i1 & tdd_rx_rf_en) : rx_valid_i1;
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assign tdd_rx_valid_q1 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
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assign tdd_rx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
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(rx_valid_q1 & tdd_rx_rf_en) : rx_valid_q1;
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// assign tdd_enable = tdd_enable_s;
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assign tdd_sync_t = tdd_terminal_type_s;
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// catch generated sync signal
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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tdd_slave_synced <= 1'b0;
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end else begin
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if(tdd_sync_i == 1) begin
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tdd_slave_synced <= 1'b1;
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end else begin
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tdd_slave_synced <= tdd_slave_synced & tdd_enable_s;
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end
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end
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end
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// generate sync signal
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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tdd_sync_o <= 1'b0;
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end else begin
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if(~tdd_enable & tdd_enable_s == 1'b1) begin
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tdd_sync_o <= 1'b1;
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end else begin
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tdd_sync_o <= 1'b0;
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end
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end
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end
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// generate tdd enable in function of the terminal type
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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tdd_enable <= 1'b0;
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end else begin
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tdd_enable <= (tdd_terminal_type_s == 1'b1) ? tdd_enable_s :
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(tdd_enable_s & tdd_slave_synced);
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end
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end
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// instantiations
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up_tdd_cntrl i_up_tdd_cntrl(
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@ -278,6 +238,7 @@ module axi_ad9361_tdd (
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_terminal_type(tdd_terminal_type_s),
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.tdd_sync_enable(tdd_sync_enable_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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@ -313,7 +274,7 @@ module axi_ad9361_tdd (
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ad_tdd_control i_tdd_control(
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.clk(clk),
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.rst(rst),
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.tdd_enable(tdd_enable_s),
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.tdd_enable(tdd_enable_synced_s),
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.tdd_secondary(tdd_secondary_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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@ -347,4 +308,16 @@ module axi_ad9361_tdd (
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.tdd_tx_rf_en(tdd_tx_rf_en),
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.tdd_counter_status(tdd_counter_status));
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ad_tdd_sync i_tdd_sync (
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.clk(clk),
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.rst(rst),
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.tdd_sync_en(tdd_sync_enable_s),
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.tdd_term_type(tdd_terminal_type_s),
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.tdd_enable_in(tdd_enable_s),
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.tdd_enable_out(tdd_enable_synced_s),
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.sync_req(tdd_sync_req),
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.sync_ack(tdd_sync_ack),
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.sync_dbg(tdd_sync_dbg)
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);
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endmodule
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@ -0,0 +1,169 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module ad_tdd_sync (
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// clock & reset
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clk,
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rst,
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// control signals
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tdd_sync_en, // synchronization enabled
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tdd_term_type, // master or slave
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tdd_enable_in, // tdd_enable signal asserted by software
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tdd_enable_out, // synchronized tdd_enable
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// sync interface
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sync_req, // sync request generated by master
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sync_ack, // sync acknowledge generated by slave
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// debug
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sync_dbg
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);
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input clk;
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input rst;
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input tdd_sync_en;
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input tdd_term_type;
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input tdd_enable_in;
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output tdd_enable_out;
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inout sync_req;
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inout sync_ack;
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output [5:0] sync_dbg;
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reg tdd_enable_out = 1'b0;
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reg tdd_enable_synced = 1'b0;
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reg tdd_enable_d = 1'b0;
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reg sync_req_i = 1'b0;
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reg sync_ack_i = 1'b0;
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reg [2:0] pulse_width = 3'h7;
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wire sync_ack_o_s;
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wire sync_req_o_s;
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wire sync_req_t_s;
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wire sync_ack_t_s;
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// the sync module can be bypassed
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always @(posedge clk) begin
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if (rst == 1) begin
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tdd_enable_out <= 1'b0;
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end else begin
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tdd_enable_out <= (tdd_sync_en) ? tdd_enable_synced : tdd_enable_in;
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end
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end
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// iobuffers for the syncronization lines
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assign sync_req_t_s = ~tdd_term_type;
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assign sync_ack_t_s = tdd_term_type;
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assign sync_dbg = {sync_ack_i_s,
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sync_ack_o_s,
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sync_ack_t_s,
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sync_req_i,
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sync_req_o_s,
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sync_req_t_s};
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ad_iobuf #(
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.DATA_WIDTH(1)
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) i_sync_req_iobuf (
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.dio_t (sync_req_t_s),
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.dio_i (sync_req_i),
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.dio_o (sync_req_o_s),
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.dio_p (sync_req)
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);
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ad_iobuf #(
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.DATA_WIDTH(1)
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) i_sync_ack_iobuf (
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.dio_t (sync_ack_i_s),
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.dio_i (sync_ack_i),
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.dio_o (sync_ack_o_s),
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.dio_p (sync_ack)
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);
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always @(posedge clk) begin
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if (rst == 1) begin
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tdd_enable_d <= 1'b0;
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sync_req_i <= 1'b0;
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sync_ack_i <= 1'b0;
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pulse_width <= 3'h7;
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end else begin
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tdd_enable_d <= tdd_enable_in;
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// device is master
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if (tdd_term_type == 1) begin
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if (~tdd_enable_d & tdd_enable_in == 1'b1) begin // generate sync request
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sync_req_i <= 1'b1;
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pulse_width <= 1'b0;
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end else begin
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pulse_width <= (pulse_width < 3'h7) ? pulse_width + 1 : pulse_width;
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sync_req_i <= (pulse_width == 3'h7) ? 1'b0 : 1'b1;
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end
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if (sync_ack_o_s == 1'b1) begin // sync acknowledge arrived
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tdd_enable_synced <= tdd_enable_in;
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end else begin
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tdd_enable_synced <= (tdd_enable_in == 1'b0) ? 1'b0 : tdd_enable_synced;
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end
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// device is slave
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end else begin
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if (sync_req_o_s == 1'b1) begin
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tdd_enable_synced <= tdd_enable_in;
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sync_ack_i <= 1'b1;
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end else begin
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tdd_enable_synced <= (tdd_enable_in == 1'b0) ? 1'b0 : tdd_enable_synced;
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sync_ack_i <= 1'b0;
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end
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end
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end
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end
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endmodule
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@ -55,6 +55,7 @@ module up_tdd_cntrl (
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tdd_counter_init,
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tdd_frame_length,
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tdd_terminal_type,
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tdd_sync_enable,
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tdd_vco_rx_on_1,
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tdd_vco_rx_off_1,
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tdd_vco_tx_on_1,
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@ -109,6 +110,7 @@ module up_tdd_cntrl (
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output [23:0] tdd_counter_init;
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output [23:0] tdd_frame_length;
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output tdd_terminal_type;
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output tdd_sync_enable;
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output [23:0] tdd_vco_rx_on_1;
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output [23:0] tdd_vco_rx_off_1;
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output [23:0] tdd_vco_tx_on_1;
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@ -159,6 +161,7 @@ module up_tdd_cntrl (
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reg up_tdd_gated_tx_dmapath = 1'h0;
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reg up_tdd_gated_rx_dmapath = 1'h0;
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reg up_tdd_terminal_type = 1'h0;
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reg up_tdd_sync_enable = 1'h0;
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reg [ 7:0] up_tdd_burst_count = 8'h0;
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reg [23:0] up_tdd_counter_init = 24'h0;
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@ -210,6 +213,7 @@ module up_tdd_cntrl (
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up_tdd_gated_tx_dmapath <= 1'h0;
|
||||
up_tdd_gated_rx_dmapath <= 1'h0;
|
||||
up_tdd_terminal_type <= 1'h0;
|
||||
up_tdd_sync_enable <= 1'h0;
|
||||
up_tdd_counter_init <= 24'h0;
|
||||
up_tdd_frame_length <= 24'h0;
|
||||
up_tdd_burst_count <= 8'h0;
|
||||
|
|
@ -251,7 +255,8 @@ module up_tdd_cntrl (
|
|||
up_tdd_frame_length <= up_wdata[23:0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
|
||||
up_tdd_terminal_type <= up_wdata[0];
|
||||
up_tdd_terminal_type <= up_wdata[1];
|
||||
up_tdd_sync_enable <= up_wdata[0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
|
||||
up_tdd_vco_rx_on_1 <= up_wdata[23:0];
|
||||
|
|
@ -335,7 +340,8 @@ module up_tdd_cntrl (
|
|||
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
|
||||
8'h12: up_rdata <= { 8'h0, up_tdd_counter_init};
|
||||
8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
|
||||
8'h14: up_rdata <= {31'h0, up_tdd_terminal_type};
|
||||
8'h14: up_rdata <= {30'h0, up_tdd_terminal_type,
|
||||
up_tdd_sync_enable};
|
||||
8'h18: up_rdata <= {24'h0, up_tdd_status_s};
|
||||
8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
|
||||
8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
|
||||
|
|
@ -375,7 +381,8 @@ module up_tdd_cntrl (
|
|||
up_tdd_gated_rx_dmapath,
|
||||
up_tdd_gated_tx_dmapath,
|
||||
up_tdd_burst_count,
|
||||
up_tdd_terminal_type
|
||||
up_tdd_terminal_type,
|
||||
up_tdd_sync_enable
|
||||
}),
|
||||
.up_xfer_done(),
|
||||
.d_rst(rst),
|
||||
|
|
@ -387,7 +394,8 @@ module up_tdd_cntrl (
|
|||
tdd_gated_rx_dmapath,
|
||||
tdd_gated_tx_dmapath,
|
||||
tdd_burst_count,
|
||||
tdd_terminal_type
|
||||
tdd_terminal_type,
|
||||
tdd_sync_enable
|
||||
}));
|
||||
|
||||
up_xfer_cntrl #(.DATA_WIDTH(528)) i_tdd_counter_values (
|
||||
|
|
|
|||
|
|
@ -19,9 +19,8 @@ create_bd_port -dir O enable
|
|||
create_bd_port -dir O txnrx
|
||||
create_bd_port -dir O tdd_enable
|
||||
|
||||
create_bd_port -dir I tdd_sync_i
|
||||
create_bd_port -dir O tdd_sync_o
|
||||
create_bd_port -dir O tdd_sync_t
|
||||
create_bd_port -dir IO tdd_sync_req
|
||||
create_bd_port -dir IO tdd_sync_ack
|
||||
|
||||
# ad9361 core
|
||||
|
||||
|
|
@ -140,9 +139,8 @@ ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
|
|||
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
|
||||
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
|
||||
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
|
||||
ad_connect tdd_sync_i axi_ad9361/tdd_sync_i
|
||||
ad_connect tdd_sync_o axi_ad9361/tdd_sync_o
|
||||
ad_connect tdd_sync_t axi_ad9361/tdd_sync_t
|
||||
ad_connect tdd_sync_req axi_ad9361/tdd_sync_req
|
||||
ad_connect tdd_sync_ack axi_ad9361/tdd_sync_ack
|
||||
|
||||
ad_connect tdd_enable axi_ad9361/tdd_enable
|
||||
|
||||
|
|
|
|||
|
|
@ -36,7 +36,9 @@ set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_o
|
|||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35
|
||||
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35
|
||||
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35
|
||||
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## IO_L24_13_JX2_N
|
||||
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports tdd_sync_req] ; ## IO_L24_13_JX2_N
|
||||
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tdd_sync_ack] ; ## IO_L23_13_JX2_N
|
||||
|
||||
|
||||
set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35
|
||||
set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35
|
||||
|
|
|
|||
|
|
@ -109,7 +109,8 @@ module system_top (
|
|||
tx_data_out_n,
|
||||
enable,
|
||||
txnrx,
|
||||
tdd_sync,
|
||||
tdd_sync_req,
|
||||
tdd_sync_ack,
|
||||
|
||||
gpio_rf0,
|
||||
gpio_rf1,
|
||||
|
|
@ -197,7 +198,8 @@ module system_top (
|
|||
output [ 5:0] tx_data_out_n;
|
||||
output enable;
|
||||
output txnrx;
|
||||
inout tdd_sync;
|
||||
inout tdd_sync_req;
|
||||
inout tdd_sync_ack;
|
||||
|
||||
inout gpio_rf0;
|
||||
inout gpio_rf1;
|
||||
|
|
@ -229,10 +231,6 @@ module system_top (
|
|||
wire enable_s;
|
||||
wire txnrx_s;
|
||||
|
||||
wire tdd_sync_t_s;
|
||||
wire tdd_sync_o_s;
|
||||
wire tdd_sync_i_s;
|
||||
|
||||
// assignments
|
||||
|
||||
assign hdmi_pd = 1'b0;
|
||||
|
|
@ -265,12 +263,6 @@ module system_top (
|
|||
.dio_o (gpio_i[11:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(1)) i_tdd_sync (
|
||||
.dio_t (tdd_sync_t_s),
|
||||
.dio_i (tdd_sync_o_s),
|
||||
.dio_o (tdd_sync_i_s),
|
||||
.dio_p (tdd_sync));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
|
|
@ -372,9 +364,8 @@ module system_top (
|
|||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.txnrx (txnrx_s),
|
||||
.tdd_enable (tdd_enable_s),
|
||||
.tdd_sync_i (tdd_sync_i_s),
|
||||
.tdd_sync_o (tdd_sync_o_s),
|
||||
.tdd_sync_t (tdd_sync_t_s));
|
||||
.tdd_sync_req (tdd_sync_req),
|
||||
.tdd_sync_ack (tdd_sync_ack));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -36,7 +36,8 @@ set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_o
|
|||
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N
|
||||
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
|
||||
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## PMOD1_7_LS
|
||||
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports tdd_sync_req] ; ## PMOD1_7_LS
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports tdd_sync_ack] ; ## PMOD1_5_LS
|
||||
|
||||
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P
|
||||
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N
|
||||
|
|
|
|||
|
|
@ -92,7 +92,8 @@ module system_top (
|
|||
|
||||
enable,
|
||||
txnrx,
|
||||
tdd_sync,
|
||||
tdd_sync_req,
|
||||
tdd_sync_ack,
|
||||
|
||||
gpio_muxout_tx,
|
||||
gpio_muxout_rx,
|
||||
|
|
@ -163,7 +164,8 @@ module system_top (
|
|||
|
||||
output enable;
|
||||
output txnrx;
|
||||
inout tdd_sync;
|
||||
inout tdd_sync_req;
|
||||
inout tdd_sync_ack;
|
||||
|
||||
inout gpio_muxout_tx;
|
||||
inout gpio_muxout_rx;
|
||||
|
|
@ -215,9 +217,6 @@ module system_top (
|
|||
wire gpio_txnrx;
|
||||
wire enable_s;
|
||||
wire txnrx_s;
|
||||
wire tdd_sync_t_s;
|
||||
wire tdd_sync_o_s;
|
||||
wire tdd_sync_i_s;
|
||||
|
||||
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
|
||||
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
|
||||
|
|
@ -244,12 +243,6 @@ module system_top (
|
|||
.dio_o (gpio_i[14:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(1)) i_tdd_sync (
|
||||
.dio_t (tdd_sync_t_s),
|
||||
.dio_i (tdd_sync_o_s),
|
||||
.dio_o (tdd_sync_i_s),
|
||||
.dio_p (tdd_sync));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
|
|
@ -328,9 +321,8 @@ module system_top (
|
|||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.txnrx (txnrx_s),
|
||||
.tdd_enable (tdd_enable_s),
|
||||
.tdd_sync_i (tdd_sync_i_s),
|
||||
.tdd_sync_o (tdd_sync_o_s),
|
||||
.tdd_sync_t (tdd_sync_t_s));
|
||||
.tdd_sync_req(tdd_sync_req),
|
||||
.tdd_sync_ack(tdd_sync_ack));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue