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ad9783_ebz: Match project name with folder name

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Stanca Pop 2022-09-23 13:44:54 +03:00 committed by StancaPop
parent 3e297f54dd
commit d2d32458f4
3 changed files with 5 additions and 5 deletions
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2
projects/ad9783_ebz/zcu102/Makefile
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@ -4,7 +4,7 @@
## Auto-generated, do not modify! ## Auto-generated, do not modify!
#################################################################################### ####################################################################################
PROJECT_NAME := ad9783_zcu102 PROJECT_NAME := ad9783_ebz_zcu102
M_DEPS += ../common/ad9783_ebz_bd.tcl M_DEPS += ../common/ad9783_ebz_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../scripts/adi_pd.tcl

6
projects/ad9783_ebz/zcu102/system_project.tcl
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@ -3,10 +3,10 @@ source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9783_zcu102 adi_project ad9783_ebz_zcu102
adi_project_files ad9783_zcu102 [list \ adi_project_files ad9783_ebz_zcu102 [list \
"system_top.v" \ "system_top.v" \
"system_constr.xdc"\ "system_constr.xdc"\
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run ad9783_zcu102 adi_project_run ad9783_ebz_zcu102

2
projects/ad9783_ebz/zcu102/system_top.v
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@ -1,6 +1,6 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. // Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved.
// //
// In this HDL repository, there are many different and unique modules, consisting // In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are // of various HDL (Verilog or VHDL) components. The individual modules are