zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

SPI Engine: Formatting on spi_engine_offload 

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
main
Laez Barbosa 2024-01-17 07:55:13 -03:00 committed by LBFFilho
parent d45be68ac4
commit d300b9c55c
1 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
library/spi_engine/spi_engine_offload/spi_engine_offload.v
View File

@ -129,7 +129,7 @@ module spi_engine_offload #(
wire [ 7:0] spi_sync_id_init_s; wire [ 7:0] spi_sync_id_init_s;
always @(posedge ctrl_clk) begin always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1) begin if (ctrl_mem_reset) begin
ctrl_sync_id_init <= 8'b0; ctrl_sync_id_init <= 8'b0;
ctrl_sync_id_load <= 1'b0; ctrl_sync_id_load <= 1'b0;
end else begin end else begin
@ -163,7 +163,7 @@ module spi_engine_offload #(
.out_bits(spi_sync_id_init_s)); .out_bits(spi_sync_id_init_s));
always @(posedge spi_clk) begin always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin if (!spi_resetn) begin
spi_sync_id_counter <= 8'b0; spi_sync_id_counter <= 8'b0;
end else begin end else begin
if (spi_sync_id_load_s) begin if (spi_sync_id_load_s) begin
@ -201,9 +201,9 @@ module spi_engine_offload #(
reg spi_enabled = 1'b0; reg spi_enabled = 1'b0;
always @(posedge ctrl_clk) begin always @(posedge ctrl_clk) begin
if (ctrl_enable == 1'b1) begin if (ctrl_enable) begin
ctrl_do_enable <= 1'b1; ctrl_do_enable <= 1'b1;
end else if (ctrl_is_enabled == 1'b1) begin end else if (ctrl_is_enabled) begin
ctrl_do_enable <= 1'b0; ctrl_do_enable <= 1'b0;
end end
end end
@ -260,57 +260,57 @@ module spi_engine_offload #(
assign trigger_posedge = trigger_s && !trigger_last_reg; assign trigger_posedge = trigger_s && !trigger_last_reg;
always @(posedge spi_clk) begin always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin if (!spi_resetn) begin
spi_active <= 1'b0; spi_active <= 1'b0;
end else begin end else begin
if (spi_active == 1'b0) begin if (!spi_active) begin
// start offload when we have a valid trigger, offload is enabled and // start offload when we have a valid trigger, offload is enabled and
// the DMA is enabled // the DMA is enabled
if (trigger_posedge == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1) if (trigger_posedge && spi_enable && offload_sdi_ready)
spi_active <= 1'b1; spi_active <= 1'b1;
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin end else if (cmd_ready && (spi_cmd_rd_addr_next == ctrl_cmd_wr_addr)) begin
spi_active <= 1'b0; spi_active <= 1'b0;
end end
end end
end end
always @(posedge spi_clk) begin always @(posedge spi_clk) begin
if (cmd_valid == 1'b0) begin if (!cmd_valid) begin
spi_cmd_rd_addr <= 'h00; spi_cmd_rd_addr <= 'h00;
end else if (cmd_ready == 1'b1) begin end else if (cmd_ready) begin
spi_cmd_rd_addr <= spi_cmd_rd_addr_next; spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
end end
end end
always @(posedge spi_clk) begin always @(posedge spi_clk) begin
if (spi_active == 1'b0) begin if (!spi_active) begin
spi_sdo_rd_addr <= 'h00; spi_sdo_rd_addr <= 'h00;
end else if (sdo_data_ready == 1'b1) begin end else if (sdo_data_ready) begin
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1; spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
end end
end end
always @(posedge ctrl_clk) begin always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1) if (ctrl_mem_reset)
ctrl_cmd_wr_addr <= 'h00; ctrl_cmd_wr_addr <= 'h00;
else if (ctrl_cmd_wr_en == 1'b1) else if (ctrl_cmd_wr_en)
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1; ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
end end
always @(posedge ctrl_clk) begin always @(posedge ctrl_clk) begin
if (ctrl_cmd_wr_en == 1'b1) if (ctrl_cmd_wr_en)
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data; cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
end end
always @(posedge ctrl_clk) begin always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1) if (ctrl_mem_reset)
ctrl_sdo_wr_addr <= 'h00; ctrl_sdo_wr_addr <= 'h00;
else if (ctrl_sdo_wr_en == 1'b1) else if (ctrl_sdo_wr_en)
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1; ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
end end
always @(posedge ctrl_clk) begin always @(posedge ctrl_clk) begin
if (ctrl_sdo_wr_en == 1'b1) if (ctrl_sdo_wr_en)
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data; sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
end end