diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v index 57178e070..54571d34a 100644 --- a/library/common/up_adc_common.v +++ b/library/common/up_adc_common.v @@ -51,7 +51,7 @@ module up_adc_common #( // clock reset - output mmcm_rst, + output mmcm_rst, // adc interface @@ -66,11 +66,12 @@ module up_adc_common #( input adc_status_unf, input [31:0] adc_clk_ratio, output [31:0] adc_start_code, + output adc_sref_sync, output adc_sync, - output reg up_adc_ce, // channel interface + output up_adc_ce, input up_status_pn_err, input up_status_pn_oos, input up_status_or, @@ -87,8 +88,8 @@ module up_adc_common #( // user channel control - output [ 7:0] up_usr_chanmax, - input [ 7:0] adc_usr_chanmax, + output [ 7:0] up_usr_chanmax_out, + input [ 7:0] up_usr_chanmax_in, input [31:0] up_adc_gpio_in, output [31:0] up_adc_gpio_out, @@ -111,77 +112,80 @@ module up_adc_common #( // internal registers - reg up_core_preset = 'd1; - reg up_mmcm_preset = 'd1; - reg up_wack_int = 'd0; - reg [31:0] up_scratch = 'd0; - reg up_adc_ce_int = 'd0; - reg up_mmcm_resetn = 'd0; - reg up_resetn = 'd0; - reg up_adc_sync = 'd0; - reg up_adc_r1_mode = 'd0; - reg up_adc_ddr_edgesel = 'd0; - reg up_adc_pin_mode = 'd0; - reg up_drp_sel_int = 'd0; - reg up_drp_wr_int = 'd0; - reg up_drp_status = 'd0; - reg up_drp_rwn = 'd0; - reg [11:0] up_drp_addr_int = 'd0; - reg [31:0] up_drp_wdata_int = 'd0; - reg [31:0] up_drp_rdata_hold = 'd0; - reg up_status_ovf = 'd0; - reg up_status_unf = 'd0; - reg [ 7:0] up_usr_chanmax_int = 'd0; - reg [31:0] up_adc_start_code = 'd0; - reg [31:0] up_adc_gpio_out_int = 'd0; - reg up_rack_int = 'd0; - reg [31:0] up_rdata_int = 'd0; + reg up_adc_clk_enb_int = 'd1; + reg up_core_preset = 'd1; + reg up_mmcm_preset = 'd1; + reg up_wack_int = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_adc_clk_enb = 'd0; + reg up_mmcm_resetn = 'd0; + reg up_resetn = 'd0; + reg up_adc_sync = 'd0; + reg up_adc_sref_sync = 'd0; + reg up_adc_r1_mode = 'd0; + reg up_adc_ddr_edgesel = 'd0; + reg up_adc_pin_mode = 'd0; + reg up_drp_sel_int = 'd0; + reg up_drp_wr_int = 'd0; + reg up_drp_status = 'd0; + reg up_drp_rwn = 'd0; + reg [11:0] up_drp_addr_int = 'd0; + reg [31:0] up_drp_wdata_int = 'd0; + reg [31:0] up_drp_rdata_hold = 'd0; + reg up_status_ovf = 'd0; + reg up_status_unf = 'd0; + reg [ 7:0] up_usr_chanmax_int = 'd0; + reg [31:0] up_adc_start_code = 'd0; + reg [31:0] up_adc_gpio_out_int = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; // internal signals - wire up_wreq_s; - wire up_rreq_s; - wire up_status_s; - wire up_sync_status_s; - wire up_status_ovf_s; - wire up_status_unf_s; - wire up_cntrl_xfer_done_s; - wire [31:0] up_adc_clk_count_s; + wire up_wreq_s; + wire up_rreq_s; + wire up_status_s; + wire up_sync_status_s; + wire up_status_ovf_s; + wire up_status_unf_s; + wire up_cntrl_xfer_done_s; + wire [31:0] up_adc_clk_count_s; // decode block select assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0; assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0; - // processor write interface assign up_wack = up_wack_int; + assign up_adc_ce = up_adc_clk_enb_int; always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_adc_ce <= 1'd1; + up_adc_clk_enb_int <= 1'd1; up_core_preset <= 1'd1; up_mmcm_preset <= 1'd1; up_wack_int <= 'd0; up_scratch <= 'd0; - up_adc_ce_int <= 'd0; + up_adc_clk_enb <= 'd0; up_mmcm_resetn <= 'd0; up_resetn <= 'd0; up_adc_sync <= 'd0; + up_adc_sref_sync <= 'd0; up_adc_r1_mode <= 'd0; up_adc_ddr_edgesel <= 'd0; up_adc_pin_mode <= 'd0; end else begin + up_adc_clk_enb_int <= ~up_adc_clk_enb; up_core_preset <= ~up_resetn; up_mmcm_preset <= ~up_mmcm_resetn; - up_adc_ce <= ~up_adc_ce_int; up_wack_int <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin up_scratch <= up_wdata; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin - up_adc_ce_int <= up_wdata[2]; + up_adc_clk_enb <= up_wdata[2]; up_mmcm_resetn <= up_wdata[1]; up_resetn <= up_wdata[0]; end @@ -193,6 +197,7 @@ module up_adc_common #( up_adc_sync <= up_wdata[3]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin + up_adc_sref_sync <= up_wdata[4]; up_adc_r1_mode <= up_wdata[2]; up_adc_ddr_edgesel <= up_wdata[1]; up_adc_pin_mode <= up_wdata[0]; @@ -272,7 +277,7 @@ module up_adc_common #( end end - assign up_usr_chanmax = up_usr_chanmax_int; + assign up_usr_chanmax_out = up_usr_chanmax_int; generate if (USERPORTS_DISABLE == 1) begin @@ -347,8 +352,9 @@ module up_adc_common #( 8'h01: up_rdata_int <= ID; 8'h02: up_rdata_int <= up_scratch; 8'h03: up_rdata_int <= CONFIG; - 8'h10: up_rdata_int <= {29'd0, up_adc_ce_int, up_mmcm_resetn, up_resetn}; - 8'h11: up_rdata_int <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; + 8'h10: up_rdata_int <= {29'd0, up_adc_clk_enb, up_mmcm_resetn, up_resetn}; + 8'h11: up_rdata_int <= {27'd0, up_adc_sref_sync, up_adc_sync, up_adc_r1_mode, + up_adc_ddr_edgesel, up_adc_pin_mode}; 8'h15: up_rdata_int <= up_adc_clk_count_s; 8'h16: up_rdata_int <= adc_clk_ratio; 8'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s}; @@ -359,7 +365,7 @@ module up_adc_common #( 8'h1f: up_rdata_int <= up_drp_rdata_hold; 8'h22: up_rdata_int <= {29'd0, up_status_ovf, up_status_unf, 1'b0}; 8'h23: up_rdata_int <= 32'd8; - 8'h28: up_rdata_int <= {24'd0, adc_usr_chanmax}; + 8'h28: up_rdata_int <= {24'd0, up_usr_chanmax_in}; 8'h29: up_rdata_int <= up_adc_start_code; 8'h2e: up_rdata_int <= up_adc_gpio_in; 8'h2f: up_rdata_int <= up_adc_gpio_out_int; @@ -378,10 +384,11 @@ module up_adc_common #( // adc control & status - up_xfer_cntrl #(.DATA_WIDTH(36)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(37)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), - .up_data_cntrl ({ up_adc_sync, + .up_data_cntrl ({ up_adc_sref_sync, + up_adc_sync, up_adc_start_code, up_adc_r1_mode, up_adc_ddr_edgesel, @@ -389,7 +396,8 @@ module up_adc_common #( .up_xfer_done (up_cntrl_xfer_done_s), .d_rst (adc_rst), .d_clk (adc_clk), - .d_data_cntrl ({ adc_sync, + .d_data_cntrl ({ adc_sref_sync, + adc_sync, adc_start_code, adc_r1_mode, adc_ddr_edgesel,