library/up_adc_common- add sref sync option
Rejeesh Kutty
parent
61bbfb2c82
commit
d374f5b091
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@ -51,7 +51,7 @@ module up_adc_common #(
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// clock reset
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// clock reset
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output mmcm_rst,
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output mmcm_rst,
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// adc interface
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// adc interface
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@ -66,11 +66,12 @@ module up_adc_common #(
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input adc_status_unf,
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input adc_status_unf,
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input [31:0] adc_clk_ratio,
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input [31:0] adc_clk_ratio,
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output [31:0] adc_start_code,
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output [31:0] adc_start_code,
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output adc_sref_sync,
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output adc_sync,
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output adc_sync,
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output reg up_adc_ce,
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// channel interface
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// channel interface
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output up_adc_ce,
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input up_status_pn_err,
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input up_status_pn_err,
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input up_status_pn_oos,
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input up_status_pn_oos,
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input up_status_or,
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input up_status_or,
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@ -87,8 +88,8 @@ module up_adc_common #(
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// user channel control
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// user channel control
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output [ 7:0] up_usr_chanmax,
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output [ 7:0] up_usr_chanmax_out,
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input [ 7:0] adc_usr_chanmax,
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input [ 7:0] up_usr_chanmax_in,
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input [31:0] up_adc_gpio_in,
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input [31:0] up_adc_gpio_in,
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output [31:0] up_adc_gpio_out,
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output [31:0] up_adc_gpio_out,
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@ -111,77 +112,80 @@ module up_adc_common #(
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// internal registers
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// internal registers
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reg up_core_preset = 'd1;
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reg up_adc_clk_enb_int = 'd1;
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reg up_mmcm_preset = 'd1;
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reg up_core_preset = 'd1;
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reg up_wack_int = 'd0;
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reg up_mmcm_preset = 'd1;
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reg [31:0] up_scratch = 'd0;
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reg up_wack_int = 'd0;
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reg up_adc_ce_int = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_mmcm_resetn = 'd0;
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reg up_adc_clk_enb = 'd0;
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reg up_resetn = 'd0;
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reg up_mmcm_resetn = 'd0;
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reg up_adc_sync = 'd0;
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reg up_resetn = 'd0;
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reg up_adc_r1_mode = 'd0;
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reg up_adc_sync = 'd0;
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reg up_adc_ddr_edgesel = 'd0;
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reg up_adc_sref_sync = 'd0;
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reg up_adc_pin_mode = 'd0;
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reg up_adc_r1_mode = 'd0;
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reg up_drp_sel_int = 'd0;
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reg up_adc_ddr_edgesel = 'd0;
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reg up_drp_wr_int = 'd0;
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reg up_adc_pin_mode = 'd0;
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reg up_drp_status = 'd0;
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reg up_drp_sel_int = 'd0;
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reg up_drp_rwn = 'd0;
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reg up_drp_wr_int = 'd0;
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reg [11:0] up_drp_addr_int = 'd0;
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reg up_drp_status = 'd0;
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reg [31:0] up_drp_wdata_int = 'd0;
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reg up_drp_rwn = 'd0;
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reg [31:0] up_drp_rdata_hold = 'd0;
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reg [11:0] up_drp_addr_int = 'd0;
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reg up_status_ovf = 'd0;
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reg [31:0] up_drp_wdata_int = 'd0;
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reg up_status_unf = 'd0;
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reg [31:0] up_drp_rdata_hold = 'd0;
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reg [ 7:0] up_usr_chanmax_int = 'd0;
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reg up_status_ovf = 'd0;
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reg [31:0] up_adc_start_code = 'd0;
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reg up_status_unf = 'd0;
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reg [31:0] up_adc_gpio_out_int = 'd0;
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reg [ 7:0] up_usr_chanmax_int = 'd0;
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reg up_rack_int = 'd0;
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reg [31:0] up_adc_start_code = 'd0;
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reg [31:0] up_rdata_int = 'd0;
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reg [31:0] up_adc_gpio_out_int = 'd0;
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reg up_rack_int = 'd0;
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reg [31:0] up_rdata_int = 'd0;
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// internal signals
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// internal signals
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wire up_wreq_s;
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wire up_wreq_s;
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wire up_rreq_s;
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wire up_rreq_s;
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wire up_status_s;
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wire up_status_s;
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wire up_sync_status_s;
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wire up_sync_status_s;
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wire up_status_ovf_s;
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wire up_status_ovf_s;
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wire up_status_unf_s;
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wire up_status_unf_s;
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wire up_cntrl_xfer_done_s;
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wire up_cntrl_xfer_done_s;
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wire [31:0] up_adc_clk_count_s;
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wire [31:0] up_adc_clk_count_s;
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// decode block select
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0;
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assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0;
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// processor write interface
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// processor write interface
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assign up_wack = up_wack_int;
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assign up_wack = up_wack_int;
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assign up_adc_ce = up_adc_clk_enb_int;
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always @(negedge up_rstn or posedge up_clk) begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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if (up_rstn == 0) begin
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up_adc_ce <= 1'd1;
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up_adc_clk_enb_int <= 1'd1;
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up_core_preset <= 1'd1;
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up_core_preset <= 1'd1;
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up_mmcm_preset <= 1'd1;
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up_mmcm_preset <= 1'd1;
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up_wack_int <= 'd0;
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up_wack_int <= 'd0;
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up_scratch <= 'd0;
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up_scratch <= 'd0;
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up_adc_ce_int <= 'd0;
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up_adc_clk_enb <= 'd0;
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up_mmcm_resetn <= 'd0;
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up_mmcm_resetn <= 'd0;
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up_resetn <= 'd0;
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up_resetn <= 'd0;
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up_adc_sync <= 'd0;
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up_adc_sync <= 'd0;
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up_adc_sref_sync <= 'd0;
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up_adc_r1_mode <= 'd0;
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up_adc_r1_mode <= 'd0;
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up_adc_ddr_edgesel <= 'd0;
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up_adc_ddr_edgesel <= 'd0;
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up_adc_pin_mode <= 'd0;
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up_adc_pin_mode <= 'd0;
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end else begin
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end else begin
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up_adc_clk_enb_int <= ~up_adc_clk_enb;
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up_core_preset <= ~up_resetn;
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up_core_preset <= ~up_resetn;
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up_mmcm_preset <= ~up_mmcm_resetn;
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up_mmcm_preset <= ~up_mmcm_resetn;
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up_adc_ce <= ~up_adc_ce_int;
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up_wack_int <= up_wreq_s;
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up_wack_int <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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up_scratch <= up_wdata;
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end
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
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up_adc_ce_int <= up_wdata[2];
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up_adc_clk_enb <= up_wdata[2];
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up_mmcm_resetn <= up_wdata[1];
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up_mmcm_resetn <= up_wdata[1];
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up_resetn <= up_wdata[0];
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up_resetn <= up_wdata[0];
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end
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end
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@ -193,6 +197,7 @@ module up_adc_common #(
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up_adc_sync <= up_wdata[3];
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up_adc_sync <= up_wdata[3];
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end
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
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up_adc_sref_sync <= up_wdata[4];
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up_adc_r1_mode <= up_wdata[2];
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up_adc_r1_mode <= up_wdata[2];
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up_adc_ddr_edgesel <= up_wdata[1];
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up_adc_ddr_edgesel <= up_wdata[1];
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up_adc_pin_mode <= up_wdata[0];
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up_adc_pin_mode <= up_wdata[0];
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@ -272,7 +277,7 @@ module up_adc_common #(
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end
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end
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end
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end
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assign up_usr_chanmax = up_usr_chanmax_int;
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assign up_usr_chanmax_out = up_usr_chanmax_int;
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generate
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generate
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if (USERPORTS_DISABLE == 1) begin
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if (USERPORTS_DISABLE == 1) begin
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@ -347,8 +352,9 @@ module up_adc_common #(
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8'h01: up_rdata_int <= ID;
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8'h01: up_rdata_int <= ID;
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8'h02: up_rdata_int <= up_scratch;
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8'h02: up_rdata_int <= up_scratch;
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8'h03: up_rdata_int <= CONFIG;
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8'h03: up_rdata_int <= CONFIG;
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8'h10: up_rdata_int <= {29'd0, up_adc_ce_int, up_mmcm_resetn, up_resetn};
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8'h10: up_rdata_int <= {29'd0, up_adc_clk_enb, up_mmcm_resetn, up_resetn};
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8'h11: up_rdata_int <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
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8'h11: up_rdata_int <= {27'd0, up_adc_sref_sync, up_adc_sync, up_adc_r1_mode,
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up_adc_ddr_edgesel, up_adc_pin_mode};
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8'h15: up_rdata_int <= up_adc_clk_count_s;
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8'h15: up_rdata_int <= up_adc_clk_count_s;
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8'h16: up_rdata_int <= adc_clk_ratio;
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8'h16: up_rdata_int <= adc_clk_ratio;
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8'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
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8'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
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@ -359,7 +365,7 @@ module up_adc_common #(
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8'h1f: up_rdata_int <= up_drp_rdata_hold;
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8'h1f: up_rdata_int <= up_drp_rdata_hold;
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8'h22: up_rdata_int <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
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8'h22: up_rdata_int <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
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8'h23: up_rdata_int <= 32'd8;
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8'h23: up_rdata_int <= 32'd8;
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8'h28: up_rdata_int <= {24'd0, adc_usr_chanmax};
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8'h28: up_rdata_int <= {24'd0, up_usr_chanmax_in};
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8'h29: up_rdata_int <= up_adc_start_code;
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8'h29: up_rdata_int <= up_adc_start_code;
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8'h2e: up_rdata_int <= up_adc_gpio_in;
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8'h2e: up_rdata_int <= up_adc_gpio_in;
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8'h2f: up_rdata_int <= up_adc_gpio_out_int;
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8'h2f: up_rdata_int <= up_adc_gpio_out_int;
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@ -378,10 +384,11 @@ module up_adc_common #(
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// adc control & status
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// adc control & status
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up_xfer_cntrl #(.DATA_WIDTH(36)) i_xfer_cntrl (
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up_xfer_cntrl #(.DATA_WIDTH(37)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_adc_sync,
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.up_data_cntrl ({ up_adc_sref_sync,
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up_adc_sync,
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up_adc_start_code,
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up_adc_start_code,
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up_adc_r1_mode,
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up_adc_r1_mode,
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up_adc_ddr_edgesel,
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up_adc_ddr_edgesel,
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@ -389,7 +396,8 @@ module up_adc_common #(
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.up_xfer_done (up_cntrl_xfer_done_s),
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.up_xfer_done (up_cntrl_xfer_done_s),
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.d_rst (adc_rst),
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.d_rst (adc_rst),
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.d_clk (adc_clk),
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.d_clk (adc_clk),
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.d_data_cntrl ({ adc_sync,
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.d_data_cntrl ({ adc_sref_sync,
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adc_sync,
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adc_start_code,
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adc_start_code,
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adc_r1_mode,
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adc_r1_mode,
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adc_ddr_edgesel,
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adc_ddr_edgesel,
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