Update ad469x spi engine (#1181)
* Update ad469x spi engine I replaced the SPI Engine connections in the ad469x_bd.tcl with the spi_engine_create procedure found in the spi_engine.tcl script. Through these changes, a more generic instantiation for the spi_engine can be achieved. I also created the ad469x_fmc.txt file for generating the system_constr.xdc file. Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>main
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Here are some pointers to help you:
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* [Board Product Page](https://www.analog.com/eval-ad4696)
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* Parts : [16-Bit, 16-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4696)
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[16-Bit, 16-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4695)
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[16-Bit, 8-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4697)
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[16-Bit, 8-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4696)
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* Parts : [AD4696, 16-Bit, 16-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4696)
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* Parts : [AD4695, 16-Bit, 16-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4695)
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* Parts : [AD4697, 16-Bit, 8-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4697)
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* Parts : [AD4698, 16-Bit, 8-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4698)
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* Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad469x
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* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad469x
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* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all
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FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
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# ad469x
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D8 FMC_LA01_CC_P SDO ad469x_spi_sdi LVCMOS25 #N/A
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D9 FMC_LA01_CC_N SCK ad469x_spi_sclk LVCMOS25 #N/A
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G6 FMC_LA00_CC_P CS_N ad469x_spi_cs LVCMOS25 #N/A
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G7 FMC_LA00_CC_N CNV_FMC ad469x_spi_cnv LVCMOS25 #N/A
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H7 FMC_LA02_P SDI ad469x_spi_sdo LVCMOS25 #N/A
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H10 FMC_LA04_P RESET ad469x_resetn LVCMOS25 #N/A
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H8 FMC_LA02_N GP0 ad469x_busy_alt_gp0 LVCMOS25 #N/A
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###############################################################################
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# ad4696_fmc SPI interface
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi] ; ## D08 FMC_LPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdo] ; ## H07 FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sclk] ; ## D09 FMC_LPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cs] ; ## G06 FMC_LPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cnv] ; ## G07 FMC_LPC_LA00_CC_N
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi] ; ## D08 FMC_LA01_CC_P IO_L14P_T2_SRCC_34
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdo] ; ## H07 FMC_LA02_P IO_L20P_T3_34
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sclk] ; ## D09 FMC_LA01_CC_N IO_L14N_T2_SRCC_34
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cs] ; ## G06 FMC_LA00_CC_P IO_L13P_T2_MRCC_34
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cnv] ; ## G07 FMC_LA00_CC_N IO_L13N_T2_MRCC_34
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set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad469x_resetn] ; ## H10 FMC_LPC_LA04_P
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set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad469x_busy_alt_gp0] ; ## H08 FMC_LPC_LA02_N
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set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad469x_resetn] ; ## H10 FMC_LA04_P IO_L15P_T2_DQS_34
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set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad469x_busy_alt_gp0] ; ## H08 FMC_LA02_N IO_L20N_T3_34
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# rename auto-generated clock for SPIEngine to spi_clk - 160MHz
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# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
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