diff --git a/library/axi_adc_decimate/Makefile b/library/axi_adc_decimate/Makefile index 837c24a7b..175862945 100644 --- a/library/axi_adc_decimate/Makefile +++ b/library/axi_adc_decimate/Makefile @@ -10,8 +10,8 @@ M_DEPS += ../common/up_axi.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc M_DEPS += axi_adc_decimate.v -M_DEPS += axi_adc_decimate_constr.xdc M_DEPS += axi_adc_decimate_filter.v M_DEPS += axi_adc_decimate_ip.tcl M_DEPS += axi_adc_decimate_reg.v diff --git a/library/axi_adc_decimate/axi_adc_decimate_constr.xdc b/library/axi_adc_decimate/axi_adc_decimate_constr.xdc deleted file mode 100644 index 7b012252b..000000000 --- a/library/axi_adc_decimate/axi_adc_decimate_constr.xdc +++ /dev/null @@ -1,7 +0,0 @@ -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}] -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}] -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}] - -set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] diff --git a/library/axi_adc_decimate/axi_adc_decimate_ip.tcl b/library/axi_adc_decimate/axi_adc_decimate_ip.tcl index 303c673da..8934a8f23 100644 --- a/library/axi_adc_decimate/axi_adc_decimate_ip.tcl +++ b/library/axi_adc_decimate/axi_adc_decimate_ip.tcl @@ -8,7 +8,7 @@ adi_ip_files axi_adc_decimate [list \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/ad_iqcor.v" \ - "axi_adc_decimate_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ "fir_decim.v" \ "cic_decim.v" \ "axi_adc_decimate_filter.v" \ diff --git a/library/axi_adc_trigger/Makefile b/library/axi_adc_trigger/Makefile index c2ab354f1..1496e40ca 100644 --- a/library/axi_adc_trigger/Makefile +++ b/library/axi_adc_trigger/Makefile @@ -9,6 +9,7 @@ M_DEPS += ../common/up_axi.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc M_DEPS += axi_adc_trigger.v M_DEPS += axi_adc_trigger_constr.xdc M_DEPS += axi_adc_trigger_ip.tcl diff --git a/library/axi_adc_trigger/axi_adc_trigger_constr.xdc b/library/axi_adc_trigger/axi_adc_trigger_constr.xdc index a5fd7c12f..9827fc7d7 100644 --- a/library/axi_adc_trigger/axi_adc_trigger_constr.xdc +++ b/library/axi_adc_trigger/axi_adc_trigger_constr.xdc @@ -1,14 +1,11 @@ -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}] -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_a_d*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_b_d*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}] -set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg* && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg* && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}] diff --git a/library/axi_adc_trigger/axi_adc_trigger_ip.tcl b/library/axi_adc_trigger/axi_adc_trigger_ip.tcl index 4dec51fbf..e4ee0662c 100644 --- a/library/axi_adc_trigger/axi_adc_trigger_ip.tcl +++ b/library/axi_adc_trigger/axi_adc_trigger_ip.tcl @@ -7,6 +7,7 @@ adi_ip_create axi_adc_trigger adi_ip_files axi_adc_trigger [list \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ "axi_adc_trigger_constr.xdc" \ "axi_adc_trigger_reg.v" \ "axi_adc_trigger.v" ] diff --git a/library/axi_dac_interpolate/Makefile b/library/axi_dac_interpolate/Makefile index f5ce5311f..c3307e486 100644 --- a/library/axi_dac_interpolate/Makefile +++ b/library/axi_dac_interpolate/Makefile @@ -11,8 +11,8 @@ M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../xilinx/common/ad_mul.v +M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc M_DEPS += axi_dac_interpolate.v -M_DEPS += axi_dac_interpolate_constr.xdc M_DEPS += axi_dac_interpolate_filter.v M_DEPS += axi_dac_interpolate_ip.tcl M_DEPS += axi_dac_interpolate_reg.v diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc b/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc deleted file mode 100644 index 9ee64a1e4..000000000 --- a/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc +++ /dev/null @@ -1,9 +0,0 @@ - -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}] -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}] -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}] - -set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] - diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl b/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl index a56772173..8df5cc386 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl +++ b/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl @@ -9,7 +9,7 @@ adi_ip_files axi_dac_interpolate [list \ "$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/ad_iqcor.v" \ "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ - "axi_dac_interpolate_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ "cic_interp.v" \ "fir_interp.v" \ "axi_dac_interpolate_reg.v" \ diff --git a/library/axi_logic_analyzer/Makefile b/library/axi_logic_analyzer/Makefile index f538e037e..4ce6b81cd 100644 --- a/library/axi_logic_analyzer/Makefile +++ b/library/axi_logic_analyzer/Makefile @@ -11,6 +11,9 @@ M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_rst_constr.xdc +M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc M_DEPS += axi_logic_analyzer.v M_DEPS += axi_logic_analyzer_constr.xdc M_DEPS += axi_logic_analyzer_ip.tcl diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc b/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc index 5ae8b47a3..cce919845 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc +++ b/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc @@ -1,33 +1,7 @@ -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}] -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}] -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}] -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}] -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}] -set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg* && IS_SEQUENTIAL}] \ - -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && IS_SEQUENTIAL}] \ - -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] \ - -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] - -set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \ - -to [get_cells -hier -filter {name =~ *downsampler_counter_* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \ - -to [get_cells -hier -filter {name =~ *data_r_reg* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \ - -to [get_cells -hier -filter {name =~ *dac_read_reg* && IS_SEQUENTIAL}] - -set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && IS_SEQUENTIAL}] \ - -to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] \ - -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && IS_SEQUENTIAL}] \ - -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg* && IS_SEQUENTIAL}] - -set_false_path -to [get_cells -hier -filter {name =~ *trigger_m1_reg* && IS_SEQUENTIAL}] - -set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_pins BUFGMUX_CTRL_inst/S*] + set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}] diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl b/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl index 85a0eacec..913b71da8 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl +++ b/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl @@ -9,6 +9,9 @@ adi_ip_files axi_logic_analyzer [list \ "$ad_hdl_dir/library/common/up_xfer_status.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ "axi_logic_analyzer_constr.xdc" \ "axi_logic_analyzer_reg.v" \ "axi_logic_analyzer_trigger.v" \