From d3c6771ad63fe0ccf4f9883b5ebf8133390e9cec Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 10 May 2017 11:12:45 +0300 Subject: [PATCH] axi_ad9371: Update dac_clk_ratio to 2 DAC sampling frequency is two times of the JESD204 core clock. --- library/axi_ad9371/axi_ad9371_tx.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_ad9371/axi_ad9371_tx.v b/library/axi_ad9371/axi_ad9371_tx.v index ce64c0e6a..853b4fec4 100644 --- a/library/axi_ad9371/axi_ad9371_tx.v +++ b/library/axi_ad9371/axi_ad9371_tx.v @@ -301,7 +301,7 @@ module axi_ad9371_tx ( .dac_status (1'b1), .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), - .dac_clk_ratio (32'd1), + .dac_clk_ratio (32'd2), .up_drp_sel (), .up_drp_wr (), .up_drp_addr (),