axi_ad9371: Update dac_clk_ratio to 2

DAC sampling frequency is two times of the JESD204 core clock.
2017-05-10 11:12:45 +03:00 · 2017-05-10 11:12:45 +03:00 · d3c6771ad6
parent e2ef470150
commit d3c6771ad6
1 changed files with 1 additions and 1 deletions
--- a/library/axi_ad9371/axi_ad9371_tx.v
+++ b/library/axi_ad9371/axi_ad9371_tx.v
@ -301,7 +301,7 @@ module axi_ad9371_tx (
    .dac_status (1'b1),
    .dac_status_ovf (dac_dovf),
    .dac_status_unf (dac_dunf),
-    .dac_clk_ratio (32'd1),
+    .dac_clk_ratio (32'd2),
    .up_drp_sel (),
    .up_drp_wr (),
    .up_drp_addr (),