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lower the address space requirements

main
Rejeesh Kutty 2014-03-26 11:03:22 -04:00
parent 9b4539b7c2
commit d3d26e1220
2 changed files with 32 additions and 32 deletions
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36
library/axi_dmac/axi_dmac_alt.v
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@ -207,8 +207,8 @@ module axi_dmac_alt (
input s_axi_aclk; input s_axi_aclk;
input s_axi_aresetn; input s_axi_aresetn;
input s_axi_awvalid; input s_axi_awvalid;
input [31:0] s_axi_awaddr; input [13:0] s_axi_awaddr;
input [ 0:0] s_axi_awid; input [ 1:0] s_axi_awid;
input [ 7:0] s_axi_awlen; input [ 7:0] s_axi_awlen;
input [ 2:0] s_axi_awsize; input [ 2:0] s_axi_awsize;
input [ 1:0] s_axi_awburst; input [ 1:0] s_axi_awburst;
@ -223,11 +223,11 @@ module axi_dmac_alt (
output s_axi_wready; output s_axi_wready;
output s_axi_bvalid; output s_axi_bvalid;
output [ 1:0] s_axi_bresp; output [ 1:0] s_axi_bresp;
output [ 0:0] s_axi_bid; output [ 1:0] s_axi_bid;
input s_axi_bready; input s_axi_bready;
input s_axi_arvalid; input s_axi_arvalid;
input [31:0] s_axi_araddr; input [13:0] s_axi_araddr;
input [ 0:0] s_axi_arid; input [ 1:0] s_axi_arid;
input [ 7:0] s_axi_arlen; input [ 7:0] s_axi_arlen;
input [ 2:0] s_axi_arsize; input [ 2:0] s_axi_arsize;
input [ 1:0] s_axi_arburst; input [ 1:0] s_axi_arburst;
@ -238,7 +238,7 @@ module axi_dmac_alt (
output s_axi_rvalid; output s_axi_rvalid;
output [ 1:0] s_axi_rresp; output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata; output [31:0] s_axi_rdata;
output [ 0:0] s_axi_rid; output [ 1:0] s_axi_rid;
output s_axi_rlast; output s_axi_rlast;
input s_axi_rready; input s_axi_rready;
@ -248,7 +248,7 @@ module axi_dmac_alt (
input m_dest_axi_aresetn; input m_dest_axi_aresetn;
output m_dest_axi_awvalid; output m_dest_axi_awvalid;
output [31:0] m_dest_axi_awaddr; output [31:0] m_dest_axi_awaddr;
output [ 0:0] m_dest_axi_awid; output [ 1:0] m_dest_axi_awid;
output [ 7:0] m_dest_axi_awlen; output [ 7:0] m_dest_axi_awlen;
output [ 2:0] m_dest_axi_awsize; output [ 2:0] m_dest_axi_awsize;
output [ 1:0] m_dest_axi_awburst; output [ 1:0] m_dest_axi_awburst;
@ -263,11 +263,11 @@ module axi_dmac_alt (
input m_dest_axi_wready; input m_dest_axi_wready;
input m_dest_axi_bvalid; input m_dest_axi_bvalid;
input [ 1:0] m_dest_axi_bresp; input [ 1:0] m_dest_axi_bresp;
input [ 0:0] m_dest_axi_bid; input [ 1:0] m_dest_axi_bid;
output m_dest_axi_bready; output m_dest_axi_bready;
output m_dest_axi_arvalid; output m_dest_axi_arvalid;
output [31:0] m_dest_axi_araddr; output [31:0] m_dest_axi_araddr;
output [ 0:0] m_dest_axi_arid; output [ 1:0] m_dest_axi_arid;
output [ 7:0] m_dest_axi_arlen; output [ 7:0] m_dest_axi_arlen;
output [ 2:0] m_dest_axi_arsize; output [ 2:0] m_dest_axi_arsize;
output [ 1:0] m_dest_axi_arburst; output [ 1:0] m_dest_axi_arburst;
@ -278,7 +278,7 @@ module axi_dmac_alt (
input m_dest_axi_rvalid; input m_dest_axi_rvalid;
input [ 1:0] m_dest_axi_rresp; input [ 1:0] m_dest_axi_rresp;
input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata; input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata;
input [ 0:0] m_dest_axi_rid; input [ 1:0] m_dest_axi_rid;
input m_dest_axi_rlast; input m_dest_axi_rlast;
output m_dest_axi_rready; output m_dest_axi_rready;
@ -288,7 +288,7 @@ module axi_dmac_alt (
input m_src_axi_aresetn; input m_src_axi_aresetn;
output m_src_axi_awvalid; output m_src_axi_awvalid;
output [31:0] m_src_axi_awaddr; output [31:0] m_src_axi_awaddr;
output [ 0:0] m_src_axi_awid; output [ 1:0] m_src_axi_awid;
output [ 7:0] m_src_axi_awlen; output [ 7:0] m_src_axi_awlen;
output [ 2:0] m_src_axi_awsize; output [ 2:0] m_src_axi_awsize;
output [ 1:0] m_src_axi_awburst; output [ 1:0] m_src_axi_awburst;
@ -303,11 +303,11 @@ module axi_dmac_alt (
input m_src_axi_wready; input m_src_axi_wready;
input m_src_axi_bvalid; input m_src_axi_bvalid;
input [ 1:0] m_src_axi_bresp; input [ 1:0] m_src_axi_bresp;
input [ 0:0] m_src_axi_bid; input [ 1:0] m_src_axi_bid;
output m_src_axi_bready; output m_src_axi_bready;
output m_src_axi_arvalid; output m_src_axi_arvalid;
output [31:0] m_src_axi_araddr; output [31:0] m_src_axi_araddr;
output [ 0:0] m_src_axi_arid; output [ 1:0] m_src_axi_arid;
output [ 7:0] m_src_axi_arlen; output [ 7:0] m_src_axi_arlen;
output [ 2:0] m_src_axi_arsize; output [ 2:0] m_src_axi_arsize;
output [ 1:0] m_src_axi_arburst; output [ 1:0] m_src_axi_arburst;
@ -318,7 +318,7 @@ module axi_dmac_alt (
input m_src_axi_rvalid; input m_src_axi_rvalid;
input [ 1:0] m_src_axi_rresp; input [ 1:0] m_src_axi_rresp;
input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata; input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata;
input [ 0:0] m_src_axi_rid; input [ 1:0] m_src_axi_rid;
input m_src_axi_rlast; input m_src_axi_rlast;
output m_src_axi_rready; output m_src_axi_rready;
@ -349,8 +349,8 @@ module axi_dmac_alt (
// defaults // defaults
assign s_axi_bid = 1'd0; assign s_axi_bid = 2'd0;
assign s_axi_rid = 1'd0; assign s_axi_rid = 2'd0;
assign s_axi_rlast = 1'd0; assign s_axi_rlast = 1'd0;
// instantiation // instantiation
@ -377,7 +377,7 @@ module axi_dmac_alt (
.s_axi_aclk (s_axi_aclk), .s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn), .s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid), .s_axi_awvalid (s_axi_awvalid),
.s_axi_awaddr (s_axi_awaddr), .s_axi_awaddr ({18'd0, s_axi_awaddr}),
.s_axi_awready (s_axi_awready), .s_axi_awready (s_axi_awready),
.s_axi_wvalid (s_axi_wvalid), .s_axi_wvalid (s_axi_wvalid),
.s_axi_wdata (s_axi_wdata), .s_axi_wdata (s_axi_wdata),
@ -387,7 +387,7 @@ module axi_dmac_alt (
.s_axi_bresp (s_axi_bresp), .s_axi_bresp (s_axi_bresp),
.s_axi_bready (s_axi_bready), .s_axi_bready (s_axi_bready),
.s_axi_arvalid (s_axi_arvalid), .s_axi_arvalid (s_axi_arvalid),
.s_axi_araddr (s_axi_araddr), .s_axi_araddr ({18'd0, s_axi_araddr}),
.s_axi_arready (s_axi_arready), .s_axi_arready (s_axi_arready),
.s_axi_rvalid (s_axi_rvalid), .s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready), .s_axi_rready (s_axi_rready),

28
library/axi_dmac/axi_dmac_hw.tcl
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@ -157,7 +157,7 @@ add_interface s_axi axi4 end
set_interface_property s_axi associatedClock s_axi_clock set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1 add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 32 add_interface_port s_axi s_axi_awaddr awaddr Input 14
add_interface_port s_axi s_axi_awready awready Output 1 add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1 add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32 add_interface_port s_axi s_axi_wdata wdata Input 32
@ -167,13 +167,13 @@ add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2 add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1 add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1 add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 32 add_interface_port s_axi s_axi_araddr araddr Input 14
add_interface_port s_axi s_axi_arready arready Output 1 add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1 add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2 add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32 add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1 add_interface_port s_axi s_axi_rready rready Input 1
add_interface_port s_axi s_axi_awid awid Input 1 add_interface_port s_axi s_axi_awid awid Input 2
add_interface_port s_axi s_axi_awlen awlen Input 8 add_interface_port s_axi s_axi_awlen awlen Input 8
add_interface_port s_axi s_axi_awsize awsize Input 3 add_interface_port s_axi s_axi_awsize awsize Input 3
add_interface_port s_axi s_axi_awburst awburst Input 2 add_interface_port s_axi s_axi_awburst awburst Input 2
@ -181,15 +181,15 @@ add_interface_port s_axi s_axi_awlock awlock Input 1
add_interface_port s_axi s_axi_awcache awcache Input 4 add_interface_port s_axi s_axi_awcache awcache Input 4
add_interface_port s_axi s_axi_awprot awprot Input 3 add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_wlast wlast Input 1 add_interface_port s_axi s_axi_wlast wlast Input 1
add_interface_port s_axi s_axi_bid bid Output 1 add_interface_port s_axi s_axi_bid bid Output 2
add_interface_port s_axi s_axi_arid arid Input 1 add_interface_port s_axi s_axi_arid arid Input 2
add_interface_port s_axi s_axi_arlen arlen Input 8 add_interface_port s_axi s_axi_arlen arlen Input 8
add_interface_port s_axi s_axi_arsize arsize Input 3 add_interface_port s_axi s_axi_arsize arsize Input 3
add_interface_port s_axi s_axi_arburst arburst Input 2 add_interface_port s_axi s_axi_arburst arburst Input 2
add_interface_port s_axi s_axi_arlock arlock Input 1 add_interface_port s_axi s_axi_arlock arlock Input 1
add_interface_port s_axi s_axi_arcache arcache Input 4 add_interface_port s_axi s_axi_arcache arcache Input 4
add_interface_port s_axi s_axi_arprot arprot Input 3 add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_rid rid Output 1 add_interface_port s_axi s_axi_rid rid Output 2
add_interface_port s_axi s_axi_rlast rlast Output 1 add_interface_port s_axi s_axi_rlast rlast Output 1
# conditional interface # conditional interface
@ -227,7 +227,7 @@ proc axi_dmac_elaborate {} {
add_interface_port m_dest_axi m_dest_axi_rresp rresp Input 2 add_interface_port m_dest_axi m_dest_axi_rresp rresp Input 2
add_interface_port m_dest_axi m_dest_axi_rdata rdata Input C_DMA_DATA_WIDTH_DEST add_interface_port m_dest_axi m_dest_axi_rdata rdata Input C_DMA_DATA_WIDTH_DEST
add_interface_port m_dest_axi m_dest_axi_rready rready Output 1 add_interface_port m_dest_axi m_dest_axi_rready rready Output 1
add_interface_port m_dest_axi m_dest_axi_awid awid Output 1 add_interface_port m_dest_axi m_dest_axi_awid awid Output 2
add_interface_port m_dest_axi m_dest_axi_awlen awlen Output 8 add_interface_port m_dest_axi m_dest_axi_awlen awlen Output 8
add_interface_port m_dest_axi m_dest_axi_awsize awsize Output 3 add_interface_port m_dest_axi m_dest_axi_awsize awsize Output 3
add_interface_port m_dest_axi m_dest_axi_awburst awburst Output 2 add_interface_port m_dest_axi m_dest_axi_awburst awburst Output 2
@ -235,15 +235,15 @@ proc axi_dmac_elaborate {} {
add_interface_port m_dest_axi m_dest_axi_awcache awcache Output 4 add_interface_port m_dest_axi m_dest_axi_awcache awcache Output 4
add_interface_port m_dest_axi m_dest_axi_awprot awprot Output 3 add_interface_port m_dest_axi m_dest_axi_awprot awprot Output 3
add_interface_port m_dest_axi m_dest_axi_wlast wlast Output 1 add_interface_port m_dest_axi m_dest_axi_wlast wlast Output 1
add_interface_port m_dest_axi m_dest_axi_bid bid Input 1 add_interface_port m_dest_axi m_dest_axi_bid bid Input 2
add_interface_port m_dest_axi m_dest_axi_arid arid Output 1 add_interface_port m_dest_axi m_dest_axi_arid arid Output 2
add_interface_port m_dest_axi m_dest_axi_arlen arlen Output 8 add_interface_port m_dest_axi m_dest_axi_arlen arlen Output 8
add_interface_port m_dest_axi m_dest_axi_arsize arsize Output 3 add_interface_port m_dest_axi m_dest_axi_arsize arsize Output 3
add_interface_port m_dest_axi m_dest_axi_arburst arburst Output 2 add_interface_port m_dest_axi m_dest_axi_arburst arburst Output 2
add_interface_port m_dest_axi m_dest_axi_arlock arlock Output 1 add_interface_port m_dest_axi m_dest_axi_arlock arlock Output 1
add_interface_port m_dest_axi m_dest_axi_arcache arcache Output 4 add_interface_port m_dest_axi m_dest_axi_arcache arcache Output 4
add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3 add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3
add_interface_port m_dest_axi m_dest_axi_rid rid Input 1 add_interface_port m_dest_axi m_dest_axi_rid rid Input 2
add_interface_port m_dest_axi m_dest_axi_rlast rlast Input 1 add_interface_port m_dest_axi m_dest_axi_rlast rlast Input 1
} }
@ -276,7 +276,7 @@ proc axi_dmac_elaborate {} {
add_interface_port m_src_axi m_src_axi_rresp rresp Input 2 add_interface_port m_src_axi m_src_axi_rresp rresp Input 2
add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC
add_interface_port m_src_axi m_src_axi_rready rready Output 1 add_interface_port m_src_axi m_src_axi_rready rready Output 1
add_interface_port m_src_axi m_src_axi_awid awid Output 1 add_interface_port m_src_axi m_src_axi_awid awid Output 2
add_interface_port m_src_axi m_src_axi_awlen awlen Output 8 add_interface_port m_src_axi m_src_axi_awlen awlen Output 8
add_interface_port m_src_axi m_src_axi_awsize awsize Output 3 add_interface_port m_src_axi m_src_axi_awsize awsize Output 3
add_interface_port m_src_axi m_src_axi_awburst awburst Output 2 add_interface_port m_src_axi m_src_axi_awburst awburst Output 2
@ -284,15 +284,15 @@ proc axi_dmac_elaborate {} {
add_interface_port m_src_axi m_src_axi_awcache awcache Output 4 add_interface_port m_src_axi m_src_axi_awcache awcache Output 4
add_interface_port m_src_axi m_src_axi_awprot awprot Output 3 add_interface_port m_src_axi m_src_axi_awprot awprot Output 3
add_interface_port m_src_axi m_src_axi_wlast wlast Output 1 add_interface_port m_src_axi m_src_axi_wlast wlast Output 1
add_interface_port m_src_axi m_src_axi_bid bid Input 1 add_interface_port m_src_axi m_src_axi_bid bid Input 2
add_interface_port m_src_axi m_src_axi_arid arid Output 1 add_interface_port m_src_axi m_src_axi_arid arid Output 2
add_interface_port m_src_axi m_src_axi_arlen arlen Output 8 add_interface_port m_src_axi m_src_axi_arlen arlen Output 8
add_interface_port m_src_axi m_src_axi_arsize arsize Output 3 add_interface_port m_src_axi m_src_axi_arsize arsize Output 3
add_interface_port m_src_axi m_src_axi_arburst arburst Output 2 add_interface_port m_src_axi m_src_axi_arburst arburst Output 2
add_interface_port m_src_axi m_src_axi_arlock arlock Output 1 add_interface_port m_src_axi m_src_axi_arlock arlock Output 1
add_interface_port m_src_axi m_src_axi_arcache arcache Output 4 add_interface_port m_src_axi m_src_axi_arcache arcache Output 4
add_interface_port m_src_axi m_src_axi_arprot arprot Output 3 add_interface_port m_src_axi m_src_axi_arprot arprot Output 3
add_interface_port m_src_axi m_src_axi_rid rid Input 1 add_interface_port m_src_axi m_src_axi_rid rid Input 2
add_interface_port m_src_axi m_src_axi_rlast rlast Input 1 add_interface_port m_src_axi m_src_axi_rlast rlast Input 1
} }