lower the address space requirements
Rejeesh Kutty
parent
9b4539b7c2
commit
d3d26e1220
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@ -207,8 +207,8 @@ module axi_dmac_alt (
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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input [ 0:0] s_axi_awid;
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input [13:0] s_axi_awaddr;
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input [ 1:0] s_axi_awid;
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input [ 7:0] s_axi_awlen;
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input [ 2:0] s_axi_awsize;
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input [ 1:0] s_axi_awburst;
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@ -223,11 +223,11 @@ module axi_dmac_alt (
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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output [ 0:0] s_axi_bid;
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output [ 1:0] s_axi_bid;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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input [ 0:0] s_axi_arid;
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input [13:0] s_axi_araddr;
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input [ 1:0] s_axi_arid;
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input [ 7:0] s_axi_arlen;
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input [ 2:0] s_axi_arsize;
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input [ 1:0] s_axi_arburst;
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@ -238,7 +238,7 @@ module axi_dmac_alt (
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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output [ 0:0] s_axi_rid;
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output [ 1:0] s_axi_rid;
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output s_axi_rlast;
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input s_axi_rready;
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@ -248,7 +248,7 @@ module axi_dmac_alt (
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input m_dest_axi_aresetn;
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output m_dest_axi_awvalid;
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output [31:0] m_dest_axi_awaddr;
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output [ 0:0] m_dest_axi_awid;
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output [ 1:0] m_dest_axi_awid;
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output [ 7:0] m_dest_axi_awlen;
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output [ 2:0] m_dest_axi_awsize;
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output [ 1:0] m_dest_axi_awburst;
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@ -263,11 +263,11 @@ module axi_dmac_alt (
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input m_dest_axi_wready;
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input m_dest_axi_bvalid;
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input [ 1:0] m_dest_axi_bresp;
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input [ 0:0] m_dest_axi_bid;
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input [ 1:0] m_dest_axi_bid;
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output m_dest_axi_bready;
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output m_dest_axi_arvalid;
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output [31:0] m_dest_axi_araddr;
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output [ 0:0] m_dest_axi_arid;
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output [ 1:0] m_dest_axi_arid;
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output [ 7:0] m_dest_axi_arlen;
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output [ 2:0] m_dest_axi_arsize;
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output [ 1:0] m_dest_axi_arburst;
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@ -278,7 +278,7 @@ module axi_dmac_alt (
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input m_dest_axi_rvalid;
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input [ 1:0] m_dest_axi_rresp;
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input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata;
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input [ 0:0] m_dest_axi_rid;
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input [ 1:0] m_dest_axi_rid;
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input m_dest_axi_rlast;
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output m_dest_axi_rready;
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@ -288,7 +288,7 @@ module axi_dmac_alt (
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input m_src_axi_aresetn;
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output m_src_axi_awvalid;
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output [31:0] m_src_axi_awaddr;
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output [ 0:0] m_src_axi_awid;
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output [ 1:0] m_src_axi_awid;
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output [ 7:0] m_src_axi_awlen;
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output [ 2:0] m_src_axi_awsize;
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output [ 1:0] m_src_axi_awburst;
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@ -303,11 +303,11 @@ module axi_dmac_alt (
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input m_src_axi_wready;
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input m_src_axi_bvalid;
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input [ 1:0] m_src_axi_bresp;
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input [ 0:0] m_src_axi_bid;
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input [ 1:0] m_src_axi_bid;
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output m_src_axi_bready;
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output m_src_axi_arvalid;
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output [31:0] m_src_axi_araddr;
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output [ 0:0] m_src_axi_arid;
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output [ 1:0] m_src_axi_arid;
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output [ 7:0] m_src_axi_arlen;
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output [ 2:0] m_src_axi_arsize;
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output [ 1:0] m_src_axi_arburst;
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@ -318,7 +318,7 @@ module axi_dmac_alt (
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input m_src_axi_rvalid;
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input [ 1:0] m_src_axi_rresp;
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input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata;
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input [ 0:0] m_src_axi_rid;
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input [ 1:0] m_src_axi_rid;
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input m_src_axi_rlast;
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output m_src_axi_rready;
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@ -349,8 +349,8 @@ module axi_dmac_alt (
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// defaults
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assign s_axi_bid = 1'd0;
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assign s_axi_rid = 1'd0;
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assign s_axi_bid = 2'd0;
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assign s_axi_rid = 2'd0;
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assign s_axi_rlast = 1'd0;
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// instantiation
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@ -377,7 +377,7 @@ module axi_dmac_alt (
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awaddr ({18'd0, s_axi_awaddr}),
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.s_axi_awready (s_axi_awready),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wdata (s_axi_wdata),
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@ -387,7 +387,7 @@ module axi_dmac_alt (
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bready (s_axi_bready),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_araddr (s_axi_araddr),
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.s_axi_araddr ({18'd0, s_axi_araddr}),
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.s_axi_arready (s_axi_arready),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready (s_axi_rready),
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@ -157,7 +157,7 @@ add_interface s_axi axi4 end
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set_interface_property s_axi associatedClock s_axi_clock
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set_interface_property s_axi associatedReset s_axi_reset
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add_interface_port s_axi s_axi_awvalid awvalid Input 1
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add_interface_port s_axi s_axi_awaddr awaddr Input 32
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add_interface_port s_axi s_axi_awaddr awaddr Input 14
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add_interface_port s_axi s_axi_awready awready Output 1
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add_interface_port s_axi s_axi_wvalid wvalid Input 1
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add_interface_port s_axi s_axi_wdata wdata Input 32
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@ -167,13 +167,13 @@ add_interface_port s_axi s_axi_bvalid bvalid Output 1
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add_interface_port s_axi s_axi_bresp bresp Output 2
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add_interface_port s_axi s_axi_bready bready Input 1
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add_interface_port s_axi s_axi_arvalid arvalid Input 1
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add_interface_port s_axi s_axi_araddr araddr Input 32
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add_interface_port s_axi s_axi_araddr araddr Input 14
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add_interface_port s_axi s_axi_arready arready Output 1
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add_interface_port s_axi s_axi_rvalid rvalid Output 1
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add_interface_port s_axi s_axi_rresp rresp Output 2
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add_interface_port s_axi s_axi_rdata rdata Output 32
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add_interface_port s_axi s_axi_rready rready Input 1
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add_interface_port s_axi s_axi_awid awid Input 1
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add_interface_port s_axi s_axi_awid awid Input 2
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add_interface_port s_axi s_axi_awlen awlen Input 8
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add_interface_port s_axi s_axi_awsize awsize Input 3
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add_interface_port s_axi s_axi_awburst awburst Input 2
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@ -181,15 +181,15 @@ add_interface_port s_axi s_axi_awlock awlock Input 1
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add_interface_port s_axi s_axi_awcache awcache Input 4
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add_interface_port s_axi s_axi_awprot awprot Input 3
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add_interface_port s_axi s_axi_wlast wlast Input 1
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add_interface_port s_axi s_axi_bid bid Output 1
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add_interface_port s_axi s_axi_arid arid Input 1
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add_interface_port s_axi s_axi_bid bid Output 2
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add_interface_port s_axi s_axi_arid arid Input 2
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add_interface_port s_axi s_axi_arlen arlen Input 8
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add_interface_port s_axi s_axi_arsize arsize Input 3
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add_interface_port s_axi s_axi_arburst arburst Input 2
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add_interface_port s_axi s_axi_arlock arlock Input 1
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add_interface_port s_axi s_axi_arcache arcache Input 4
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add_interface_port s_axi s_axi_arprot arprot Input 3
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add_interface_port s_axi s_axi_rid rid Output 1
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add_interface_port s_axi s_axi_rid rid Output 2
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add_interface_port s_axi s_axi_rlast rlast Output 1
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# conditional interface
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@ -227,7 +227,7 @@ proc axi_dmac_elaborate {} {
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add_interface_port m_dest_axi m_dest_axi_rresp rresp Input 2
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add_interface_port m_dest_axi m_dest_axi_rdata rdata Input C_DMA_DATA_WIDTH_DEST
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add_interface_port m_dest_axi m_dest_axi_rready rready Output 1
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add_interface_port m_dest_axi m_dest_axi_awid awid Output 1
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add_interface_port m_dest_axi m_dest_axi_awid awid Output 2
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add_interface_port m_dest_axi m_dest_axi_awlen awlen Output 8
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add_interface_port m_dest_axi m_dest_axi_awsize awsize Output 3
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add_interface_port m_dest_axi m_dest_axi_awburst awburst Output 2
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@ -235,15 +235,15 @@ proc axi_dmac_elaborate {} {
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add_interface_port m_dest_axi m_dest_axi_awcache awcache Output 4
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add_interface_port m_dest_axi m_dest_axi_awprot awprot Output 3
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add_interface_port m_dest_axi m_dest_axi_wlast wlast Output 1
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add_interface_port m_dest_axi m_dest_axi_bid bid Input 1
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add_interface_port m_dest_axi m_dest_axi_arid arid Output 1
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add_interface_port m_dest_axi m_dest_axi_bid bid Input 2
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add_interface_port m_dest_axi m_dest_axi_arid arid Output 2
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add_interface_port m_dest_axi m_dest_axi_arlen arlen Output 8
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add_interface_port m_dest_axi m_dest_axi_arsize arsize Output 3
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add_interface_port m_dest_axi m_dest_axi_arburst arburst Output 2
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add_interface_port m_dest_axi m_dest_axi_arlock arlock Output 1
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add_interface_port m_dest_axi m_dest_axi_arcache arcache Output 4
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add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3
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add_interface_port m_dest_axi m_dest_axi_rid rid Input 1
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add_interface_port m_dest_axi m_dest_axi_rid rid Input 2
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add_interface_port m_dest_axi m_dest_axi_rlast rlast Input 1
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}
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@ -276,7 +276,7 @@ proc axi_dmac_elaborate {} {
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add_interface_port m_src_axi m_src_axi_rresp rresp Input 2
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add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC
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add_interface_port m_src_axi m_src_axi_rready rready Output 1
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add_interface_port m_src_axi m_src_axi_awid awid Output 1
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add_interface_port m_src_axi m_src_axi_awid awid Output 2
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add_interface_port m_src_axi m_src_axi_awlen awlen Output 8
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add_interface_port m_src_axi m_src_axi_awsize awsize Output 3
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add_interface_port m_src_axi m_src_axi_awburst awburst Output 2
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@ -284,15 +284,15 @@ proc axi_dmac_elaborate {} {
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add_interface_port m_src_axi m_src_axi_awcache awcache Output 4
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add_interface_port m_src_axi m_src_axi_awprot awprot Output 3
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add_interface_port m_src_axi m_src_axi_wlast wlast Output 1
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add_interface_port m_src_axi m_src_axi_bid bid Input 1
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add_interface_port m_src_axi m_src_axi_arid arid Output 1
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add_interface_port m_src_axi m_src_axi_bid bid Input 2
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add_interface_port m_src_axi m_src_axi_arid arid Output 2
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add_interface_port m_src_axi m_src_axi_arlen arlen Output 8
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add_interface_port m_src_axi m_src_axi_arsize arsize Output 3
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add_interface_port m_src_axi m_src_axi_arburst arburst Output 2
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add_interface_port m_src_axi m_src_axi_arlock arlock Output 1
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add_interface_port m_src_axi m_src_axi_arcache arcache Output 4
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add_interface_port m_src_axi m_src_axi_arprot arprot Output 3
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add_interface_port m_src_axi m_src_axi_rid rid Input 1
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add_interface_port m_src_axi m_src_axi_rid rid Input 2
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add_interface_port m_src_axi m_src_axi_rlast rlast Input 1
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}
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