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adrv9009zu11eg: Added additional GPIOs and CS to the GPIO expander 

This should integrate seamlessly with SYNCHRONA14
main
Adrian Costina 2022-02-11 08:38:35 +00:00
parent 6c0a07c24b
commit d40db9e204
5 changed files with 88 additions and 68 deletions
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27
projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v
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@ -52,12 +52,14 @@ module system_top (
inout pmod0_d5, inout pmod0_d5,
inout pmod0_d6, inout pmod0_d6,
inout pmod0_d7, inout pmod0_d7,
output gpio_0_exp_n, //CS0n output gpio_0_exp_n, //CS_HMC7044
output gpio_0_exp_p, //MOSI output gpio_0_exp_p, //MOSI
input gpio_1_exp_n, //MISO input gpio_1_exp_n, //MISO
output gpio_1_exp_p, //SCK output gpio_1_exp_p, //SCK
output gpio_2_exp_n, //CS2n output gpio_2_exp_n, //CS_AD9545
output gpio_2_exp_p, //CS2p inout gpio_3_exp_n, //RESET_HMC7044
inout gpio_3_exp_p, //RESET_AD9545
inout gpio_4_exp_n, //VCXO_SELECT
output led_gpio_0, output led_gpio_0,
output led_gpio_1, output led_gpio_1,
output led_gpio_2, output led_gpio_2,
@ -265,10 +267,9 @@ module system_top (
assign spi_csn_hmc7044_car = spi_3_to_8_csn[3]; assign spi_csn_hmc7044_car = spi_3_to_8_csn[3];
assign gpio_0_exp_n = spi_3_to_8_csn[4]; assign gpio_0_exp_n = spi_3_to_8_csn[4];
assign gpio_1_exp_p = spi_clk; assign gpio_1_exp_p = spi_clk;
assign gpio_0_exp_p = spi_3_to_8_csn[4] == 1'b0 ? spi_mosi : 1'bZ; assign gpio_0_exp_p = spi_mosi;
assign spi_miso_s = spi_3_to_8_csn[4] == 1'b0 ? gpio_1_exp_n : spi_miso; assign spi_miso_s = ((spi_3_to_8_csn[4] == 1'b0) | (spi_3_to_8_csn[5] == 1'b0))? gpio_1_exp_n : spi_miso;
assign gpio_2_exp_n = spi_3_to_8_csn[5]; assign gpio_2_exp_n = spi_3_to_8_csn[5];
assign gpio_2_exp_p = spi_3_to_8_csn[6];
adrv9009zu11eg_spi i_spi ( adrv9009zu11eg_spi i_spi (
.spi_csn(spi_3_to_8_csn), .spi_csn(spi_3_to_8_csn),
@ -280,15 +281,18 @@ module system_top (
assign tx_sync = tx_sync_a & tx_sync_b; assign tx_sync = tx_sync_a & tx_sync_b;
assign gpio_i[94:90] = gpio_o[94:90]; assign gpio_i[94:93] = gpio_o[94:93];
assign gpio_i[31:28] = gpio_o[31:28]; assign gpio_i[31:28] = gpio_o[31:28];
assign gpio_i[21:20] = gpio_o[21:20]; assign gpio_i[21:20] = gpio_o[21:20];
ad_iobuf #(.DATA_WIDTH(58)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(61)) i_iobuf (
.dio_t ({gpio_t[89:32]}), .dio_t ({gpio_t[92:32]}),
.dio_i ({gpio_o[89:32]}), .dio_i ({gpio_o[92:32]}),
.dio_o ({gpio_i[89:32]}), .dio_o ({gpio_i[92:32]}),
.dio_p ({ .dio_p ({
gpio_4_exp_n, // 92
gpio_3_exp_n, // 91
gpio_3_exp_p, // 90
hmc7044_gpio_4, // 89 hmc7044_gpio_4, // 89
hmc7044_gpio_3, // 88 hmc7044_gpio_3, // 88
hmc7044_gpio_1, // 87 hmc7044_gpio_1, // 87
@ -462,7 +466,6 @@ module system_top (
.gpio_i (gpio_i), .gpio_i (gpio_i),
.gpio_o (gpio_o), .gpio_o (gpio_o),
.gpio_t (gpio_t), .gpio_t (gpio_t),
.ddr4_rtl_1_act_n(ddr4_rtl_1_act_n), .ddr4_rtl_1_act_n(ddr4_rtl_1_act_n),
.ddr4_rtl_1_adr(ddr4_rtl_1_adr), .ddr4_rtl_1_adr(ddr4_rtl_1_adr),
.ddr4_rtl_1_ba(ddr4_rtl_1_ba), .ddr4_rtl_1_ba(ddr4_rtl_1_ba),

26
projects/adrv9009zu11eg/adrv2crr_fmcomms8/system_top.v
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@ -52,12 +52,14 @@ module system_top (
inout pmod0_d5, inout pmod0_d5,
inout pmod0_d6, inout pmod0_d6,
inout pmod0_d7, inout pmod0_d7,
output gpio_0_exp_n, //CS0n output gpio_0_exp_n, //CS_HMC7044
output gpio_0_exp_p, //MOSI output gpio_0_exp_p, //MOSI
input gpio_1_exp_n, //MISO input gpio_1_exp_n, //MISO
output gpio_1_exp_p, //SCK output gpio_1_exp_p, //SCK
output gpio_2_exp_n, //CS2n output gpio_2_exp_n, //CS_AD9545
output gpio_2_exp_p, //CS2p inout gpio_3_exp_n, //RESET_HMC7044
inout gpio_3_exp_p, //RESET_AD9545
inout gpio_4_exp_n, //VCXO_SELECT
output led_gpio_0, output led_gpio_0,
output led_gpio_1, output led_gpio_1,
output led_gpio_2, output led_gpio_2,
@ -377,10 +379,9 @@ module system_top (
assign spi_csn_hmc7044_car = spi_3_to_8_csn[3]; assign spi_csn_hmc7044_car = spi_3_to_8_csn[3];
assign gpio_0_exp_n = spi_3_to_8_csn[4]; assign gpio_0_exp_n = spi_3_to_8_csn[4];
assign gpio_1_exp_p = spi_clk; assign gpio_1_exp_p = spi_clk;
assign gpio_0_exp_p = spi_3_to_8_csn[4] == 1'b0 ? spi_mosi : 1'bZ; assign gpio_0_exp_p = spi_mosi;
assign spi_miso_s = spi_3_to_8_csn[4] == 1'b0 ? gpio_1_exp_n : spi_miso; assign spi_miso_s = ((spi_3_to_8_csn[4] == 1'b0) | (spi_3_to_8_csn[5] == 1'b0))? gpio_1_exp_n : spi_miso;
assign gpio_2_exp_n = spi_3_to_8_csn[5]; assign gpio_2_exp_n = spi_3_to_8_csn[5];
assign gpio_2_exp_p = spi_3_to_8_csn[6];
assign spi_csn_adrv9009_c = spi_fmcomms8_3_to_8_csn[0]; assign spi_csn_adrv9009_c = spi_fmcomms8_3_to_8_csn[0];
assign spi_csn_adrv9009_d = spi_fmcomms8_3_to_8_csn[1]; assign spi_csn_adrv9009_d = spi_fmcomms8_3_to_8_csn[1];
@ -404,7 +405,7 @@ module system_top (
assign tx_sync = tx_sync_a & tx_sync_b & tx_sync_c & tx_sync_d; assign tx_sync = tx_sync_a & tx_sync_b & tx_sync_c & tx_sync_d;
assign gpio_i[94:90] = gpio_o[94:90]; assign gpio_i[94:93] = gpio_o[94:93];
assign gpio_i[31:28] = gpio_o[31:28]; assign gpio_i[31:28] = gpio_o[31:28];
assign gpio_i[21:20] = gpio_o[21:20]; assign gpio_i[21:20] = gpio_o[21:20];
@ -452,11 +453,14 @@ module system_top (
adrv9009_gpio_01_c, // 01 adrv9009_gpio_01_c, // 01
adrv9009_gpio_00_c})); // 00 adrv9009_gpio_00_c})); // 00
ad_iobuf #(.DATA_WIDTH(58)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(61)) i_iobuf (
.dio_t ({gpio_t[89:32]}), .dio_t ({gpio_t[92:32]}),
.dio_i ({gpio_o[89:32]}), .dio_i ({gpio_o[92:32]}),
.dio_o ({gpio_i[89:32]}), .dio_o ({gpio_i[92:32]}),
.dio_p ({ .dio_p ({
gpio_4_exp_n, // 92
gpio_3_exp_n, // 91
gpio_3_exp_p, // 90
hmc7044_gpio_4, // 89 hmc7044_gpio_4, // 89
hmc7044_gpio_3, // 88 hmc7044_gpio_3, // 88
hmc7044_gpio_2, // 87 hmc7044_gpio_2, // 87

30
projects/adrv9009zu11eg/adrv2crr_fmcxmwbr1/system_top.v
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@ -52,12 +52,14 @@ module system_top (
inout pmod0_d5, inout pmod0_d5,
inout pmod0_d6, inout pmod0_d6,
inout pmod0_d7, inout pmod0_d7,
output gpio_0_exp_n, //CS0n output gpio_0_exp_n, //CS_HMC7044
output gpio_0_exp_p, //MOSI output gpio_0_exp_p, //MOSI
input gpio_1_exp_n, //MISO input gpio_1_exp_n, //MISO
output gpio_1_exp_p, //SCK output gpio_1_exp_p, //SCK
output gpio_2_exp_n, //CS2n output gpio_2_exp_n, //CS_AD9545
output gpio_2_exp_p, //CS2p inout gpio_3_exp_n, //RESET_HMC7044
inout gpio_3_exp_p, //RESET_AD9545
inout gpio_4_exp_n, //VCXO_SELECT
output led_gpio_0, output led_gpio_0,
output led_gpio_1, output led_gpio_1,
output led_gpio_2, output led_gpio_2,
@ -274,7 +276,6 @@ module system_top (
inout dir_gpio7 inout dir_gpio7
); );
// internal signals // internal signals
wire [94:0] gpio_i; wire [94:0] gpio_i;
@ -303,6 +304,9 @@ module system_top (
wire tx_sync_b; wire tx_sync_b;
wire sysref_b; wire sysref_b;
wire tx_sync; wire tx_sync;
wire spi_mosi;
wire spi0_miso;
wire spi_miso_s;
reg [7:0] spi_3_to_8_csn; reg [7:0] spi_3_to_8_csn;
@ -325,10 +329,9 @@ module system_top (
assign spi_csn_hmc7044_car = spi_3_to_8_csn[3]; assign spi_csn_hmc7044_car = spi_3_to_8_csn[3];
assign gpio_0_exp_n = spi_3_to_8_csn[4]; assign gpio_0_exp_n = spi_3_to_8_csn[4];
assign gpio_1_exp_p = spi_clk; assign gpio_1_exp_p = spi_clk;
assign gpio_0_exp_p = spi_3_to_8_csn[4] == 1'b0 ? spi_mosi : 1'bZ; assign gpio_0_exp_p = spi_mosi;
assign spi_miso_s = spi_3_to_8_csn[4] == 1'b0 ? gpio_1_exp_n : spi_miso; assign spi_miso_s = ((spi_3_to_8_csn[4] == 1'b0) | (spi_3_to_8_csn[5] == 1'b0))? gpio_1_exp_n : spi_miso;
assign gpio_2_exp_n = spi_3_to_8_csn[5]; assign gpio_2_exp_n = spi_3_to_8_csn[5];
assign gpio_2_exp_p = spi_3_to_8_csn[6];
assign spi1_cs0 = spi1_csn[0]; assign spi1_cs0 = spi1_csn[0];
assign spi2_cs0 = spi2_csn[0]; assign spi2_cs0 = spi2_csn[0];
@ -343,7 +346,7 @@ module system_top (
assign tx_sync = tx_sync_a & tx_sync_b; assign tx_sync = tx_sync_a & tx_sync_b;
assign gpio_i[94:90] = gpio_o[94:90]; assign gpio_i[94:93] = gpio_o[94:93];
assign gpio_i[31:28] = gpio_o[31:28]; assign gpio_i[31:28] = gpio_o[31:28];
assign gpio_i[21:20] = gpio_o[21:20]; assign gpio_i[21:20] = gpio_o[21:20];
@ -385,11 +388,14 @@ module system_top (
gpio1, // 01 gpio1, // 01
gpio0})); // 00 gpio0})); // 00
ad_iobuf #(.DATA_WIDTH(58)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(61)) i_iobuf (
.dio_t ({gpio_t[89:32]}), .dio_t ({gpio_t[92:32]}),
.dio_i ({gpio_o[89:32]}), .dio_i ({gpio_o[92:32]}),
.dio_o ({gpio_i[89:32]}), .dio_o ({gpio_i[92:32]}),
.dio_p ({ .dio_p ({
gpio_4_exp_n, // 92
gpio_3_exp_n, // 91
gpio_3_exp_p, // 90
hmc7044_gpio_4, // 89 hmc7044_gpio_4, // 89
hmc7044_gpio_3, // 88 hmc7044_gpio_3, // 88
hmc7044_gpio_1, // 87 hmc7044_gpio_1, // 87

31
projects/adrv9009zu11eg/adrv2crr_xmicrowave/system_top.v
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@ -52,12 +52,14 @@ module system_top (
inout pmod0_d5, inout pmod0_d5,
inout pmod0_d6, inout pmod0_d6,
inout pmod0_d7, inout pmod0_d7,
output gpio_0_exp_n, //CS0n output gpio_0_exp_n, //CS_HMC7044
output gpio_0_exp_p, //MOSI output gpio_0_exp_p, //MOSI
input gpio_1_exp_n, //MISO input gpio_1_exp_n, //MISO
output gpio_1_exp_p, //SCK output gpio_1_exp_p, //SCK
output gpio_2_exp_n, //CS2n output gpio_2_exp_n, //CS_AD9545
output gpio_2_exp_p, //CS2p inout gpio_3_exp_n, //RESET_HMC7044
inout gpio_3_exp_p, //RESET_AD9545
inout gpio_4_exp_n, //VCXO_SELECT
output led_gpio_0, output led_gpio_0,
output led_gpio_1, output led_gpio_1,
output led_gpio_2, output led_gpio_2,
@ -274,7 +276,6 @@ module system_top (
inout dir_gpio7 inout dir_gpio7
); );
// internal signals // internal signals
wire [94:0] gpio_i; wire [94:0] gpio_i;
@ -303,6 +304,9 @@ module system_top (
wire tx_sync_b; wire tx_sync_b;
wire sysref_b; wire sysref_b;
wire tx_sync; wire tx_sync;
wire spi_mosi;
wire spi0_miso;
wire spi_miso_s;
reg [7:0] spi_3_to_8_csn; reg [7:0] spi_3_to_8_csn;
@ -325,10 +329,9 @@ module system_top (
assign spi_csn_hmc7044_car = spi_3_to_8_csn[3]; assign spi_csn_hmc7044_car = spi_3_to_8_csn[3];
assign gpio_0_exp_n = spi_3_to_8_csn[4]; assign gpio_0_exp_n = spi_3_to_8_csn[4];
assign gpio_1_exp_p = spi_clk; assign gpio_1_exp_p = spi_clk;
assign gpio_0_exp_p = spi_3_to_8_csn[4] == 1'b0 ? spi_mosi : 1'bZ; assign gpio_0_exp_p = spi_mosi;
assign spi_miso_s = spi_3_to_8_csn[4] == 1'b0 ? gpio_1_exp_n : spi_miso; assign spi_miso_s = ((spi_3_to_8_csn[4] == 1'b0) | (spi_3_to_8_csn[5] == 1'b0))? gpio_1_exp_n : spi_miso;
assign gpio_2_exp_n = spi_3_to_8_csn[5]; assign gpio_2_exp_n = spi_3_to_8_csn[5];
assign gpio_2_exp_p = spi_3_to_8_csn[6];
assign spi1_cs0 = spi1_csn[0]; assign spi1_cs0 = spi1_csn[0];
assign spi1_cs1 = spi1_csn[1]; assign spi1_cs1 = spi1_csn[1];
@ -358,7 +361,7 @@ module system_top (
assign tx_sync = tx_sync_a & tx_sync_b; assign tx_sync = tx_sync_a & tx_sync_b;
assign gpio_i[94:90] = gpio_o[94:90]; assign gpio_i[94:93] = gpio_o[94:93];
assign gpio_i[31:28] = gpio_o[31:28]; assign gpio_i[31:28] = gpio_o[31:28];
assign gpio_i[21:20] = gpio_o[21:20]; assign gpio_i[21:20] = gpio_o[21:20];
@ -386,11 +389,14 @@ module system_top (
gpio1, // 01 gpio1, // 01
gpio0})); // 00 gpio0})); // 00
ad_iobuf #(.DATA_WIDTH(58)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(61)) i_iobuf (
.dio_t ({gpio_t[89:32]}), .dio_t ({gpio_t[92:32]}),
.dio_i ({gpio_o[89:32]}), .dio_i ({gpio_o[92:32]}),
.dio_o ({gpio_i[89:32]}), .dio_o ({gpio_i[92:32]}),
.dio_p ({ .dio_p ({
gpio_4_exp_n, // 92
gpio_3_exp_n, // 91
gpio_3_exp_p, // 90
hmc7044_gpio_4, // 89 hmc7044_gpio_4, // 89
hmc7044_gpio_3, // 88 hmc7044_gpio_3, // 88
hmc7044_gpio_1, // 87 hmc7044_gpio_1, // 87
@ -564,7 +570,6 @@ module system_top (
.gpio_i (gpio_i), .gpio_i (gpio_i),
.gpio_o (gpio_o), .gpio_o (gpio_o),
.gpio_t (gpio_t), .gpio_t (gpio_t),
.ddr4_rtl_1_act_n(ddr4_rtl_1_act_n), .ddr4_rtl_1_act_n(ddr4_rtl_1_act_n),
.ddr4_rtl_1_adr(ddr4_rtl_1_adr), .ddr4_rtl_1_adr(ddr4_rtl_1_adr),
.ddr4_rtl_1_ba(ddr4_rtl_1_ba), .ddr4_rtl_1_ba(ddr4_rtl_1_ba),

4
projects/adrv9009zu11eg/common/adrv2crr_fmc_constr.xdc
View File

@ -32,7 +32,9 @@ set_property -dict {PACKAGE_PIN AL16 IOSTANDARD LVCMOS18} [get_ports gpio_0_exp
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS18} [get_ports gpio_1_exp_n] set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS18} [get_ports gpio_1_exp_n]
set_property -dict {PACKAGE_PIN AJ17 IOSTANDARD LVCMOS18} [get_ports gpio_1_exp_p] set_property -dict {PACKAGE_PIN AJ17 IOSTANDARD LVCMOS18} [get_ports gpio_1_exp_p]
set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS18} [get_ports gpio_2_exp_n] set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS18} [get_ports gpio_2_exp_n]
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS18} [get_ports gpio_2_exp_p] set_property -dict {PACKAGE_PIN AM15 IOSTANDARD LVCMOS18} [get_ports gpio_3_exp_p]
set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS18} [get_ports gpio_3_exp_n]
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS18} [get_ports gpio_4_exp_n]
set_property -dict {PACKAGE_PIN AR19 IOSTANDARD LVCMOS18} [get_ports resetb_ad9545] set_property -dict {PACKAGE_PIN AR19 IOSTANDARD LVCMOS18} [get_ports resetb_ad9545]
set_property -dict {PACKAGE_PIN AP19 IOSTANDARD LVCMOS18} [get_ports hmc7044_car_reset] set_property -dict {PACKAGE_PIN AP19 IOSTANDARD LVCMOS18} [get_ports hmc7044_car_reset]