projects: remove hardcoded div_clk from xcvr
LIacob106
LIacob106
parent
52df3c4937
commit
d4126739b4
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@ -31,6 +31,15 @@ set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18} [get_ports spi_csn_
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# clocks
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create_clock -name rx_ref_clk -period 8.00 [get_ports ref_clk0_p]
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# For transceiver output clocks use reference clock divided by two
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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create_generated_clock -name rx_div_clk [get_pins i_system_wrapper/system_i/util_ad9656_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
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# SYSREF input
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@ -80,6 +80,22 @@ set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18} [get_ports adrv9009_
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create_clock -name tx_ref_clk -period 4.00 [get_ports ref_clk0_p]
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create_clock -name rx_ref_clk -period 4.00 [get_ports ref_clk1_p]
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create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
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create_clock -name rx_os_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_2/i_gthe4_channel/RXOUTCLK]
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# For transceiver output clocks use reference clock
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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create_clock -name tx_div_clk [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
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create_clock -name rx_div_clk [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
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create_clock -name rx_os_div_clk [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_2/i_gthe4_channel/RXOUTCLK]
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@ -50,9 +50,24 @@ set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9371_gp
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create_clock -name tx_ref_clk -period 8.00 [get_ports ref_clk0_p]
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create_clock -name rx_ref_clk -period 8.00 [get_ports ref_clk1_p]
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create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
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create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gthe3_channel/RXOUTCLK]
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# For transceiver output clocks use reference clock
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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create_clock -name tx_div_clk [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
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create_clock -name rx_div_clk [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
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create_clock -name rx_os_div_clk [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gthe3_channel/RXOUTCLK]
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# gt pin assignments below are for reference only and are ignored by the tool!
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@ -52,9 +52,23 @@ set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports ad9371_gp
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create_clock -name tx_ref_clk -period 8.00 [get_ports ref_clk0_p]
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create_clock -name rx_ref_clk -period 8.00 [get_ports ref_clk1_p]
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create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
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create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gthe4_channel/RXOUTCLK]
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# For transceiver output clocks use reference clock
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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create_clock -name tx_div_clk [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
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create_clock -name rx_div_clk [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
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create_clock -name rx_os_div_clk [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gthe4_channel/RXOUTCLK]
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# pin assignments for JESD204 lanes and reference clocks
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@ -40,8 +40,23 @@ set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [g
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create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
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create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
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create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
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# For transceiver output clocks use reference clock divided by two
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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create_clock -name tx_div_clk [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
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create_clock -name rx_div_clk [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
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# gt pin assignments below are for reference only and are ignored by the tool!
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@ -38,8 +38,23 @@ set_property LOC GTHE4_COMMON_X1Y2 [get_cells -hierarchical -filter {NAME =~ *i_
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create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
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create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
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create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
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# For transceiver output clocks use reference clock divided by two
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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create_clock -name tx_div_clk [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
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create_clock -name rx_div_clk [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
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# pin assignments below are for reference only and are ignored by the tool!
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@ -40,8 +40,23 @@ set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [g
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create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p]
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create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
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create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
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# For transceiver output clocks use reference clock divided by two
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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create_clock -name tx_div_clk [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
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create_clock -name rx_div_clk [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
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# gt pin assignments below are for reference only and are ignored by the tool!
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@ -56,6 +56,21 @@ set_property -dict {PACKAGE_PIN AP43} [get_ports tx_data_n[3]]
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## clocks
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create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p]
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create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
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create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtye4_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtye4_channel/RXOUTCLK]
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# For transceiver output clocks use reference clock divided by two
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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create_clock -name tx_div_clk [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtye4_channel/TXOUTCLK]
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create_clock -name rx_div_clk [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtye4_channel/RXOUTCLK]
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@ -45,8 +45,23 @@ set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100}
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create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p]
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create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
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create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
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# For transceiver output clocks use reference clock divided by two
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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create_clock -name tx_div_clk [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
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create_clock -name rx_div_clk [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
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# pin assignments below are for reference only and are ignored by the tool!
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