From d41945f568f1a57bb2abe8fc8850722ee21a1770 Mon Sep 17 00:00:00 2001
From: AndreiGrozav <andrei.grozav@analog.com>
Date: Tue, 11 Oct 2016 17:02:46 +0300
Subject: [PATCH] altera/ad_serdes: Add support for any SERDES factor less than
 8

---
 library/altera/common/ad_serdes_in.v  | 33 ++++++++++++++++-------
 library/altera/common/ad_serdes_out.v | 39 ++++++++++++++++++++-------
 2 files changed, 54 insertions(+), 18 deletions(-)

diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v
index a84bb0c8c..20716cf1e 100644
--- a/library/altera/common/ad_serdes_in.v
+++ b/library/altera/common/ad_serdes_in.v
@@ -43,6 +43,7 @@ module ad_serdes_in #(
   // parameters
 
   parameter   DEVICE_TYPE = 0,
+  parameter   SERDES_FACTOR = 8,
   parameter   DATA_WIDTH = 16) (
 
   // reset and clocks
@@ -83,17 +84,31 @@ module ad_serdes_in #(
   // internal signals
 
   wire    [(DATA_WIDTH-1):0]      delay_locked_s;
+  wire    [(DATA_WIDTH-1):0]      data_out_s[ 7:0];
+  wire    [(DATA_WIDTH-1):0]      data_sel_s[ 7:0];
 
   // assignments
 
   assign up_drdata = 5'd0;
   assign delay_locked = & delay_locked_s;
 
+  assign data_s0 = data_sel_s[0];
+  assign data_s1 = data_sel_s[1];
+  assign data_s2 = data_sel_s[2];
+  assign data_s3 = data_sel_s[3];
+  assign data_s4 = data_sel_s[4];
+  assign data_s5 = data_sel_s[5];
+  assign data_s6 = data_sel_s[6];
+  assign data_s7 = data_sel_s[7];
+
   // instantiations
 
-  genvar l_inst;
+  genvar l_inst, l_order;
   generate
   for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
+    for (l_order = 0; l_order < SERDES_FACTOR; l_order = l_order + 1) begin: g_order
+      assign data_sel_s[l_order][l_inst] = data_out_s[8 - SERDES_FACTOR + l_order][l_inst];
+    end
   alt_serdes_in_core i_core (
     .clk_export (clk),
     .div_clk_export (div_clk),
@@ -101,14 +116,14 @@ module ad_serdes_in #(
     .loaden_export (loaden),
     .locked_export (locked),
     .data_in_export (data_in_p[l_inst]),
-    .data_s_export ({ data_s0[l_inst],
-                      data_s1[l_inst],
-                      data_s2[l_inst],
-                      data_s3[l_inst],
-                      data_s4[l_inst],
-                      data_s5[l_inst],
-                      data_s6[l_inst],
-                      data_s7[l_inst]}),
+    .data_s_export ({data_out_s[0][l_inst],
+                     data_out_s[1][l_inst],
+                     data_out_s[2][l_inst],
+                     data_out_s[3][l_inst],
+                     data_out_s[4][l_inst],
+                     data_out_s[5][l_inst],
+                     data_out_s[6][l_inst],
+                     data_out_s[7][l_inst]}),
     .delay_locked_export (delay_locked_s[l_inst]));
   end
   endgenerate
diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v
index c5a9ac648..6857b5fd5 100644
--- a/library/altera/common/ad_serdes_out.v
+++ b/library/altera/common/ad_serdes_out.v
@@ -41,6 +41,7 @@
 module ad_serdes_out #(
 
   parameter   DEVICE_TYPE = 0,
+  parameter   SERDES_FACTOR = 8,
   parameter   DATA_WIDTH = 16) (
 
   // reset and clocks
@@ -63,29 +64,49 @@ module ad_serdes_out #(
   output  [(DATA_WIDTH-1):0]  data_out_p,
   output  [(DATA_WIDTH-1):0]  data_out_n);
 
+  // internal signals
+
+  wire    [(DATA_WIDTH-1):0]  data_in_s[ 7:0];
+  wire    [(DATA_WIDTH-1):0]  data_in_s2[ 7:0];
+
   // defaults
 
   assign data_out_n = 'd0;
 
   // instantiations
 
+    assign data_in_s[0] = data_s0;
+    assign data_in_s[1] = data_s1;
+    assign data_in_s[2] = data_s2;
+    assign data_in_s[3] = data_s3;
+    assign data_in_s[4] = data_s4;
+    assign data_in_s[5] = data_s5;
+    assign data_in_s[6] = data_s6;
+    assign data_in_s[7] = data_s7;
+
+  genvar l_order;
+  generate
+    for (l_order = 0; l_order < 8; l_order = l_order + 1) begin: g_order
+      assign data_in_s2[l_order] = (l_order < 8-SERDES_FACTOR) ? 1'b0 : data_in_s[l_order -8 + SERDES_FACTOR];
+    end
+  endgenerate
+
   genvar l_inst;
   generate
   for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
-
     alt_serdes_out_core i_core (
       .clk_export (clk),
       .div_clk_export (div_clk),
       .loaden_export (loaden),
       .data_out_export (data_out_p[l_inst]),
-      .data_s_export ({ data_s0[l_inst],
-                        data_s1[l_inst],
-                        data_s2[l_inst],
-                        data_s3[l_inst],
-                        data_s4[l_inst],
-                        data_s5[l_inst],
-                        data_s6[l_inst],
-                        data_s7[l_inst]}));
+      .data_s_export ({data_in_s2[0][l_inst],
+                       data_in_s2[1][l_inst],
+                       data_in_s2[2][l_inst],
+                       data_in_s2[3][l_inst],
+                       data_in_s2[4][l_inst],
+                       data_in_s2[5][l_inst],
+                       data_in_s2[6][l_inst],
+                       data_in_s2[7][l_inst]}));
   end
   endgenerate