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axi_pulse_gen_regmap: Rename the clk output to clk_out

main
Istvan Csomortani 2019-07-18 08:36:41 +01:00 committed by István Csomortáni
parent f1403aa593
commit d4200aee9a
2 changed files with 8 additions and 8 deletions
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2
library/axi_pulse_gen/axi_pulse_gen.v
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@ -104,7 +104,7 @@ module axi_pulse_gen #(
.PULSE_PERIOD (PULSE_PERIOD)) .PULSE_PERIOD (PULSE_PERIOD))
i_regmap ( i_regmap (
.ext_clk (ext_clk), .ext_clk (ext_clk),
.clk (clk), .clk_out (clk),
.pulse_gen_resetn (pulse_gen_resetn), .pulse_gen_resetn (pulse_gen_resetn),
.pulse_width (pulse_width_s), .pulse_width (pulse_width_s),
.pulse_period (pulse_period_s), .pulse_period (pulse_period_s),

14
library/axi_pulse_gen/axi_pulse_gen_regmap.v
View File

@ -49,7 +49,7 @@ module axi_pulse_gen_regmap #(
// control and status signals // control and status signals
output clk, output clk_out,
output pulse_gen_resetn, output pulse_gen_resetn,
output [31:0] pulse_width, output [31:0] pulse_width,
output [31:0] pulse_period, output [31:0] pulse_period,
@ -131,11 +131,11 @@ module axi_pulse_gen_regmap #(
generate generate
if (ASYNC_CLK_EN) begin : counter_external_clock if (ASYNC_CLK_EN) begin : counter_external_clock
assign clk = ext_clk; assign clk_out = ext_clk;
ad_rst i_d_rst_reg ( ad_rst i_d_rst_reg (
.rst_async (up_reset), .rst_async (up_reset),
.clk (clk), .clk (clk_out),
.rstn (pulse_gen_resetn), .rstn (pulse_gen_resetn),
.rst ()); .rst ());
@ -145,7 +145,7 @@ module axi_pulse_gen_regmap #(
i_pulse_period_sync ( i_pulse_period_sync (
.in_clk (up_clk), .in_clk (up_clk),
.in_data (up_pulse_period), .in_data (up_pulse_period),
.out_clk (clk), .out_clk (clk_out),
.out_data (pulse_period)); .out_data (pulse_period));
sync_data #( sync_data #(
@ -154,7 +154,7 @@ module axi_pulse_gen_regmap #(
i_pulse_width_sync ( i_pulse_width_sync (
.in_clk (up_clk), .in_clk (up_clk),
.in_data (up_pulse_width), .in_data (up_pulse_width),
.out_clk (clk), .out_clk (clk_out),
.out_data (pulse_width)); .out_data (pulse_width));
sync_event #( sync_event #(
@ -163,12 +163,12 @@ module axi_pulse_gen_regmap #(
i_load_config_sync ( i_load_config_sync (
.in_clk (up_clk), .in_clk (up_clk),
.in_event (up_load_config), .in_event (up_load_config),
.out_clk (clk), .out_clk (clk_out),
.out_event (load_config)); .out_event (load_config));
end else begin : counter_sys_clock // counter is running on system clk end else begin : counter_sys_clock // counter is running on system clk
assign clk = up_clk; assign clk_out = up_clk;
assign pulse_gen_resetn = ~up_reset; assign pulse_gen_resetn = ~up_reset;
assign pulse_period = up_pulse_period; assign pulse_period = up_pulse_period;
assign pulse_width = up_pulse_width; assign pulse_width = up_pulse_width;