Add util_sigma_delta_spi peripheral

The util_sigma_delta_spi peripheral can be used to seperate the interleaved
SPI bus and DRDY signals for a ADC from the Analog Devices SigmaDelta
family.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2015-04-14 10:51:37 +02:00
parent e6b58e8a20
commit d43ba44d0f
4 changed files with 153 additions and 0 deletions

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@ -59,6 +59,7 @@ clean:
make -C util_pmod_adc clean
make -C util_pmod_fmeter clean
make -C util_rfifo clean
make -C util_sigma_delta_spi clean
make -C util_upack clean
make -C util_wfifo clean
@ -116,6 +117,7 @@ lib:
-make -C util_pmod_adc
-make -C util_pmod_fmeter
-make -C util_rfifo
-make -C util_sigma_delta_spi
-make -C util_upack
-make -C util_wfifo

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@ -0,0 +1,42 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := util_sigma_delta_spi_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += util_sigma_delta_spi.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
.PHONY: all clean clean-all
all: util_sigma_delta_spi.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
util_sigma_delta_spi.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) util_sigma_delta_spi_ip.tcl >> util_sigma_delta_spi_ip.log 2>&1
####################################################################################
####################################################################################

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@ -0,0 +1,74 @@
module util_sigma_delta_spi (
input clk,
input resetn,
input spi_active,
input s_sclk,
input s_sdo,
input s_sdo_t,
output s_sdi,
input [NUM_CS-1:0] s_cs,
output m_sclk,
output m_sdo,
output m_sdo_t,
input m_sdi,
output [NUM_CS-1:0] m_cs,
output reg data_ready
);
parameter NUM_CS = 1;
parameter CS_PIN = 0;
parameter IDLE_TIMEOUT = 63;
/*
* For converters from the ADI SigmaDelta family the data ready interrupt signal
* uses the same physical wire as the the DOUT signal for the SPI bus. This
* module extracts the data ready signal from the SPI bus and makes sure to
* suppress false positives. The data ready signal is indicated by the converter
* by pulling DOUT low. This will only happen if the CS pin for the converter is
* low and no SPI transfer is active. There is a small delay between the end of
* the SPI transfer and the point where the converter starts to indicate the
* data ready signal. IDLE_TIMEOUT allows to specify the amount of clock cycles
* the bus needs to be idle before the data ready signal is detected.
*/
assign m_sclk = s_sclk;
assign m_sdo = s_sdo;
assign m_sdo_t = s_sdo_t;
assign s_sdi = m_sdi;
assign m_cs = s_cs;
reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT;
reg [2:0] sdi_d = 'h00;
always @(posedge clk) begin
if (resetn == 1'b0) begin
counter <= IDLE_TIMEOUT;
end else begin
if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
if (counter != 'h00)
counter <= counter - 1'b1;
end else begin
counter <= IDLE_TIMEOUT;
end
end
end
always @(posedge clk) begin
/* The data ready signal is fully asynchronous */
sdi_d <= {sdi_d[1:0], m_sdi};
end
always @(posedge clk) begin
if (counter == 'h00 && sdi_d[2] == 1'b0) begin
data_ready <= 1'b1;
end else begin
data_ready <= 1'b0;
end
end
endmodule

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@ -0,0 +1,35 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_sigma_delta_spi
adi_ip_files util_sigma_delta_spi [list \
"util_sigma_delta_spi.v" \
]
adi_ip_properties_lite util_sigma_delta_spi
adi_add_bus "m_spi" "master" \
"analog.com:interface:spi_master_rtl:1.0" \
"analog.com:interface:spi_master:1.0" \
{
{"m_sclk" "SCLK"} \
{"m_sdi" "SDI"} \
{"m_sdo" "SDO"} \
{"m_sdo_t" "SDO_T"} \
{"m_cs" "CS"} \
}
adi_add_bus "s_spi" "slave" \
"analog.com:interface:spi_master_rtl:1.0" \
"analog.com:interface:spi_master:1.0" \
{
{"s_sclk" "SCLK"} \
{"s_sdi" "SDI"} \
{"s_sdo" "SDO"} \
{"s_sdo_t" "SDO_T"} \
{"s_cs" "CS"} \
}
adi_add_bus_clock "clk" "m_spi:s_spi" "resetn"
ipx::save_core [ipx::current_core]