axi_ad9963: Integrated ADC/DAC clock enables

library/axi_ad9963/axi_ad9963.v

@@ -154,6 +154,8 @@ module axi_ad9963 #(
   wire            up_rack_rx_s;
   wire    [31:0]  up_rdata_tx_s;
   wire            up_rack_tx_s;
+  wire            up_adc_ce;
+  wire            up_dac_ce;
 
   // signal name changes
 
@@ -188,8 +190,10 @@ module axi_ad9963 #(
     .adc_valid (adc_valid_s),
     .adc_data (adc_data_s),
     .adc_status (adc_status_s),
+    .up_adc_ce(up_adc_ce),
     .dac_valid (dac_valid_s),
     .dac_data (dac_data_s),
+    .up_dac_ce(up_dac_ce),
     .up_clk (up_clk),
     .up_adc_dld (up_adc_dld_s),
     .up_adc_dwdata (up_adc_dwdata_s),
@@ -210,6 +214,7 @@ module axi_ad9963 #(
     .adc_valid (adc_valid_s),
     .adc_data (adc_data_s),
     .adc_status (adc_status_s),
+    .up_adc_ce(up_adc_ce),
     .up_dld (up_adc_dld_s),
     .up_dwdata (up_adc_dwdata_s),
     .up_drdata (up_adc_drdata_s),
@@ -256,6 +261,7 @@ module axi_ad9963 #(
     .dac_data_q (dac_data_q),
     .dac_dovf(dac_dovf),
     .dac_dunf(dac_dunf),
+    .up_dac_ce(up_dac_ce),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_wreq (up_wreq_s),

library/axi_ad9963/axi_ad9963_constr.xdc

@@ -0,0 +1 @@
+set_false_path -from [get_cells -hier -filter {name =~ *up_*ce_reg*      && IS_SEQUENTIAL}] -to [get_pins -hier -filter {name =~ *bufgctrl*/S0}]

library/axi_ad9963/axi_ad9963_if.v

@@ -24,9 +24,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// This interface includes both the transmit and receive components -
-// They both uses the same clock (sourced from the receiving side).
-// assumes RX_IQ is 1 for I and 0 for Q (RX_IFIRST = 1 , RXIQ_HILO = 1)
 
 `timescale 1ns/100ps
 
@@ -62,21 +59,23 @@ module axi_ad9963_if #(
   output reg          adc_valid,
   output reg  [23:0]  adc_data,
   output reg          adc_status,
+  input               up_adc_ce,
 
   // transmit data path interface
 
-  input           dac_valid,
+  input               dac_valid,
-  input   [23:0]  dac_data,
+  input       [23:0]  dac_data,
+  input               up_dac_ce,
 
   // delay interface
 
-  input           up_clk,
+  input               up_clk,
-  input   [12:0]  up_adc_dld,
+  input       [12:0]  up_adc_dld,
-  input   [64:0]  up_adc_dwdata,
+  input       [64:0]  up_adc_dwdata,
-  output  [64:0]  up_adc_drdata,
+  output      [64:0]  up_adc_drdata,
-  input           delay_clk,
+  input               delay_clk,
-  input           delay_rst,
+  input               delay_rst,
-  output          delay_locked);
+  output              delay_locked);
 
   // internal registers
 
@@ -101,7 +100,7 @@ module axi_ad9963_if #(
       adc_valid <= 1'b1;                        // data[23:12] Q
     end else begin
       rx_data_p <= rx_data_p_s;               // if this happens it means that risedge data is sampled on falledge
-      adc_data  <= {rx_data_p, rx_data_n_s} ;  // so we take current N data with previous P data
+      adc_data  <= {rx_data_p, rx_data_n_s};  // so we take current N data with previous P data
       adc_valid <= 1'b1;                      // in order to have data sampled at the same instance sent to the DMA
     end
   end
@@ -123,9 +122,22 @@ module axi_ad9963_if #(
 
   // device clock interface (receive clock)
 
-  BUFG i_clk_gbuf (
+  BUFGCTRL #(
-    .I (trx_clk),
+      .INIT_OUT(0),
-    .O (adc_clk));
+      .PRESELECT_I0("FALSE"),
+      .PRESELECT_I1("FALSE")
+      )
+  bufgctrl_adc (
+      .O(adc_clk),
+      .CE0(1'b1),
+      .CE1(1'b0),
+      .I0(trx_clk),
+      .I1(1'b0),
+      .IGNORE0(1'b0),
+      .IGNORE1(1'b0),
+      .S0(up_adc_ce),
+      .S1(1'b0)
+      );
 
   // receive data interface, ibuf -> idelay -> iddr
 
@@ -183,9 +195,22 @@ module axi_ad9963_if #(
     .I (tx_clk),
     .O (div_clk));
 
-  BUFG dac_bufg (
+  BUFGCTRL #(
-    .I(div_clk),
+    .INIT_OUT(0),
-    .O(dac_clk));
+    .PRESELECT_I0("FALSE"),
+    .PRESELECT_I1("FALSE")
+    )
+  bufgctrl_dac (
+    .O(dac_clk),
+    .CE0(1'b1),
+    .CE1(1'b0),
+    .I0(div_clk),
+    .I1(1'b0),
+    .IGNORE0(1'b0),
+    .IGNORE1(1'b0),
+    .S0(up_dac_ce),
+    .S1(1'b0)
+    );
 
   generate
   for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data

library/axi_ad9963/axi_ad9963_ip.tcl

@@ -28,6 +28,7 @@ adi_ip_files axi_ad9963 [list \
   "$ad_hdl_dir/library/common/up_adc_channel.v" \
   "$ad_hdl_dir/library/common/up_dac_common.v" \
   "$ad_hdl_dir/library/common/up_dac_channel.v" \
+  "axi_ad9963_constr.xdc" \
   "axi_ad9963_if.v" \
   "axi_ad9963_rx_pnmon.v" \
   "axi_ad9963_rx_channel.v" \
@@ -44,7 +45,6 @@ set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_cor
 
 ipx::remove_bus_interface rst [ipx::current_core]
 ipx::remove_bus_interface clk [ipx::current_core]
-ipx::remove_bus_interface l_clk [ipx::current_core]
 ipx::remove_bus_interface delay_clk [ipx::current_core]
 
 ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \

library/axi_ad9963/axi_ad9963_rx.v

@@ -73,6 +73,8 @@ module axi_ad9963_rx #(
   input               adc_dovf,
   input               adc_dunf,
 
+  output              up_adc_ce,
+
   // processor interface
 
   input               up_rstn,
@@ -221,6 +223,7 @@ module axi_ad9963_rx #(
     .adc_usr_chanmax (8'd1),
     .up_adc_gpio_in (32'h0),
     .up_adc_gpio_out (),
+    .up_adc_ce(up_adc_ce),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_wreq (up_wreq),

library/axi_ad9963/axi_ad9963_tx.v

@@ -68,6 +68,8 @@ module axi_ad9963_tx #(
   input               dac_dovf,
   input               dac_dunf,
 
+  output              up_dac_ce,
+
   // processor interface
 
   input               up_rstn,
@@ -81,16 +83,10 @@ module axi_ad9963_tx #(
   output reg  [31:0]  up_rdata,
   output reg          up_rack);
 
-  // internal registers
-
-  reg             dac_data_sync = 'd0;
-  reg     [ 7:0]  dac_rate_cnt = 'd0;
-
   // internal signals
 
   wire            dac_data_sync_s;
   wire            dac_dds_format_s;
-  wire    [ 7:0]  dac_datarate_s;
   wire    [23:0]  dac_data_int_s;
   wire    [31:0]  up_rdata_s[0:2];
   wire            up_rack_s[0:2];
@@ -100,26 +96,18 @@ module axi_ad9963_tx #(
 
   assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
 
-  always @(posedge dac_clk) begin
-    dac_data_sync <= dac_data_sync_s;
-  end
-
-  // rate counters and data sync signals
-
-  always @(posedge dac_clk) begin
-    if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 8'd0)) begin
-      dac_rate_cnt <= dac_datarate_s;
-    end else begin
-      dac_rate_cnt <= dac_rate_cnt - 1'b1;
-    end
-  end
-
   // dma interface
 
   always @(posedge dac_clk) begin
-    dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
+    if (dac_rst == 1'b1) begin
-    dac_valid_i <= dac_valid;
+      dac_valid <= 1'b0;
-    dac_valid_q <= dac_valid;
+      dac_valid_i <= 1'b0;
+      dac_valid_q <= 1'b0;
+    end else begin
+      dac_valid <= 1'b1;
+      dac_valid_i <= dac_valid;
+      dac_valid_q <= dac_valid;
+    end
   end
 
   // processor read interface
@@ -146,7 +134,7 @@ module axi_ad9963_tx #(
     .dac_data_out (dac_data_int_s[11:0]),
     .dac_data_in (dac_data_int_s[23:12]),
     .dac_enable (dac_enable_i),
-    .dac_data_sync (dac_data_sync),
+    .dac_data_sync (dac_data_sync_s),
     .dac_dds_format (dac_dds_format_s),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
@@ -175,7 +163,7 @@ module axi_ad9963_tx #(
     .dac_data_out (dac_data_int_s[23:12]),
     .dac_data_in (dac_data_int_s[11:0]),
     .dac_enable (dac_enable_q),
-    .dac_data_sync (dac_data_sync),
+    .dac_data_sync (dac_data_sync_s),
     .dac_dds_format (dac_dds_format_s),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
@@ -206,11 +194,12 @@ module axi_ad9963_tx #(
     .dac_par_enb (),
     .dac_r1_mode (),
     .dac_datafmt (dac_dds_format_s),
-    .dac_datarate (dac_datarate_s),
+    .dac_datarate (),
     .dac_status (1'b1),
     .dac_status_ovf (dac_dovf),
     .dac_status_unf (dac_dunf),
     .dac_clk_ratio (32'd1),
+    .up_dac_ce(up_dac_ce),
     .up_drp_sel (),
     .up_drp_wr (),
     .up_drp_addr (),